MX29F040QC-90 Macronix International Co., MX29F040QC-90 Datasheet

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MX29F040QC-90

Manufacturer Part Number
MX29F040QC-90
Description
Manufacturer
Macronix International Co.
Datasheet

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FEATURES
• 524,288 x 8 only
• Single power supply operation
• Fast access time: 55/70/90/120ns
• Low power consumption
• Command register architecture
• Auto Erase (chip & sector) and Auto Program
• Erase suspend/Erase Resume
GENERAL DESCRIPTION
The MX29F040 is a 4-mega bit Flash memory organized
as 512K bytes of 8 bits. MXIC's Flash memories offer
the most cost-effective and reliable read/write non-vola-
tile random access memory. The MX29F040 is pack-
aged in 32-pin PLCC, TSOP, PDIP. It is designed to be
reprogrammed and erased in system or in standard
EPROM programmers.
The standard MX29F040 offers access time as fast as
55ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F040 has separate chip enable (CE) and output
enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F040 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
P/N:PM0538
- 5.0V only operation for read, erase and program op-
eration
- 30mA maximum active current(5MHz)
- 1uA typical standby current
- Byte Programming (7us typical)
- Sector Erase
8 equal sectors of 64K-Byte each
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
- Suspends an erase operation to read data from, or
4M-BIT [512KX8] CMOS EQUAL SECTOR FLASH MEMORY
1
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F040 uses a 5.0V 10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
• Status Reply
• Sector protect/unprotect for 5V only system or 5V/
• Sector protection
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
• Compatibility with JEDEC standard
• 20 years data retention
program data to, another sector that is not being
erased, then resumes the erase.
- Data polling & Toggle bit for detection of program
and erase cycle completion.
12V system.
- Hardware method to disable any combination of
sectors from program or erase operations
- 32-pin PLCC, TSOP or PDIP
- Pinout and software compatible with single-power
supply Flash
MX29F040
REV. 2.3, DEC. 10, 2004

Related parts for MX29F040QC-90

MX29F040QC-90 Summary of contents

Page 1

FEATURES • 524,288 x 8 only • Single power supply operation - 5.0V only operation for read, erase and program op- eration • Fast access time: 55/70/90/120ns • Low power consumption - 30mA maximum active current(5MHz) - 1uA typical standby ...

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PIN CONFIGURATIONS 32 PDIP A18 1 32 A16 31 2 A15 3 30 A12 ...

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BLOCK DIAGRAM CONTROL CE INPUT OE LOGIC WE ADDRESS LATCH A0-A18 AND BUFFER Q0-Q7 P/N:PM0538 PROGRAM/ERASE HIGH VOLTAGE MX29F040 FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 3 MX29F040 WRITE STATE ...

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AUTOMATIC PROGRAMMING The MX29F040 is byte programmable using the Auto- matic Programming algorithm. The Automatic Program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. The typical chip ...

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TABLE 1. SOFTWARE COMMAND DEFINITIONS First Bus Command Bus Cycle Cycle Addr Reset 1 XXXH F0H Read 1 RA Read Silicon ID 4 555H Sector Protect Verify 4 555H Program 4 555H Chip Erase 6 555H Sector Erase 6 555H ...

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TABLE 2. MX29F040 BUS OPERATION Mode Pins CE Read Silicon ID L Manufacturer Code(1) Read Silicon ID L Device Code(1) Read L Standby H Output Disable L Write L Sector Protect with 12V L system(6) Chip Unprotect with 12V L ...

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READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command reg- ister. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. If ...

Page 8

SECTOR ERASE COMMANDS The Automatic Sector Erase does not require the device to be entirely pre-programmed prior to executing the Au- tomatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device ...

Page 9

ERASE SUSPEND This command only has meaning while the state ma- chine is executing Automatic Sector Erase operation, and therefore will only be responded during Automatic Sector Erase operation. When the Erase Suspend com- mand is written during a sector ...

Page 10

Q6:Toggle BIT I Toggle Bit indicates whether an Automatic Pro- gram or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ...

Page 11

Q5 Exceeded Timing Limits Q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). Under these conditions Q5 will produce a "1". This time-out condition indicates that the program or erase cycle ...

Page 12

SECTOR PROTECTION WITH 12V SYSTEM The MX29F040 features sector protection. This feature will disable both program and erase operations for these sectors protected. To activate this mode, the program- ming equipment must force VID on address pin A9 and control ...

Page 13

CAPACITANCE ( 1.0 MHz) SYMBOL PARAMETER CIN1 Input Capacitance CIN2 Control Pin Capacitance COUT Output Capacitance READ OPERATION ° DC CHARACTERISTICS ( SYMBOL PARAMETER ILI Input Leakage Current ILO ...

Page 14

ABSOLUTE MAXIMUM RATINGS RATING Ambient Operating Temperature Storage Temperature Ambient Temperature with Power -55 Applied Applied Input Voltage Applied Output Voltage VCC to Ground Potential A9 & OE READ TIMING WAVEFORMS VIH Addresses VIL VIH CE VIL VIH WE VIL ...

Page 15

AC CHARACTERISTICS SYMBOL PARAMETER tOES OE setup time tCWC Command programming cycle tCEP WE programming pulse width tCEPH1 WE programming pulse width High tCEPH2 WE programming pulse width High tAS Address setup time tAH Address hold time ...

Page 16

SWITCHING TEST CIRCUITS DEVICE UNDER TEST SWITCHING TEST WAVEFORMS 2.4V 0.45V AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0". Input pulse rise and fall times are < 20ns.(5ns for 29F040-55) Note:VIH/VIL=3.0/0V,VOH/VOL=1.5/1.5V ...

Page 17

AUTOMATIC PROGRAMMING TIMING WAVEFORM One byte data is programmed. Verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. Programming completion can be verified by DATA ...

Page 18

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Toggle Bit Checking NO Invalid Command Auto Program Completed P/N:PM0538 START NO Q6 not Toggled YES Verify Byte ...

Page 19

AUTOMATIC CHIP ERASE TIMING WAVEFORM All data in chip are erased. External erase verification is not required because data is erased automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit checking after AUTOMATIC ...

Page 20

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address 555H NO Invalid Command Auto Chip ...

Page 21

AUTOMATIC SECTOR ERASE TIMING WAVEFORM Sector data indicated by A16 to A18 are erased. External erase verify is not required because data are erased automatically by internal control circuit. Erasure comple- tion can be verified by DATA polling and toggle ...

Page 22

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector Address Load Other Sector Addrss If ...

Page 23

ERASE SUSPEND/ERASE RESUME FLOWCHART P/N:PM0538 START Write Data B0H NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H Continue Erase Another . NO Erase Suspend ? YES 23 ...

Page 24

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V A1 A6 12V 5V A9 tVLHT 12V 5V OE tVLHT WE CE Data A18-A16 P/N:PM0538 tWPP 1 tOESP Sector Address 24 MX29F040 Verify tVLHT 01H F0H tOE REV. 2.3, DEC. 10, ...

Page 25

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V A1 12V 5V A9 tVLHT A6 12V 5V OE tVLHT WE tOESP CE Data P/N:PM0538 Verify tVLHT tWPP 2 tOE 25 MX29F040 00H F0H REV. 2.3, DEC. 10, 2004 ...

Page 26

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V No PLSCNT=32? Yes Device Failed P/N:PM0538 START Set Up Sector Addr (A18, A17, A16) PLSCNT=1 OE=VID,A9=VID,CE=VIL A6=VIL Activate WE Pulse Time Out 10us Set WE=VIH, CE=OE=VIL A9 should remain VID Read from Sector ...

Page 27

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0538 START Protect All Sectors PLSCNT=1 Set OE=A9=VID CE=VIL,A6=1 Activate WE Pulse Time Out 12ms ...

Page 28

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V tCEP WE CE Data Don't care (Note 2) A18-A16 Note1: Must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12V provided. Note2: ...

Page 29

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V tCEP WE CE Data Don't care (Note 2) Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12V provided. Note2: Except ...

Page 30

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment PLSCNT No PLSCNT=32? Yes Device Failed P/N:PM0538 START PLSCNT=1 Write "unlock for sector protect/unprotect" Command(Table1) Set Up Sector Addr (A18, A17, A16) OE=VIH,A9=VIH CE=VIL,A6=VIL Activate WE Pulse to start Data don't care ...

Page 31

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V Increment Sector Addr * It is recommended before unprotect whole chip, all sectors should be protected in advance. P/N:PM0538 START Protect All Sectors PLSCNT=1 Write "unlock for sector protect/unprotect" Command (Table 1) Set ...

Page 32

ID CODE READ TIMING WAVEFORM VCC 5V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC A1 VIH VIL ADD VIH A2-A8 A10-A18 VIL CE VIH VIL VIH WE VIL VIH OE VIL VIH DATA VIL Q0-Q7 P/N:PM0538 tACC ...

Page 33

ERASE AND PROGRAMMING PERFORMANCE (1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Chip Programming Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured at 25 C,5V. 3.Maximunm values measured at ...

Page 34

... Access Time Operating Current Standby Current Temperature (ns) MX29F040QC-55 55 MX29F040QC-70 70 MX29F040QC-90 90 MX29F040QC-12 120 MX29F040TC-55 55 MX29F040TC-70 70 MX29F040TC-90 90 MX29F040TC-12 120 MX29F040PC-55 55 MX29F040PC-70 70 MX29F040PC-90 90 MX29F040PC-12 120 MX29F040QC-55G 55 MX29F040QC-70G 70 MX29F040QC-90G 90 MX29F040TC-55G 55 MX29F040TC-70G 70 MX29F040TC-90G 90 MX29F040TC-12G 120 MX29F040PC-55G 55 MX29F040PC-70G 70 MX29F040PC-90G 90 MX29F040QI-55 55 MX29F040QI-70 70 MX29F040QI-90 90 P/N:PM0538 MAX.(mA) MAX.(uA ...

Page 35

PART NO. Access Time Operating Current Standby Current Temperature PACKAGE (ns) MX29F040TI-55 55 MX29F040TI-70 70 MX29F040TI-90 90 MX29F040PI-55 55 MX29F040PI-70 70 MX29F040PI-90 90 MX29F040QI-55G 55 MX29F040QI-70G 70 MX29F040QI-90G 90 MX29F040TI-55G 55 MX29F040TI-70G 70 MX29F040TI-90G 90 MX29F040PI-55G 55 MX29F040PI-70G 70 MX29F040PI-90G ...

Page 36

PACKAGE INFORMATION P/N:PM0538 MX29F040 36 REV. 2.3, DEC. 10, 2004 ...

Page 37

P/N:PM0538 MX29F040 37 REV. 2.3, DEC. 10, 2004 ...

Page 38

P/N:PM0538 MX29F040 38 REV. 2.3, DEC. 10, 2004 ...

Page 39

REVISION HISTORY Revision Description 1.0 To remove "Advanced Information" datasheet marking and contain information on products in full production. 1.1 To improve ICC1:from 40mA @5MHz to 30mA @5MHz 1.2 To add the description for 100K endurance cycle To modify timing ...

Page 40

... MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. MX29F040 ...

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