AMPAL22V10AJC Advanced Micro Devices, AMPAL22V10AJC Datasheet

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AMPAL22V10AJC

Manufacturer Part Number
AMPAL22V10AJC
Description
Manufacturer
Advanced Micro Devices
Datasheet

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PAL22V10 Family, AmPAL22V10/A
24-Pin TTL Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The PAL22V10 provides user-programmable logic for
replacing conventional SSI/MSI gates and flip-flops at a
reduced chip count.
The PAL22V10 device implements the familiar Boolean
logic transfer function, the sum of products. The PAL de-
vice is a programmable AND array driving a fixed OR
array. The AND array is programmed to create custom
product terms, while the OR array sums selected terms
at the outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to 16 across the outputs
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
BLOCK DIAGRAM
Publication# 16559
Issue Date: February 1996
As fast as 7.5-ns propagation delay and
91 MHz f
10 Macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
Varied product term distribution allows up to
16 product terms per output for complex
functions
RESET
OUTPUT
MACRO
LOGIC
CELL
FINAL
I/O
MAX
8
0
Rev. C
1
(external)
OUTPUT
CLK/I
MACRO
LOGIC
CELL
I/O
Amendment /0
10
1
0
OUTPUT
MACRO
LOGIC
CELL
I/O
12
COM’L: -7/10/15
2
OUTPUT
MACRO
LOGIC
CELL
I/O
14
3
OUTPUT
MACRO
LOGIC
Programmable
CELL
I/O
16
AND Array
(44 x 132)
4
OUTPUT
MACRO
grammed as registered or combinatorial, and active
high or active low. The output configuration is
determined by two fuses controlling two multiplexers in
each macrocell.
AMD’s FusionPLD program allows PAL22V10 designs
to be implemented using a wide variety of popular indus-
try-standard design tools. By working closely with the
FusionPLD partners, AMD certifies that the tools pro-
vide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
LOGIC
CELL
I/O
16
Global asynchronous reset and synchronous
preset for initialization
Power-up reset for initialization and register
preload for testability
Extensive third-party software and programmer
support through FusionPLD partners
24-Pin SKINNYDIP, 24-pin Flatpack and
28-pin PLCC and LCC packages save space
5
OUTPUT
MACRO
LOGIC
CELL
I/O
14
6
OUTPUT
MACRO
LOGIC
CELL
I/O
12
7
OUTPUT
MACRO
LOGIC
CELL
I/O
11
10
8
I
1
- I
11
OUTPUT
MACRO
LOGIC
Advanced
CELL
I/O
8
9
Devices
16559C-1
Micro
PRESET
2-197

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AMPAL22V10AJC Summary of contents

Page 1

FINAL COM’L: -7/10/15 PAL22V10 Family, AmPAL22V10/A 24-Pin TTL Versatile PAL Device DISTINCTIVE CHARACTERISTICS As fast as 7.5-ns propagation delay and 91 MHz f (external) MAX 10 Macrocells programmable as registered or combinatorial, and active high or active low to match ...

Page 2

AMD CONNECTION DIAGRAMS Top View SKINNYDIP/FLATPACK CLK ...

Page 3

ORDERING INFORMATION Commercial Products AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of: FAMILY TYPE PAL or AmPAL = Programmable Array Logic NUMBER OF ARRAY ...

Page 4

AMD FUNCTIONAL DESCRIPTION The PAL22V10 allows the systems engineer to imple- ment a design on-chip, by opening fuse links to config- ure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which ...

Page 5

Registered Output Configuration Each macrocell of the PAL22V10 includes a D-type flip- flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock in- put. In the registered configuration (S feedback is from Q ...

Page 6

AMD Register Preload The register on the PAL22V10 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct load- ing of arbitrary states, making it unnecessary to cycle through long ...

Page 7

LOGIC DIAGRAM SKINNYDIP (PLCC/LCC) Pinouts CLK ( ( ( ( ...

Page 8

AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . Supply ...

Page 9

CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may ...

Page 10

AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . Supply ...

Page 11

CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may ...

Page 12

AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . Supply ...

Page 13

CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may ...

Page 14

AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . Supply ...

Page 15

CAPACITANCE (Note 1) Parameter Symbol Parameter Description C Input Capacitance IN C Output Capacitance OUT Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may ...

Page 16

AMD SWITCHING WAVEFORMS Input or V Feedback Combinatorial Output Combinatorial Output t WH Clock Clock Width Input t ARW Asserting Asynchronous Reset t AR Registered Output Clock Asynchronous Reset Notes 1 Input pulse amplitude ...

Page 17

KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING TEST CIRCUIT Specification Closed Open Closed Open Closed INPUTS OUTPUTS Must be Will be Steady ...

Page 18

AMD MEASURED SWITCHING CHARACTERISTICS for the PAL22V10- 4. (Note Note: ...

Page 19

INPUT/OUTPUT EQUIVALENT SCHEMATICS Input Program/Verify Circuitry Typical Input 40 NOM Input, I/O Pins Typical Output PAL22V10 Family AMD V CC 16559C- Output Program/Verify/ Test Circuitry Preload Circuitry 16559C-17 2-215 ...

Page 20

AMD POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed pat- tern. This feature is valuable in simplifying state ...

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