CS98100-CM Cirrus Logic, Inc., CS98100-CM Datasheet
CS98100-CM
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CS98100-CM Summary of contents
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... MP3 plus WMA decoding. Other advanced features include karaoke down-mix. The low cost ex- tended feature set makes the CS98100 ideal for both low-end and high-end system manufacturers. ORDERING INFORMATION CS98100-CM 0° to 70° C DSP Instruction X, Y Data Cache Memory ...
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... SDRAM Interface .................................................................................................. 8 1.2.3 DVD Serial Interface Timing ................................................................................ 11 1.2.4 Digital Video Interface Timing ............................................................................. 12 1.2.5 Digital Audio Interface Timing ............................................................................. 13 1.2.6 ROM/NVRAM Interface ....................................................................................... 15 1.2.7 Miscellaneous Timings ........................................................................................ 17 2. TYPICAL APPLICATION ........................................................................................................ 18 2.1 CS98100 Device Summary ............................................................................................. 18 3. FUNCTIONAL DESCRIPTION ............................................................................................... 20 3.1 RISC Processor ............................................................................................................... 20 3.2 DSP Processor ................................................................................................................ 20 3.3 Memory Control ............................................................................................................... 20 3.4 Dataflow Control (DMA) ................................................................................................... 20 3.5 System Control Functions ................................................................................................ 20 3.6 DVD/ATAPI Interface ....................................................................................................... 21 3 ...
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... Figure 3. SDRAM Burst Read Transaction ..................................................................................... 9 Figure 4. SDRAM Burst Write Transaction ..................................................................................... 9 Figure 5. CS98100 SDRAM Read and Write ................................................................................ 10 Figure 6. CS98100 DVD Serial Interface Timing Diagram............................................................ 11 Figure 7. CS98100 Digital Video Interface Timing Diagram ......................................................... 12 Figure 8. Digital Audio In Timing Diagram .................................................................................... 13 Figure 9. Digital Audio Out Timing Diagram.................................................................................. 14 Figure 10. ROM/NVRAM Reading Timing .................................................................................... 15 Figure 11 ...
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... Table 21. Audio Output Interface Pin Assignments....................................................................... 51 Table 22. Host Master Interface Pin Assignments ........................................................................ 52 Table 23. DVD I/O Channel Interface Pin Assignments ................................................................ 53 Table 24. DVD Serial Data Interface Pin Assignments ................................................................. 54 Table 25. Video Encoder Interface Pin Assignments .................................................................... 55 Table 26. General Purpose I/O Interface Pin Assignments........................................................... 56 Table 27. Power and Ground ........................................................................................................ 57 4 CS98100 ...
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... Supply Current, core and PLL Digital Pins Input Voltage, High Input Voltage, Low Description Symbol AMB Symbol Conditions Normal Operating DD I Normal Operating CS98100 Min Max Unit -0.5 4.6 Volts -0.5 2.5 Volts -0.5 5.5 Volts - - 260 o C 235 o C -40 125 o ...
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... buffer rating OUT 37.5 Ω 37.5 Ω MAT V RL= 37.5Ω out DG DP SNR AM PM CS98100 Min Typ Max Units -1 +1 µA 75 KΩ 2.4 Volts 0.4 Volts -1 +1 µ 1.28 Volts 2 % 1.28 Volts 1 % 0.5 deg ...
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... AC CHARACTERISTICS (TA= 25°C; VDD_PLL=VDD_CORE=1.8 V±10%, VDD_IO=3.3 V±10%) 1.2.1 ATAPI Interface The CS98100 can interface with ATAPI-type slave loader gluelessly. transaction and a write ATAPI transaction. PIO mode 4 is implemented for sufficient data transfer rate be- tween ATAPI device and the CS98100. See Table 1 for the ATAPI symbols and characterization data. ...
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... SDRAM Interface The CS98100 interfaces with either SDRAM or SGRAM, for high data bandwidth transfer. Table 2 show the interface pin timing. Figure 3 shows a burst read (length = 8) transaction, while action. In both Figure 3 and Figure Symbol t Output Delay from DR_CKO active edge mco t DR_CKO Period ...
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... DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0] F Figure 3. SDRAM Burst Read Transaction DR_CKO R0 DR_A_[11:0] DR_CKE DR_RAS_N DR_CAS_N DR_WE_N DR_D[31:0] DR_DQM[3:0] F Figure 4. SDRAM Burst Write Transaction CS98100 ...
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... DR_RAS_N,DR_CAS_N DR_W E_N,DR_AP,DR_DQM[3:0], DR_CKE,DR_A[11: mco DR_CKO DR_D[31:0](WRITE) DR_D[31:0](READ) t msur Figure 5. CS98100 SDRAM Read and Write CS98100 t mper t t mdow mhw t mhr ...
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... DVDS_VLD,DVDS_SOS Setup to DVDS_CLK dscdsu t DVDS_VLD,DVDS_SOS Hold after DVDS_CLK 0 dscdhd 1. Values are guaranteed by design only DVDS_CLK (Input) DVDS_DATA (Input) DVDS_VLD, DVDS_SOS (Input) Figure 6. CS98100 DVD Serial Interface Timing Diagram Description Table 3. CS98100 DVD Interface Characteristics t dsckper t t dsckl dsckh t dsdsu t dscdsu CS98100 ...
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... Table 4. CS98100 Digital Video Interface Characteristics 1. Values are guaranteed by design only recommanded that the output data should be taken at the opposite edge of the CLK27_O. CLK27_O (Output) VDAT[7:0] (Output) VSYNC/HSYNC (Output) Figure 7. CS98100 Digital Video Interface Timing Diagram 12 Description -10 -10 Tvocper Tcovo1 Tcovo2 CS98100 Min ...
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... AIN_DATA hold time after AUD_BCK active edge 1 *AUD_BCK (Output) AIN_LRCK (Input) AIN_DATA (Input) * Active clock edge is programmable. Timing is referenced from active edge. Description Table 5. Digital Audio In Characteristics t lrts t t sdsus sdhs Figure 8. Digital Audio In Timing Diagram CS98100 Min Typ Max Unit ...
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... AUD_BCK(Output) AUD_LRCK(Output) AUD_DO[3:0] (Output) * Active clock edge is programmable. Timing is referenced from active edge. 14 Description Table 6. Digital Audio Out Characteristics t axper t t axcl t odbck t t odsd Figure 9. Digital Audio Out Timing Diagram CS98100 Min Typ Max 216 ns -10 10 ...
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... [ Description Table 7. RAM/NVROM Characteristics cds t ods t ads Figure 10. ROM/NVRAM Reading Timing CS98100 Min Typ Max Unit ...
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... Figure 11. ROM/NVRAM Write Timing CS98100 ...
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... XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz RESET-N GPIO Figure 12. Miscellaneous Timings Description Table 8. Miscellaneous Timing Characteristics t xccper t rstl t t gpl gph CS98100 Min Typ Max Unit 37.037 ns 1000 ± 1 KHz). ...
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... TYPICAL APPLICATION Figure 13 shows an example of a complete high-end DVD solution using the CS98100. Front Panel Audio IR DVD Loader (IO Channel, ATPAI or Serial) 2.1 CS98100 Device Summary RISC-32 • Powerful 32-bit RISC processor • Optimizing C compiler and source level debug- ger • Big or little endian data formats supported • ...
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... Hardware vertical scaling supports NTSC-PAL format conversion • 16 level alpha blending System Functions • 208-pin MQFP package. • All I/O pins are 3V with 5V tolerance. • Advanced 0.18 micron CMOS technology. • Chip runs at 90 MHz • Supports Low power modes and clock shutoff. CS98100 19 ...
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... DRAM Interface supports MByte. For a typical DVD player application, CS98100 requires 8 MByte of SDRAM and 1 MByte of FLASH. 20 Sharing the same interface, the CS98100 also sup- ports flash ROM, OTP, or masked ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside DRAM for execution. ...
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... FIFO in DRAM. The same interface pins can be optionally config- ured as a generic 16-bit host master port. In this mode, the CS98100 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects) ...
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... Video Processing The CS98100 Video processor is a powerful, fully programmable video post processing engine that displays video on an interlaced progressive HDTV. A 16-tap polyphase vertical filter is fully programmable on a line-by-line basis, to provide high quality vertical scaling and interlaced field conversion ...
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... MEMORY MAP AND REGISTERS 4.1 Processor Memory Map The CS98100 externally supports Mbytes DRAM and 16 Mbytes ROM/NVRAM. the memory map as viewed by the RISC processor, and identifies whether each segment is mapped or cacheable. Processor byte address 0000_0000 – 07FF_FFFF 8000_0000 - 81FF_FFFF 9400_0000 – 9CFF_FFFF 9C00_0000 – ...
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... Table 13 lists all the registers for the CS98100 and their addresses, and indicates whether the registers are read/write (R/W), read only (RO) or write only (WO). 24 Table 11. Internal IO Space Map DRAM Controller (DRC) Serial DVD (DVDS) MPEG Video Decoder Table 12 ...
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... InterProc_Comm_Register_0 General InterProc_Comm_Register_1 General InterProc_Comm_Register_2 General InterProc_Comm_Register_3 General General General General General General General General GenIO_Three_State_Enable GenIO_Positive_Edge_Mask GenIO_Negative_Edge_Mask GenIO2_Three_State_Enable Table 13. CS98100 Registers CS98100 Register Name Command Semaphore_Register_0 Semaphore_Register_1 Semaphore_Register_2 Semaphore_Register_3 Semaphore_Register_4 Semaphore_Register_5 Semaphore_Register_6 Semaphore_Register_7 GenIO_Read_Data GenIO_Write_Data GenIO_Positive_Edge GenIO_Negative_Edge GenIO_Interrupt_Status GenIO_Level_Mask GenIO2_Read_Data ...
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... General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Interrupt) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) General (Timer) Table 13. CS98100 Registers (Continued) CS98100 Register Name GenIODVD_Three_State_Enable GenIODVD_Mode Ser1_Mstr_Write_1Byte Ser1_Mstr_Write_2Bytes Ser1_Mstr_Control Ser1_Mstr_Status Ser1_Mstr_Read_Data RSK_Interrupt_Mask RSK_Interrupt_Set RSK_Interrupt_Status ...
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... General (Serial IF2) 10E0 R/W General (Serial IF2) 10E4 R/W General (Serial IF3) 10E8 RO General (Serial IF3) 100 R/W 104 R/W Table 13. CS98100 Registers (Continued) Function General (IR) General (IR) General (IR) General (IR) General (IR) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) General (PLL) Host Host ...
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... Dram controller Dram controller Dram controller Dram controller DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Table 13. CS98100 Registers (Continued) CS98100 Register Name Device_3_Control Device_4_Control Write_Data_Port Read_Data_Port Host_Start_Address Dram Start Address Stream_Transfer_Size DRAM_Burst_Threshold Ser1_Slave_Address Host_Master_Control DRAM_Controller_Priority0 DRAM_Controller_Priority1 DRAM_Controller_Priority2 ...
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... R/W 458 RO 45C R/W 500 R/W 504 R/W 508 R/W 510 R/W 514 R/W 518 RO 534 RO 53C RO 544 R/W 548 R/W Table 13. CS98100 Registers (Continued) Function DMA DMA DMA CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD DVD_Current_Dram_Address CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD CD/DVD DVDS DVDS DVDS ...
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... Subpicture_PTS_FIFO_Write_Address Sync Control Subpicture_PTS_FIFO_Read_Address Sync Control Sync Control Sync Control Sync Control Highlight_Control_Information_Address Sync Control Sync Control Sync Control Sync Control Sync Control Table 13. CS98100 Registers (Continued) CS98100 Register Name DRAM_Underflow_Status Input_Data_Counter DSP_Boot_Code_Start_Address DSP_Run_Enable DSP_Program_CntRun_Status Audio_Sync_Control Video_Sync_Control Video_Sync_Status Wait_Line Frame_Period STC_Interval ...
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... MPEG Vid Decoder 84C R/W MPEG Vid Decoder 854 R/W MPEG Vid Decoder 858 R/W MPEG Vid Decoder A00 R/W A04 R/W Table 13. CS98100 Registers (Continued) Function Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control Sync Control MPEG_Video_FIFO_Start_Address MPEG_Video_FIFO_End_Address MPEG_Video_FIFO_Current_Address MPEG_Video_Horiz_Pan_Vector MPEG_Video_FIFO_Add_Bytes ...
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... Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Video Processor Frame_V_Buffer_Compressed_Offset Video Processor Table 13. CS98100 Registers (Continued) CS98100 Register Name PIP_VidBrdEndX PIP_VidBrdStartY PIP_VidBrdEndY PIP_BorderClr PIP_Vscale PIP_Line_Offnum_Bot PIP_FrBaseY PIP_FrBaseU PIP_FrBaseV PIP_Line_Width ...
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... C10 R/W C14 R/W C18 R/W C1C R/W C20 R/W C24 R/W C28 R/W C2C R/W C30 R/W C34 R/W C38 R/W C3C R/W Table 13. CS98100 Registers (Continued) Function Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture Subpicture CS98100 Register Name Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker Anti-Flicker ...
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... On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display On Screen Display PCM PCM PCM PCM PCM PCM Table 13. CS98100 Registers (Continued) CS98100 Register Name Subpicture_DCI_Address Subpicture_HLI_Address Subpicture_Control Subpicture_Display_Offset Subpicture_Display_Scale OSD_Status OSD_Control OSD_Color_Number OSD_Color_Data OSD_Region1_Control OSD_Region1_Hlimits OSD_Region1_Vlimits ...
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... R/W E68 R/W E6C RO F00 R/W F04 RO F40 R/W F44 R/W F48 R/W F4C R/W F50 R/W F54 R/W F58 R/W F5C R/W Table 13. CS98100 Registers (Continued) Function PCM PCM PCM PCM PCM PCM_In_FIFO_Interrupt_Address PCM PCM_Out_FIFO_Interrupt_Address2 PCM PCM_Out_FIFO_Interrupt_Address3 PCM PCM_In_FIFO_Current_Address PCM PCM IEC958_Output_FIFO_Start_Address PCM IEC958_Output_FIFO_End_Address PCM IEC958_Output_FIFO_Current_Address PCM IEC958_Output_FIFO_Interrupt_Address PCM IEC958_Output_FIFO_Add_Blocks PCM ...
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... Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder Video Encoder RISC Table 13. CS98100 Registers (Continued) CS98100 Register Name Test Test Test Burst_Gain Component_Mode Sync_Attenuation Sync_Offset Test Closed_Caption_Control Closed_Caption_Data0 ...
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... MS_SDA1 M_SCL2 M_SDA2 Table 14 lists the conventions used to identify the pin type and direction. H_ALE H_RD H_WR H_RDY CS98100 RST_N IR_IN SER_CS SER_DI Figure 14. CS98100 Pin Layout Symbol Description I Input S Schmitt trigger on input D pull down resistor U pull up resistor O Output O4 Output – 4mA drive O8 Output – ...
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... PIN ASSIGNMENTS Table 15 lists the pin number, pin name and pin type for the 208-pin CS98100 package. For signal pins, the pin direction after reset is shown. The pri- Pin Name Type Reset 1 PLL_1V8 Pwr 2 M_A11 M_A10 M_A9 M_D8 ...
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... DR_BS_N O Core Power DR_AP O Core Ground I/O Ground DR_RAS_N O I/O Power DR_CAS_N O DR_Data[31] B DR_Data[30] B DR_Data[29] B DR_Data[28] B DR_Data[27] B NVM_Addr[23] I/O Ground DR_Data[26] B NVM_Addr[22] I/O Power DR_Data[23] B NVM_Addr[21] Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note ...
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... Hst_Addr[0] O GPIO_D[23] Hst_ALE O GPIO_D[26] DR_Data[17] B NVM_Addr[13] I/O Ground DR_Data[16] B NVM_Addr[12] DR_Data[15] B NVM_Data[15] DR_Data[14] B NVM_Data[14] I/O Power DR_Data[13] B NVM_Data[13] DR_Data[12] B NVM_Data[12] DR_Data[11] B NVM_Data[11] Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note ...
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... DR_Addr[6] O NVM_Addr[6] DR_Addr[5] O NVM_Addr[5] DR_Addr[4] O NVM_Addr[4] I/O Power DR_Addr[3] O NVM_Addr[3] DR_Addr[2] O NVM_Addr[2] DR_Addr[1] O NVM_Addr[1] DR_Addr[0] O NVM_Addr[0] I/O Ground Vid_Data[0] O GPIO_2[0] Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note DVD_Data[ DVD_Data[ DVD_Data[ DVD_Data[ DVD_Error I B DVD_SOS ...
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... AUD_XCK B AUD_BCK O GPIO_2[12] AUD_LRCK O Hst_Write O GPIO_D[17] Hst_Read O GPIO_D[16] (Tie to ground) I I/O Ground Core Ground AUD_Dout[0] O Core Power AUD_Dout[1] O GPIO_2[13] AUD_Dout[2] O GPIO_2[14] AUD_Dout[3] O GPIO_2[15] Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note DVD_ENA I B DVD_RDY ...
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... GPIO_2[21] DVDS_CLK I DVDS_DAT I GPIO_2[23] DVDS_VLD B GPIO_2[25] DVDS_SOS B GPIO_2[24] Vid_Clock O GPIO_2[22] Infrared I I/O Ground Reset_L I PLL Power PLL Ground Hst_Ready O GPIO_D[22] Core Ground Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note DVD_STB I 43 ...
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... GPIO_D[8] Hst_Data[5] B GPIO_D[8] Hst_Data[4] B GPIO_D[8] Analog Ground Digital Power Digital Ground Video Out O Analog Power Analog Ground Video Out O Analog Power Analog Ground Table 15. Pin Assignments (Continued) CS98100 Dir Function #3 Dir Note B CD_DATA I B CD_LRCK I B CD_BCLK I B CD_C2P0 I B DVDL_DI ...
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... IO_GND Gnd 208 PLL_GND Gnd Note 1: Pin may be used for micro-less DVD loader interface Note 2: Pin should be left unconnected Note 3 M_D[31:16] are driving when CS98100 is reading ROM/NVRAM on M_D[15:0], which occurs immediately after reset. Function #1 Dir Function #2 Video O Analog Power Analog Ground ...
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... XTLCLK_O 154 RST_N 125 MFG_TEST 46 Type I De-modulated infrared Input, from IR receiver MHz crystal input MHz oscillator input O 27 MHz crystal output I Reset Input, active low. I Manufacturing test pin, should always connect to ground. Table 16. Miscellaneous Interface Pins CS98100 Description ...
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... Output data for 4-wire serial port – may function as bi- directional data in 3-wire mode. B Input data for 4-wire serial port B Chip select for 4-wire serial port (output for master mode, input for slave mode). Can also be used as bi-directional ready line. Table 17. Serial Interface Pin Assignments CS98100 Description 47 ...
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... Table 18 terface any particular configuration of SDRAM. Type Description B Memory Data Bus. CS98100 can use all 32 bits or can use only M_D[15:0], in which case M_D[31:16] can be left unconnected.note: 32 bits wide is recommended O Memory Address Bus. Connect in order starting with M_A[0] to all RAM address pins not already connected to DR_BS_N or DR_AP ...
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... DRAM data bus). Use M_D[7:0] for 8-bit inter- face. O NVM_Addr[11:0], Memory Address Bus[11:0] (shared with DRAM address bus) O NVM_Addr[23:12], Memory Address Bus[23:12] (shared with bits [27:16] of DRAM data bus) O ROM/NVRAM Chip Enable. O ROM/NVRAM Output Enable. O Copy of ROM/NVRAM Output Enable. O NVRAM Write Enable. CS98100 49 ...
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... Digital Video Output Interface This interface can be used to drive CCIR- 601/CCIR-656 digital data to an external video en- coder (such as an CS4955), for example if a fourth DAC is required. The CS98100 is sync master of Pin Signal Name 113 HSYNC 114 VSYNC 148 CLK27_O 112, 111, 110, 109, ...
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... Audio Serial PCM Data Out[3] (2-channel downmix) O IEC-958 Output I This input can come from from an external comparator. I Left/Right Clock. Input from external audio ADC. The CS98100 can be programmed to use the Audio Output func- tion’s internally generated LR clock, in which case this pin is not required. CS98100 51 ...
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... Host Master/ATAPI Interface This 16-bit parallel host interface allows the CS98100 host master, controlling other de- vices that would be used on the same system. The interface supports a programmable protocols and speeds, including multiplexed and non-multiplexed addressing. Slaves with different protocols can be connected at the same time, controlled by different ...
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... DVD I/O Channel Interface This interface connects to standard DVD loaders, and consists of three parts: Control, DVD Data and CD Data. This interface shares CS98100 pins with the Host Master/ATAPI interface. The pin defini- Pin Signal Name 94 DVD_SOS 93 DVD_Error 124 H_RD 123 H_WR 158 ...
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... DVD loader, a general purpose ATAPI GPIOs. Type Description I DVD clock input – rising edge is the active edge I DVD serial data input (data can be input MSB or LSB first) I DVD valid – a bit of data is clocked in when this pin is high I DVD start of sector input – active high CS98100 ...
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... Analog video output – Y(YUV), G(RGB), Y(Y/C/YC) O Analog video output – V(YUV), R(RGB), YC(Y/C/YC) O Compensation pin, should be connect through 0.1µF capaci- tor to analog 3.3V supply B Current adjust pin, connect through 174Ω,1% resistor to analog ground B Voltage reference pin, connect through 0.1µF capacitor to analog ground CS98100 55 ...
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... General Purpose Input/Output (GPIO) The CS98100 provides a number of GPIO pins, each with individual output three-state controls. There are eight dedicated GPIO pins, which can also be used to generate internal interrupts based on edge or level events on the pins. Two groups of ad- Pin Signal Name ...
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... Power and Ground The CS98100 requires five different types of power supplies for the Plus, internal logic, IO pins, video DAC-digital and video DAC analog. The PLLs, in- ternal logic and video DAC digital use 1.8 V supply voltage. The IO pins and video DAC analog use 3.3 V supply voltage ...
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... PIN MQFP PACKAGE SPECIFICATIONS 208 0.50±0.10 +0.10 0.15 –0.05 0.20 ±0.05 Notes: Measurement Unit = mm Figure 15. CS98100 208-Pin MQFP Package Drawing 58 30.60±0.30 28.00±0.13 157 156 105 104 WITH PLATING BASE METAL DETAIL A CS98100 3.68(MAX) 3.23 ±0.08 0.10(MIN) Detail A 0~10° 0.50±0.20 1.30±0.20 ...
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Notes • ...
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