MN89306 Panasonic, MN89306 Datasheet

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MN89306

Manufacturer Part Number
MN89306
Description
Manufacturer
Panasonic
Datasheet

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LSIs for Display
MN89306
XGA LCD Display Controller
built-in BitBLT graphics accelerator supports 16 two-operand raster operations. The MN89306 also provides a full
complement of power management functions to implement low-power video systems.
Note) The term bpp stands for bits per pixel.
LCD display functions
Display modes
Host interface
Memory interface
Memory write FIFO
BitBLT accelerator
LCD panel screen size correction
Power management mode
Automatic stop function for clock supply to non-operation blocks (BitBLT and graphics blocks)
Supply voltage
Word processors, POS terminals and other equipment with LCD display
Overview
Features
Applications
The MN89306 is an LCD display controller IC that provides high-speed graphics and high-quality display. The
Color TFT (800
Color DSTN/SSTN (800
800
640
320
ISA (16 bits), 386 and 486 (16 bits)
RISC CPUs (16-bit WAIT/RDY control)
16M or 4M EDO, Fast Page Mode DRAM, SDRAM. (16-bit bus)
16 bits
Video memory internal transfers
Host to video memory transfers
Pattern expansion
16 raster operations with 2-operand
Monochrome expansion and transfer
Filling of rectangular areas
The screen size correction can be set independently in the horizontal and vertical directions.
Standby mode
Suspend mode
Sleep mode
3.0 V to 3.6 V (The host interface pins also support 5 V inputs.)
480: 16 bpp (when 320
600: 4 and 8 bpp
480: 4 and 8 bpp
4 stages
600 and 640
600 and 640
480 resolution images are displayed on a 640
480)
480)
480 panel)
1

Related parts for MN89306

MN89306 Summary of contents

Page 1

... MN89306 XGA LCD Display Controller Overview The MN89306 is an LCD display controller IC that provides high-speed graphics and high-quality display. The built-in BitBLT graphics accelerator supports 16 two-operand raster operations. The MN89306 also provides a full complement of power management functions to implement low-power video systems. ...

Page 2

... MN89306 Block Diagram ISA/386/486/RISC HOST I/F WRITE FIFO GRAPHICS BitBLT PATBLT STRING EXTEND 2 HALF FRAME CONTROL GRAY SCALE ENGINE RAM CRTC/LCDC ATT PSCONV VIDEO FIFO MEMORY ACCESS ARBITRATOR MEMORY I/F EDO/Fast Page Mode/Synchronous DRAMs LSIs for Display LCD panel LCD I/F (TFT/SSTN/DSTN) PLL SEQUENCER ...

Page 3

... RISC CPU 16 bits Furthermore, since the MN89306 supports linear addressing, the CPU address calculation time can be reduced. Thus memory accesses are faster than if memory were accessed using a VGA compatible address area. Note) 1. ISA bus is a registered trademark of the (US) Industry Standards Architecture. ...

Page 4

... MN89306 Block Functional Descriptions (continued) 7) Video FIFO/PSCONV The video FIFO temporarily stores data read out of memory in fast page mode, converts that data to dot units according to control signals from the CRT/LCD controller, and outputs that display data. In text mode, this circuit calculates font addresses and issues access requests to the memory interface. ...

Page 5

... MD1 120 MD0 121 MCS (SDRAM) 122 VDD 123 RESET 124 GND 125 PLLTEST 126 VREF5 127 XO 128 (TOP VIEW) MN89306 DISP 61 SCK 60 VDD 59 GND 58 BS16 57 LDEV 56 RDY 55 VDD 54 GND TEST 46 D6 ...

Page 6

... MN89306 Pin Arrangement (continued) 2) 386SX Local Bus Mode MA0 97 GND 98 VDD 99 RAS 100 UCAS /CAS (SDRAM) 101 LCAS /LDQM(SDRAM) 102 WE 103 MD15 104 MD14 105 MD13 106 MD12 107 MD11 108 MD10 109 GND 110 HDQM(SDRAM) 111 MD9 112 MD8 113 ...

Page 7

... MD1 120 MD0 121 MCS (SDRAM) 122 VDD 123 RESET 124 GND 125 PLLTEST 126 VREF5 127 XO 128 (TOP VIEW) MN89306 DISP 61 SCK 60 VDD 59 GND 58 IOCS16 57 MEMCS16 56 IOCHRDY 55 VDD 54 GND 53 SD0 52 SD1 51 SD2 50 SD3 49 SD4 48 SD5 47 TEST 46 SD6 ...

Page 8

... MN89306 Pin Arrangement (continued) 4) RISC CPU Mode MA0 97 GND 98 VDD 99 RAS 100 UCAS /CAS (SDRAM) 101 LCAS /LDQM(SDRAM) 102 WE 103 MD15 104 MD14 105 MD13 106 MD12 107 MD11 108 MD10 109 GND 110 HDQM(SDRAM) 111 MD9 112 MD8 113 MD7 ...

Page 9

... Indicates to the host that this chip was accessed as a local bus device. 16-bit data bus Indicates to the host that this chip was accessed as a 16-bit device. Function A high level on this input indicates that a DMA operation is in progress. Therefore, the MN89306 will not respond to an I/O access when this input is high. MN89306 9 ...

Page 10

... MN89306 Pin Descriptions (continued) 2) ISA Bus Related Pins (continued) Pin Name I/O Level SBHE TTL System byte high enable IOWR TTL I/O write IORD TTL I/O read MEMW TTL Memory write MEMR TTL Memory read A[ TTL Address[22 : 20] ...

Page 11

... Write signal for the CPU data bus high order byte, bits [15:8]. The MN89306 can be set to operate as either a big endian or a little endian machine. CPU address lines. CPU data bus. The MN89306 can be set to operate as either a big endian or a little endian machine. The functions of this signal differs depending on the type of CPU selected. ...

Page 12

... MN89306 Pin Descriptions (continued) 3) RISC CPU Related Pins (continued) Due to the differences between the buses, the pin functions correspond as shown in the table. ISA 386SX AEN ADS SBHE CCLK IOWR M/IO IORD W/R MEMW A23 MEMR A22 A21 A21 A20 A20 SA[ A[ SA1 A1 SA0 ...

Page 13

... Lower column address strobe for RAM RAM low-order byte column address strobe signal. Upper column address strobe for RAM RAM high-order byte column address strobe signal. Write enable Data write signal Memory data bus DRAM memory data. MN89306 ...

Page 14

... MN89306 Pin Descriptions (continued) 4) Memory Access Related Pins (continued) When SDRAM is used. Pin Name I/O Level MA11 O MA[ I/O CMOS MCLK O MCS O RAS O CAS LDQM O HDQM O MCLKEN O MD[ I/O CMOS 14 Function Display memory address Display memory address These pins are set to input mode by a reset, and the pins MA[2:0] are used to set the chip host type ...

Page 15

... RAMDAC mode and as the display enable signal when a TFT LCD panel is used. Data shift clock/Dot clock This output is used as the dot clock output for a TFT LCD panel or in external RAMDAC mode also used as the data shift clock output to an STN LCD panel. MN89306 15 ...

Page 16

... MN89306 Pin Descriptions (continued) 5) LCD Related Pins (continued) Pin Name I/O Level UD LD The table below shows the pin functions for each panel type. Pin TFT DISP DEN LP HSYNC FP VSYNC SCK DCLK UD7 R3 UD6 R2 UD5 R1 UD4 R0 UD3 UD2 UD1 G3 UD0 G2 LD7 G1 LD6 ...

Page 17

... Used for IC testing. These pin must be held at the ground level during normal operation. Used for PLL testing. This pin must be held at the ground level during normal operation. Function Digital system power supply (3.3 V) Digital system power supply (GND input pin power supply (4. 5.25 V) MN89306 Host type 17 ...

Page 18

... MN89306 Electrical Characteristics 1. Absolute Maximum Ratings at V Parameter Supply voltage † reference voltage Input pin voltage (except TYPE * Input pin voltage (TYPE-A) Input pin voltage (TYPE-B) Output pin voltage (except TYPE * Output pin voltage (TYPE-C) Output current (TYPE-HL1) Output current (TYPE-HL2) ...

Page 19

... MHz, output pins open V 3 5.0 V REF5 DD1 MHz, output pins open V 3 5.0 V REF5 With the LSI set to standby mode via register settings. MN89306 Min Typ Max 3.0 3.3 3.6 4.75 5.0 5. 100 0 100 XIN MHz, SS TEST ...

Page 20

... MN89306 Electrical Characteristics (continued Characteristics (continued) a Parameter Operating supply current Suspend mode Operating supply current Sleep mode Input with pull-down resisitor (CMOS level ): TEST, MINTEST High-level input voltage Low-level input voltage Pull-down resistor Input leakage current ...

Page 21

... 2 2 MN89306 MHz, SS TEST Min Typ Max V 0 0 0.6 DD 0.4 ...

Page 22

... MN89306 Electrical Characteristics (continued Characteristics (continued) a Parameter I/O with pull-down resisitor (CMOS level) (continued): MA3 to MA10 Pull-down resistor Output leakage current I/O (TTL level): SD0 to SD15 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage ...

Page 23

... Note) The XIN clock determines the memory control timing and the LCD control timing. Determine the XIN clock period based on the specifications of the DRAM and LCD panel used Input Descriptions Descriptions MN89306 5 7 Output Valid data Min Max Unit 4XIN 15 4XIN 15 0 ...

Page 24

... MN89306 Electrical Characteristics (continued Characteristics (continued) 3) ISA Timing AEN REFRESH A[22 : 20] SA[ SBHE IORD , IOWR MEMR , MEMW SD[ Hi-Z IOCHRDY Hi-Z MEMCS16 Hi-Z IOCS16 No. 1 AEN setup time 2 AEN hold time 3 REFRESH# setup time 4 REFRESH# hold time 5 A[22:20], SA[19:0], and SBHE# setup time 6 A[22:20], SA[19:0], and SBHE# hold time ...

Page 25

... CLK1X (Internal) (Only in 386 mode) No. 1 RESET hold time 2 RESET setup time 3 RESET high-level period Descriptions 5) CCLK (4 5 CCLK (MCLK Descriptions MN89306 Min Max Unit 4 4 † † † † MCLK Min Max Unit ...

Page 26

... MN89306 Electrical Characteristics (continued Characteristics (continued) 6) 386CPU RDY# Input and Pipeline Mode Timing CCLK ADS A[ Non VGA RDY LDEV BS16 No. 1 LDEV# and BS16# output delay time (only valid in pipeline mode) 2 RDY# input setup time 3 RDY# input hold time 7) 486CPU Local Bus Timing ...

Page 27

... Note) 1. † : The wait time differs depending on the chip status. 2. CLK in the table refers to one clock period of CCLK. 3. Values listed in the table apply when the external load capacitor is 50 pF. The output delay times will differ depending on the external load capacitor. Descriptions MN89306 Min Max Unit 15 ...

Page 28

... MN89306 Electrical Characteristics (continued Characteristics (continued) 8) 386CPU Local Bus Timing CCLK CCLK1 (Internal M/ ADS 5 Hi-Z BS16 Hi-Z D[ Hi-Z RDY 17 LDEV No. 1 A[23:2], M/IO#, BE[3:0]#, and W/R# setup time 2 A[23:2], M/IO#, BE[3:0]#, and W/R# hold time 3 ADS# setup time 4 ADS# hold time 5 BS16# active delay time 6 BS16# inactive delay time ...

Page 29

... D[15:0] output delay time (read) 6 D[15:0] setup time (read) 7 D[15:0] hold time (read) 8 WE1# and WE0# setup time 9 WE1# and WE0# hold time 10 D[15:0] setup time (write) 11 D[15:0] hold time (write Invalid Valid Descriptions MN89306 Hi Hi-Z 15 Hi-Z 15 Min Max Unit ...

Page 30

... MN89306 Electrical Characteristics (continued Characteristics (continued) 9) RISC CPU Timing (continued) No. 12 RDY# and WAIT# output delay time 13 RDY# low-level output and WAIT# high-level output delay time 14 RDY# and WAIT# hold time 15 Delay time from A[25:1], CS CCLK to the RDY# or WAIT# output high-impedance state. ...

Page 31

... Tb is set with memory control register 2 (XSR0F) bit set with memory control register 3 (XSR12) bits 6 and 7. 4. For fast page mode DRAM, the random access cycle will For EDO DRAM, the random access cycle will Tc. (min (min.) MN89306 ...

Page 32

... MN89306 Electrical Characteristics (continued Characteristics (continued) 12) Memory Access Timing (EDO and fast page mode memory) RAS UCAS , LCAS READ WRITE MD No. Descriptions Memory type Random access cycle time 1 Page mode RAS# low-level period 2 RAS# high-level period 3 CAS# hold time ...

Page 33

... (Ta Tc) 6 (Ta Tc †1 † ( MN89306 Min Max Unit Fast page Fast page mode mode ( ( ( ...

Page 34

... MN89306 Electrical Characteristics (continued Characteristics (continued) 13) CBR Automatic Refresh Timing 3 RAS 4 UCAS LCAS No. Descriptions Memory type 1 Refresh cycle 2 RAS# low-level period 3 RAS# high-level period 4 CAS# high-level period 5 CAS# setup time 6 CAS# hold time Note one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz). ...

Page 35

... Values listed in the table apply when the external load capacitor is 20 pF. The output delay times will differ depending on the external load capacitor. 3. The specification values are determined by referencing to 1 CAS latency 2) 8 RA0 CA0 RA0 D01 D02 Bank0 Write with auto precharge Descriptions MN89306 4 CA0 7 D03 D04 Don't care Min Max Unit T(at 65 MHz ...

Page 36

... MN89306 Electrical Characteristics (continued Characteristics (continued) 16) SDRAM Read Timing (Burst length 1 MCLK 2 3 MCLKEN MCS RAS CAS MA11 RA0 MA10 MA0 to MA9 RA0 HDQM LDQM MD Bank0 Active No. 1 Clock period 2 MCLK high-level period 3 MCLK low-level period 4 MCLKEN hold time ...

Page 37

... AC Characteristics (continued) 17) SDRAM Power on Timing No. 1 TRC control (controlled with bit 3 to bit 5 in XSR20) Note one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz). 2. The specification values are determined by referencing to 1.4 V. Descriptions MN89306 Min Max Unit 3T 10T ns 37 ...

Page 38

... MN89306 Electrical Characteristics (continued Characteristics (continued) 18) SDRAM Self-Refresh Timing No. 1 TRC control (controlled with bit 3 to bit 5 in XSR20) Note one period of MCLK (the divided-by-2 PLL clock: 35 MHz to 65 MHz). 2. The specification values are determined by referencing to 1 Descriptions LSIs for Display ...

Page 39

... CLK is the display system clock (DCLK). 3. Values listed in the table apply when the external load capacitor is 30 pF. Line 1 Line 2 Line 241 Line 242 Line 243 Descriptions MN89306 Line 3 Line 4 Line 5 Line 244 Line 245 2 3 Min Max †1 8CLK 5 †2 664CLK 10 † ...

Page 40

... MN89306 Electrical Characteristics (continued Characteristics (continued) 20) Monochrome STN Two-Screen Panel Timing LP FP Line 239 Line 240 UD LD Line 479 Line 480 LP FP SCK SCK high-level period 2 FP rise to LP fall setup time 3 FP fall to LP fall hold time ...

Page 41

... When the time from LP completion to the 1 line completion is set character by LCD5 and LCD0. 2. CLK is the display system clock (DCLK). 3. Values listed in the table apply when the external load capacitor is 30 pF. Line 1 Line 2 Line Descriptions MN89306 Line 4 Line Min Max †1 8CLK 5 †2 664CLK 10 †4 8CLK 10 † ...

Page 42

... MN89306 Electrical Characteristics (continued Characteristics (continued) 22) Monochrome STN Single-Screen Panel Timing (8-bit data transfer mode LD Line 479 Line 480 LP FP SCK SCK LD No high-level period 2 FP rise to LP fall setup time 3 FP fall to LP fall hold time ...

Page 43

... When the time from LP completion to the 1 line completion is set character by LCD5 and LCD0. 2. CLK is the display system clock (DCLK). 3. Values listed in the table apply when the external load capacitor is 30 pF. Line 1 Line 2 Line Descriptions MN89306 Line 4 Line Min Max †1 8CLK 5 †2 664CLK 10 *4 8CLK 10 † ...

Page 44

... MN89306 Electrical Characteristics (continued Characteristics (continued) 24) Color TFT Timing DEN DEN 5 DCLK No low-level period 2 FP low-level period 3 LP period 4 DEN high-level period 5 DCLK period 6 R[3 : 0], G[3 : 0], B setup time ...

Page 45

... The XIN duty factor is not taken into consideration when the display clock is set to be the sequencer output. 2. Values listed in the table apply when the external load capacitor Descriptions MN89306 4 Min Max †2 8DCLK 10 †3 1HSYNC †4 672DCLK † ...

Page 46

... MN89306 Package Dimensions (Unit: mm) LQFP128-P-1818C 96 97 128 1 (1.25) 46 20.00±0.20 18.00±0. 0.20±0.05 0.50 0.10 Seating plane LSIs for Display 0.10 M (1.00 0.50±0.20 (0.60) ...

Page 47

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