HM5264805FTT-A60 Renesas Electronics Corporation., HM5264805FTT-A60 Datasheet

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HM5264805FTT-A60

Manufacturer Part Number
HM5264805FTT-A60
Description
Manufacturer
Renesas Electronics Corporation.
Datasheet
Description
The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word
HM5264805F is a 64-Mbit SDRAM organized as 2097152-word
is a 64-Mbit SDRAM organized as 4194304-word
rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
3.3 V power supply
Clock frequency: 133 MHz/100 MHz (max)
LVTTL interface
Single pulsed RAS
4 banks can operate simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8/full page
2 variations of burst sequence
Sequential (BL = 1/2/4/8/full page)
Interleave (BL = 1/2/4/8)
1-Mword 16-bit 4-bank/2-Mword 8-bit 4-bank
HM5264165F-75/A60/B60
HM5264805F-75/A60/B60
HM5264405F-75/A60/B60
64M LVTTL interface SDRAM
PC/133,
/4-Mword
133 MHz/100 MHz
PC/100 SDRAM
4-bit
4-bit 4-bank
4 bank. All inputs and outputs are referred to the
8-bit
4 bank. The Hitachi HM5264405F
16-bit
ADE-203-940B (Z)
4 bank. The Hitachi
Nov. 10, 1999
Rev. 1.0

Related parts for HM5264805FTT-A60

HM5264805FTT-A60 Summary of contents

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HM5264165F-75/A60/B60 HM5264805F-75/A60/B60 HM5264405F-75/A60/B60 64M LVTTL interface SDRAM 1-Mword 16-bit 4-bank/2-Mword 8-bit 4-bank /4-Mword PC/133, Description The Hitachi HM5264165F is a 64-Mbit SDRAM organized as 1048576-word HM5264805F is a 64-Mbit SDRAM organized as 2097152-word is a 64-Mbit SDRAM organized as 4194304-word ...

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... MHz HM5264165FTT-A60 100 MHz *2 HM5264165FTT-B60 100 MHz *1 HM5264165FLTT-75 133 MHz HM5264165FLTT-A60 100 MHz *2 HM5264165FLTT-B60 100 MHz *1 HM5264805FTT-75 133 MHz HM5264805FTT-A60 100 MHz *2 HM5264805FTT-B60 100 MHz *1 HM5264805FLTT-75 133 MHz HM5264805FLTT-A60 100 MHz *2 HM5264805FLTT-B60 100 MHz *1 HM5264405FTT-75 133 MHz HM5264405FTT-A60 100 MHz ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264165F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ15 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264805F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ7 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Arrangement (HM5264405F) Pin Description Pin name Function A0 to A13 Address input Row address Column address Bank select address A12/A13 (BS) CKE DQ0 to DQ3 Data-input/output CS Chip select RAS Row address strobe command CAS Column address strobe ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264165F Column address counter Row decoder Memory array Bank 0 4096 row X 256 column X 16 bit A13 Column address Row address buffer buffer Row decoder Row decoder Memory array ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264805F Column address counter Row decoder Memory array Bank 0 4096 row X 512 column X 8 bit A0 to A13 Column address Row address buffer buffer Row decoder Row decoder Memory array Memory ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Block Diagram (HM5264405F Column address counter Row decoder Memory array Bank 0 4096 row X 1024 column X 4 bit A13 Column address Row address buffer buffer Row decoder Row decoder Memory array ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Pin Functions CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (input pin): When CS is Low, the command input cycle becomes valid. When CS ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 V and V Q (power supply pins): Ground is connected output buffer.) Command Operation Command Truth Table The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins. Command Ignore command ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Truth Table (HM5264165F) Command Upper byte write enable/output enable Lower byte write enable/output enable Upper byte write inhibit/output disable Lower byte write inhibit/output disable Note ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CKE Truth Table Current state Command Active Clock suspend mode entry Any Clock suspend Clock suspend Clock suspend mode exit Idle Auto-refresh command (REF) Idle Self-refresh entry (SELF) Idle Power down entry Self refresh Self refresh exit (SELFX) Power ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self- refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self- refresh is performed internally and automatically, external ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CS RAS CAS WE Current state Row active Read ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 CS RAS CAS WE Current state Write Write with auto- H precharge L H ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after t has elapsed from the completion of precharge. RP From IDLE state, command operation To [DESL], [NOP], ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Simplified State Diagram MODE REGISTER SET (on full page) Write CKE_ WRITE SUSPEND CKE WRITE WITH AP CKE_ WRITEA SUSPEND CKE POWER POWER APPLIED ON Automatic transition after completion of command. Transition resulting from command input. Note: 1. After ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 Sequential Burst length = 8 Starting Ad. Addressing(decimal Sequential ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Operation of the SDRAM Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst Length CLK t RCD Command ACTV READ Address Row Column out out 0 out out 0 out 1 out 2 out 3 Dout out 0 out 1 ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0 single write operation, data is only written to the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent clocks. ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Write command interval: 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM, DQMU/DQML must be set High so that the output buffer ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = full page burst CLK READ Command PRE/PALL Dout CAS Latency = 3, Burst Length = 1, 2, ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than the case of different bank-active commands: The interval between the two bank-active commands must be no less ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than l CLK Command MRS Address CODE Mode Register Set . RSA ACTV BS & ROW ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DQM Control The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data, respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the auto- refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power up sequence CKE, DQM, Low DQMU/DQML Low CLK Low CS, DQ Power stabilize Absolute Maximum Ratings Parameter Voltage on any pin relative Supply voltage relative to V ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 V /V Clamp IL IH clamp for CLK, CKE, CS, DQM and D/Q pins. This SDRAM has V and Minimum V Clamp Current IL V (V) IL –2 –1.8 –1.6 –1.4 –1.2 –1 –0.9 –0.8 –0.6 ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Minimum V Clamp Current 0.6 ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 I /I Characteristics OL OH Output Low Current ( Vout (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3 3.45 250 200 150 100 0 Min (mA) Max ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Output High Current ( +70˚ Vout (V) 3.45 3.3 3 2.6 2.4 2 1.8 1.65 1.5 1 0.5 1 –100 –200 –300 –400 –500 –600 ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5264165F) Parameter Symbol Min Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5264805F) Parameter Symbol Min Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 DC Characteristics ( +70˚C, V (HM5264405F) Parameter Symbol Min Operating current (CAS latency = 2) I CC1 (CAS latency = 3) I CC1 Standby current in power down I CC2P Standby current in power down I ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes depends on output load condition when the device is selected output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 AC Characteristics ( +70˚C, V HITACHI Parameter Symbol System clock cycle time (CAS latency = (CAS latency = CLK high pulse width t CKH CLK low pulse width t CKL ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Notes measurement assumes t 2. Access time is measured at 1.5 V. Load condition pF (min) defines the time at which the outputs achieves the low impedance state ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Relationship Between Frequency and Minimum Latency Parameter Frequency (MHz) t (ns) CK Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Parameter Frequency (MHz) t (ns command disable Power down exit to command input Burst stop to output valid data hold (CAS latency = 2) (CAS latency = 3) Burst stop to output high impedance (CAS latency ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Timing Waveforms Read Cycle CKH CKL CLK V IH CKE t RCD RAS CAS t t ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Write Cycle CKH CKL CLK V IH CKE t RCD RAS CAS ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Mode Register Set Cycle CLK V CKE IH CS RAS CAS WE BS Address valid code DQM, DQMU/DQML DQ (output) DQ (input) l RSA l RP Precharge Mode If needed register Set Read Cycle/Write Cycle ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Single Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read CKE RAS CAS WE BS ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Read/Burst Write Cycle CLK CKE CS RAS CAS WE BS Address R:a C:a DQM, DQMU/DQML DQ (input) DQ (output) Bank 0 Bank 0 Active Read V CKE IH CS RAS CAS WE BS R:a C:a ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Full Page Read/Write Cycle CLK V CKE IH CS RAS CAS WE BS Address R:a C:a R:b DQM, DQMU/DQML DQ (output) DQ (input) Bank 0 Bank 0 Bank 3 Active Read Active V CKE IH CS RAS CAS WE ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Auto Refresh Cycle CLK CKE RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Auto Refresh Precharge If needed Self Refresh Cycle CLK CKE Low CKE ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Clock Suspend Mode t CES CLK CKE CS RAS CAS WE BS Address R:a DQM, DQMU/DQML DQ (output) DQ (input) Bank0 Active clock Active clock Active suspend start suspend end CKE CS RAS ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Power Down Mode CLK CKE CS RAS CAS WE BS Address A10=1 DQM, DQMU/DQML DQ (input) DQ (output Precharge command If needed Initialization Sequence CLK CKE RAS CAS WE Address valid ...

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... HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Package Dimensions HM5264165FTT/FLTT HM5264805FTT/FLTT HM5264405FTT/FLTT Series (TTP-54D) 22.22 22.72 Max 54 1 0.80 +0.10 *0.30 –0.05 0.13 M 0.28 0.05 0.91 Max 0.10 *Dimension including the plating thickness Base material dimension 11.76 0.20 0 – 5 0.50 Hitachi Code JEDEC EIAJ Weight (reference value) Unit: mm 0.80 0.10 TTP-54D — — 0.53 g ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Revision Record Rev. Date Contents of Modification 0.0 Jul. 17, 1998 Initial issue 0.1 Dec. 28, 1998 Addition of HM5264165/HM5264805/ HM5264405FTT/FLTT-75 (133MHz) Unification with HM5264165/HM5264805/ HM5264405FTT/FLTT-B6 Change of part number to HM5264165/HM5264805/ HM5264405F-75/A60/B60 Change figure of mode register configuration ...

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HM5264165F/HM5264805F/HM5264405F-75/A60/B60 Revision Record (cont.) Rev. Date Contents of Modification 1.0 Nov. 10, 1999 Ordering information Addition of notes 1 and 2 CKE Truth table Clock suspend mode entry CS Addition of description to clock suspend mode entry DC ...

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