SDA6000 Infineon Technologies AG, SDA6000 Datasheet
SDA6000
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SDA6000 Summary of contents
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Man ers .1, June 2 000 Tel cod ...
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... Edition 2000-06-15 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infi ...
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Contents Overview Pin Description Architectural Overview C16X Microcontroller Interrupt and Trap Function System Control & Configuration Peripherals Clock System Sync System Display Generator D/A Converter Slicer and Acquisition Register Overview Elelctrical Characteristics ...
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Man Dec oder ...
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SDA 6000 Revision History: Previous Version: Page Subjects (major changes since last revision) Complete Update of Controller & Peripheral Spec --> Detailed Version ASC: Autobaud Detection Feature included IC: New Description GPT: New Description IIC changed to I For questions ...
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Contents Overview ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6 System Control & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 ...
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Table of Contents 7.3.4.1 Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . 7.3.4.2 Baud Rate Selection and Calculation . ...
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Table of Contents 10.5.1 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ...
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List of Figures Figure 1-1 M2 Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 7-12 GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . Figure 7-13 Auxiliary Timer of Timer Block 1 in Capture Mode ...
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List of Figures Figure 10-2 Behavior of Blank Pin for Consecutive Frames in ‘Meshed’ Regions ...
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Preface 16-bit controller based on Infineon’s C16x core with embedded teletext and graphic controller functions. M2 can be used for a wide range of TV and OSD applications. This document provides complete reference information on the hardware ...
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Related Documentation For easier understanding of this specification it is recommended to read the documentation listed in the following table. Moreover it gives an overview of the software drivers which are available for M2. Document Name Appl. Note “Initialization and ...
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Overview M2 is designed to provide absolute top performance for a wide spectrum of teletext and graphic applications in standard and high end TV-sets and VCRs. M2 contains a data caption unit, a display unit and a high performance ...
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SDRAMs as well as ROMs or FLASH ROMs. The organization of the memory is linear, so that it is easy to program the chip for graphic purposes. The SW development environment “MATE” is available to simplify and speed up ...
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SIE-MATE Tool Concept: Fast Prototyping on the PC User Interface Object Editor Converter Display data info M2 formatted data, Object Library Manager Dedicated M2 Libraries RTOS Embedded System the 16 Bit MC, TTX/EPG/TeleWeb, High End OSD Engine ...
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Standard Tool Chain For the M2 software development (documentation, coding, debugging and test) the Infineon C166 microcontroller family standard tools can be used: These are ASCII editor, structogram editor, compiler, assembler, linker. Debugging is supported by low-priced ROM-Monitor debuggers or ...
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Teletext Decoder with Embedded 16-bit Controller M2 Version 2.0 1.1 Features General • Level 1.5, 2.5, 3.5 WST Display Compatible • Fast External Bus Interface for SDRAM ( MByte) and ROM or Flash-ROM ( MByte) • ...
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High-speed Synchronous Serial Interface (SSC). Full- and Half-duplex synchronous up to 16.5 Mbaud • 3 Independent, HW-supported Multi Master/Slave I • 16-Bit Watchdog Timer (WDT) • Real Time Clock (RTC) • On Chip Debug Support (OCDS) • 4-Channel 8-bit ...
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Logic Symbol XTAL1 XTAL2 RSTIN CVBS1A CVBS1B CVBS2 COR BLANK HSYNC VSYNC WR CSROM CSSDRAM MEMCLK UDQM LDQM CLKEN Figure 1-2 Logic Symbol Users Manual DD(3 DD(2.5 ...
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Pin Description ...
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Pin Descriptions 2.1 Pin Diagram (top view) P6.2 97 P6.3 98 P6.4 99 P6.5 100 P6.6 101 VSYNC 102 HSYNC 103 COR/RSTOUT 104 BLANK/CORBLA 105 V 106 DD33-8 V 107 SS33-8 XTAL1 108 XTAL2 109 V 110 SSA-1 V ...
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Pin Definitions and Functions Table 2-1 Pin Definition and Functions Pin Pin Name Second No. Function 37 A0 R0/ R1/ R2/ R3/ R4/ R5/ R6/ ...
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Table 2-1 Pin Definition and Functions (cont’d) Pin Pin Name Second No. Function 67 D10 – 72 D11 – 66 D12 – 62 D13 – 56 D14 – 51 D15 – – 46 CSROM – 44 CSSDRAM – ...
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Table 2-1 Pin Definition and Functions (cont’d) Pin Pin Name Second No. Function 113 G – 114 B – 104 COR RSTOUT 105 BLANK CORBLA 103 HSYNC – 102 VSYNC VCS 5 P2.8 EX0IN 6 P2.9 EX1IN 7 P2.10 EX2IN ...
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Table 2-1 Pin Definition and Functions (cont’d) Pin Pin Name Second No. Function 83 P3.9 MTSR 88 P3.10 TxD0 89 P3.11 RxD0 90 P3.12 – 91 P3.13 SCLK 92 P3.15 – 124 P5.0 AN.0 125 P5.1 AN.1 126 P5.2 AN.2 ...
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Table 2-1 Pin Definition and Functions (cont’d) Pin Pin Name Second No. Function 4 TDO – 2 TMS – 128 TMODE – V 110 – SSA-1 V 111 – DDA-1 V 115, – SSA2-4 118, 122 V 116, – DDA2-4 ...
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Architectural Overview ...
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Architectural Overview AMI Figure 3-1 M2 Top Level Block Diagram Users Manual Architectural Overview SDA 6000 2000-06-15 ...
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The architecture of M2 comprises of a 16-bit microcontroller which is derived from the well known Infineon Technologies C16x controller family. Due to the core philosophy of M2, the architecture of the CPU core is the same as described in ...
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The screen refresh unit is used to read the frame buffer pixel by pixel in real time and to process the transparency and RGB data. A color look up table (CLUT) can be used to get the RGB data of ...
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C16X Microcontroller ...
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C16X Microcontroller 4.1 Overview M2’s microcontroller and its peripherals are based on a Cell-Based Core (CBC) which is compatible to the well known C166 architecture. In M2, the CPU and its peripherals are generally clocked with 33.33 MHz which ...
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Barrel shifter • Bit processing capability • Hardware support for multiply and divide instructions Internal RAM (IRAM) The internal dual-port RAM is the physical support for the General Purpose Registers, the system stack and the PEC pointers. Due to ...
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Control interface for Clock Generation Unit • Identification register block for chip and CSCU identification OCDS The On-Chip Debug System allows the detection of specific events during user program execution through software and hardware breakpoints. An additional communication module ...
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External Memory SDRAM ROM1 ROM2 Figure 4-1 M2 Memory Path Block Diagram All memory locations are byte and word readable. The internal memories (IRAM, XRAM) and the external dynamic memory (SDRAM) are byte and word writable, but external static memory ...
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Figure 4-2 Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) ...
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Segment 0 64 Kbytes 00’FFFF RAM / SFR Area 00’F000 2 C 00’E800 XRAM 00’E000 00’C000 00’8000 00’4000 00’0000 Figure 4-3 Internal RAM Areas and SFR Areas Note: The upper 256 bytes of SFR area, ESFR area and IRAM are ...
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The upper 256 Byte of the IRAM (00’FD00 current bank are provided for single bit storage, and thus they are bit addressable. 4.3.1 System Stack The system stack may be defined within the IRAM. The size of the system stack ...
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Table 4-1 Mapping of General Purpose Registers to RAM Addresses Internal RAM Byte Registers Address <CP> – H <CP> – H <CP> – H <CP> – H <CP> – H ...
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H DSTP7 00’FCFC SRCP7 H PEC Source and Destination Pointers 00’FCE2 DSTP0 H 00’FCE0 H SRCP0 Figure 4-4 Location of the PEC Pointers Whenever a PEC data transfer is performed, the pair of source and destination pointers, which is ...
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Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared! The upper half of each register block is bit-addressable, so the respective control/status bits can directly be modified or checked using bit addressing. When ...
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SDRAM PC SDRAM compliant (Intel standard) memory devices with MByte and a minimum clock period (latency 3) may be connected to M2’s external memory bus. Supported data organizations are given below: Memory Size ...
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MByte SDRAM (2...4 banks) Figure 4-5 External Memory Configuration The interlocking execution of access cycles to different memory modules is supported. All external SDRAM access cycles must be executed with a pre-defined burst length and latency ...
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MEMCLK CSSDRAM RAS Read CAS WR ca A(21:0) SDRAM Data D(15:0) CSROM RD Figure 4-6 Interlocked Access Cycles to ROM and SDRAM Users Manual C16X Microcontroller Act ROM_Adr ROM Data SDA 6000 Write ra ra UET11119 2000-06-15 ...
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MEMCLK Pre RAS Read CAS SDRAM: 16 MBit, 2 Banks A (9:0) A10 Bank 1 A11 b1 SDRAM: 64 MBit, 4 Banks A (9:0) A10 A11 Bank Y by A(13:12) Precharge D(15: Figure 4-7 Interlocked Access Cycles ...
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EBI Address-Space FF’FFFF H D 80’0000 H S2 60’0000 H S1 41’0000 H 40’0000 H A Figure 4-8 Memory Mapping from C16x address-space to EBI address-space for 1 64MBit SDRAM (D) and 2 16MBit static memory devices (S1, S2) is ...
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Access to segments 65 to 255 selects the XBUS. This address range (41’0000 FF’FFFF ) is not remapped by the C16x Mapping by caches: In normal operation mode the address requested by the controller is not altered by ...
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Addresses 00’0000 ... 3F’FFFF H • Addresses 40’0000 ... 7F’FFFF H The addresses shown on the external address lines of M2 are word oriented, starting at 0 for each device. The External Bus Interface (EBI) provides a special mode, ...
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REDIR1 Bit Function REDIR1_SEG For access to segment 255, the segment part of the address is (7:0) replaced by REDIR1_SEG. The configuration of the “External Bus Interface” and its operation mode is defined with ...
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Phase EDMR EDMA Figure 4-9 Four-Phase Handshake • Phase I: The controller requests a direct mode command which has not yet been executed by the EBI. The controller must not reset the EDMR bit until the EBI acknowledges the EDMA ...
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The setting required for initiating a certain command on the SDRAM has to be written to the EBIDIR register before the direct mode request, the EDMR bit in the EBICON register is asserted. The following table shows the commands that ...
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Bit Function CSENA Chip Select Enable ‘0’: CS3 is active for 2nd ROM device ‘1’: CS3 is inactive The allocation of address ranges for the SDRAM banks is controlled through the SDRSZE bit. SDRSZE = ‘0’ (16 MBit): Address ...
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Memory Areas are partitions of the address space that represent different kinds of memory (if provided at all). These memory areas are ...
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CPU (XBUS, program memory bus or peripheral bus). Where the program memory bus and the peripheral bus are tightly coupled to the CPU, XBUS accesses are performed, if possible, in parallel while the ...
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PEC interrupt processing steals just one machine cycle from the current CPU activity to perform a single data transfer via the on-chip Peripheral Event Controller (PEC). System errors detected during program execution (so-called hardware traps) are also processed as ...
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In this stage an operation is performed on the previously fetched operands in the ALU. In addition, the condition flags in the PSW register are updated, as specified by the instruction. All explicit writes to the SFR memory ...
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Machine Cycle FETCH DECODE EXECUTE WRITEBACK Time Figure 4-11 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed up sequential program processing. When a branch is taken, the instruction which has been fetched in advance is ...
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Cache Jump Instruction Processing The CPU incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved, ...
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However, there are some very rare cases, where the CPU, being a pipelined machine, requires attention by ...
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I : POP R0 n+2 Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved internally by the CPU logic. Controlling Interrupts Software modifications (implicit or explicit) of the PSW are done in the execute phase of ...
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Timing Instruction pipelining reduces the average instruction processing time on a wide scale (usually from four to one machine cycles). However, there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to ...
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Pipeline Effects” on page 4-29). Protected bits are not changed during the read-modify-write sequence, i.e. when hardware sets e.g. an interrupt request flag between the read and the write of the read- modify-write sequence. ...
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Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles (wait-states). The operand and instruction accesses listed below can extend the execution time of an instruction: • Internal code memory operand reads ...
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SYSCON ROM SGT ROM STKSZ(2..0) S1 DIS Bit Function XPEN XBUS Peripheral Enable Bit ‘0’: Accesses to the on-chip X-Peripherals and their functions are disabled. ‘1’: The on-chip X-Peripherals are enabled and ...
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Bit Function ROMS1 Internal ROM Mapping ‘0’: External ROM area mapped to segment 0 (00’0000 ‘1’: External ROM area mapped to segment 1 (01’0000 Note: ROMS1 = ‘0’ is recommended. STKSZ System Stack Size (2 … 0) Selects the size ...
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PSW ILVL(3..0) IEN rw rw Bit Function N Negative Result Set, when the result of an ALU operation is negative. C Carry Flag Set, when the result of an ALU operation produces a carry bit. ...
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N-Flag: For most of the ALU operations, the N-flag is set to ‘1’ if the most significant bit of the result contains a ‘1’, otherwise it is cleared. In the case of integer operations the N-flag can be interpreted ...
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V-flag, the C-flag allows the evaluation of the rounding error with a finer resolution (see Table 4-3). For Boolean bit operations with only one operand the V-flag is always cleared. For Boolean bit operations with two operands the V-flag represents ...
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MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered. CPU Interrupt Status (IEN, ...
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CSP Bit Function SEGNR Segment Number (7 … 0) Specifies the code segment, from where the current instruction fetched. SEGNR ...
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Code Segment FF’FFFF H 255 254 FE’0000 H 1 01’0000 H 0 00’0000 H Figure 4-14 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. The Data Page ...
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DPP2 DPP3 Bit Function DPPxPN Data ...
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Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the updating of the DPP register by the instruction. 1023 1022 1021 ...
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Note the user's responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur. • Do not set ...
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Short 4-Bit GPR Addresses (mnemonic Rb) specify an address relative to the memory location specified by the contents of the CP register, i.e. the base of the current register bank. Depending on whether a relative word (Rw) or ...
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This mechanism is supported by the STKOV and STKUN registers (see respective descriptions below). The SP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to ...
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Automatic system stack flushing allows the use of the system stack as a “Stack Cache” for a bigger external user stack. In this ...
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SUB instructions or by PUSH or POP operations (explicit or implicit, i.e. CALL or RET instructions). This control mechanism is not triggered, i.e. no stack trap is generated, when • the stack pointer SP is directly updated via MOV instructions ...
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MDL Bit Function mdl Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide ...
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After the completion of the new division or multiplication the state of the interrupted multiply or divide ...
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IDCHIP CHIPID(7..0) r Bit Function CHIPREVNU Device Revision Code (7 … 0) Identifies the device step where the first release is marked ‘01 CHIPID Device Identification (7 … 0) Identifies the device name. IDMANUF 15 ...
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Interrupt and Trap Function ...
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Interrupt and Trap Functions The C166 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources either by the CPU itself or external, i.e. peripherals connected to the XBUS or ...
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The control register contains the interrupt request flag, the interrupt enable bit, and the interrupt priority of the associated node. The C166 architecture provides a vectored interrupt ...
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Table 5-1 Interrupt Allocation Table (cont’d) Source of Interrupt or PEC Service Request External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 ...
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Table 5-1 Interrupt Allocation Table (cont’d) Source of Interrupt or PEC Service Request Realtime Clock PECC Link IRQ Note: Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction. The respective vector location ...
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Table 5-2 (cont’d) Exception Condition Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction Normal Interrupt Processing and PEC Service During each instruction cycle ...
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Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization; the upper 8 ...
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Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines ...
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Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated. Upon entry into the interrupt service routine the priority ...
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The table below shows a few examples of each action executed with each particular programming of an interrupt control register. Priority Level ILVL GLVL COUNT = CPU interrupt, level 15, group priority 3 ...
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PSW ILVL IEN rw rw Bit Function CPU status flags (Described in Chapter 4.6) MULIP, Define the current status of the CPU (ALU, multiplication unit). USR0 HLDEN HOLD Enable (Enables ...
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CPU. However requests that have already entered the pipeline at that time will be processed. When IEN is set to ‘1’, all interrupt sources, which have been individually enabled by the interrupt enable bits in their ...
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PECCx CLT Bit Function COUNT PEC Transfer Count (7 … 0) Counts PEC transfers (bytes or words) and influences the channel’s action. BWT Byte / Word Transfer Selection 0: ...
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Increment Control Field INC controls, if one of the PEC pointers is incremented after the PEC transfer. However not possible to increment both pointers. If the pointers are not modified (INC = ‘00’) the respective channel will always ...
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Note: PEC transfers are only executed if their priority level is higher than the CPU level, i.e. only PEC channels 7 … 4 are processed, while the CPU executes on level 14. All interrupt request sources that are enabled and ...
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PEC control register the enabled CL flag and if its transfer count is more than zero. Note: With the last transfer of a block transfer (COUNT = 0), the channel link control flag CL of that ...
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CLISNC Bit Function xxIE PEC Channel Link Interrupt Enable Control Bit (individually enables/disables a specific channel pair interrupt request) ‘0’: PEC interrupt request is disabled ‘1’: ...
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DSTP7 SRCP7 DSTP6 SRCP6 DSTP5 SRCP5 DSTP4 SRCP4 Figure 5-2 Mapping of PEC Offset Pointers into the Internal RAM The pointer locations for inactive PEC channels may be used for general data storage. Only the required pointers occupy RAM locations. ...
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Table 5-4 PEC Segment Number Register Addresses Register Address PECSN0 FED0 / 68 H PECSN1 FED2 / 69 H PECSN2 FED4 / 6A H PECSN3 FED6 / word data transfer is selected for a specific PEC ...
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Classes with members can be established by using the same interrupt priority (ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality is built-in and handled automatically by the interrupt controller. Classes with more ...
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Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the ...
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When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in reverse order, taking into account the value of bit SGTDIS. Context Switching An interrupt service routine usually saves all the ...
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All instructions in the pipeline, including instruction N (during which the interrupt request flag is set), are completed before entering the service routine. The actual execution time for these instructions (e.g. wait-states) therefore influences the interrupt response time. In Figure ...
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N require external operand read accesses, instructions N-3 through N write back external operands, and the interrupt vector also points to an external location. In this case the interrupt response time is the time needed to perform 9 word ...
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Pipeline Stage FETCH DECODE EXECUTE WRITEBACK 1 IR-Flag 0 Figure 5-5 Pipeline Diagram for PEC Response Time In Figure 5-5, the respective interrupt request flag is set in cycle 1 (fetching instruction N). The indicated source wins the prioritization round ...
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If instruction N reads the PSW and instruction N-1 effects the condition flags, the PEC response time may additionally be extended by 2 state times. The worst case PEC response time during internal code memory program execution adds to ...
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The 8 lines can be programmed individually to this fast interrupt mode, where the trigger transition (rising, falling or both) can also be selected. The External Interrupt Control register EXICON controls this feature for all 8 signals. EXICON (F1C0 / ...
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TRAP instruction must be terminated with a RETI (return from interrupt) instruction to ensure correct operation. Note: The CPU level in register PSW is not modified by the TRAP instruction, so the service routine ...
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The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the kind of trap which caused the exception. Each trap function is indicated by a separate request flag. When a hardware trap occurs, the corresponding request flag ...
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Class A traps have the third highest priority (trap priority II), class B traps are on the 4rd rank so a class A trap can interrupt a class B trap. If more than one class A trap occurs at a ...
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Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP. When an implicit decrement of the SP is made through a PUSH or ...
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Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address, the ILLOPA flag in the TFR register is set and the CPU enters the illegal word operand access trap routine. ...
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EXISEL EXI7SS EXI6SS EXI5SS rw rw Bit Function EXIxSS External Interrupt x Source Selection Field ( … Input from default pin 0 1: Input from “alternate source” Input ...
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System Control & Configuration ...
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System Control & Configuration M2 has extended features for system level control and configuration. Most of these features are now handled by a new block inside the M2 which is the System Control Unit (SCU). The SCU is used ...
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Reset conditions are indicated in the WDTCON register. Hardware Reset A hardware reset is triggered asynchronously by a falling edge of the reset input signal, RSTIN. To ensure the recognition of the RSTIN signal, it must be held low for ...
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X- Bus cycle. 6.1.1 Behavior of I/Os during Reset During the internal reset sequence all of the M2’s I/O pins are configured as inputs by clearing the ...
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The system start-up configuration is determined by the level on PORT4 at the end of the internal reset sequence. During reset internal pull-up ...
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Chip Select Line Pin P4.1 (CSENA) defines the external memory configuration. When pulled low it enables chip select 3 (CS3) (a second ROM device is assumed). RP0H.1 = ‘0’ denotes the memory configuration with only one ROM device while RP0H.1 ...
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Register Write Protection The System Control Unit (SCU) provides two different protection types of configuration registers: • Unprotected Registers • Protectable Registers The unprotected registers allow the reading and writing (if not read-only) of register values without any restrictions. ...
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The new password is defined with command 3 and stored in the according 8-bit field in the SCUSLS register. The SCUSLC register is defined as follows SCUSLC Bit Function Command Code of Command to be ...
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SCUSLS STATE Bit Function PASSWORD Current Password SL Current Security Level ‘00’: Unprotected Write Mode ‘01’: Low Protected Mode ‘10’: Reserved ‘11’: Write Protected Mode STATE Current State ‘000’: State 0 = ...
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The following state diagram shows the state machine for security level switching and for unlock command execution in low protected mode: Reset Command 4 and Low Protected Mode Any SCU Register Write Access State 4 Figure 6-1 State Machine for ...
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Power Reduction Modes Three power reduction modes with different levels of power reduction, which may be entered under software control, have been implemented in M2: Idle Mode: The CPU is stopped, while the peripherals including watchdog timer continue their ...
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Power down mode can only be terminated with hardware reset. To prevent unintentional entry into Idle mode, the IDLE instruction has been implemented as a protected 32-bit instruction. Mode Idle Entry by … writing SLEEPCON ...
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Active Mode Figure 6-2 Transitions between Idle Mode and Active Mode Any interrupt request, whose individual Interrupt Enable flag was set before Idle mode was entered, will terminate Idle mode regardless of the current CPU priority. The CPU will not ...
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Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU is stopped, while all peripherals continue their operation in the same way previously described. Therefore all ports pins, which are configured as general purpose output ...
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Pin( LDQM, UDQM XTAL1, XTAL2 RSTIN CSDRAM CSROM CS3 , , MEMCLK, CLKEN CVBS1, CVBS2 CORBLA HSYNC, VSYNC The external write strobe WR controls the data transfer from the external memory. During ...
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Alternatively BLANK can be generated as a separate output signal. COR can be generated separately as well, in which case no RSTOUT is available. HSYNC and VSYNC are bidirectional pins which are ...
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WDT DISWDT Figure 6-3 WDT Block Diagram The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is ...
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SRVWDT does not match the format for protected instructions, the Protection Fault Trap will be entered, rather than the instruction being executed. The time period for an overflow of the watchdog timer is programmable in two ways: • The input ...
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Bit Function WDTIN Watchdog Timer Input Frequency Selection 0: Input frequency is 1: Input frequency is WDTR Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruction. SWR Software Reset Indication Flag SHWR Short Hardware ...
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The reset indication flags are not mutually exclusive, e.g. more than one flag may be set after reset depending on its source. The table below summarizes the possible combinations: Table 6-2 Reset Indication Flag Combinations Reset Source Long Hardware Reset ...
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RSTIN P4.0 RxD0 TxD0 CSP:IP 1) BSL initialization time, > 1.5 2) Zero byte (1 start bit, eight ’0’ data bits, 1 stop bit), sent by host 3) Identification byte (D5 ) sent bytes of ...
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BSL mode. All code fetches to segment 0 are made from the special Boot-ROM, while data accesses read from the external user ROM. 6.9 Identification Registers A set of 8 identification registers are provided to ...
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Bit Function MANUF Manufacturer This is the JEDEC normalized manufacturer code. 0C1 : Infineon Technologies H 020 : SGS-Thomson H DEPT Department Indicates the department within Infineon Technologies CAD Macrocells H 02 ...
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Bit Function Size Size of On-chip Program Memory The size of the implemented program memory in terms blocks, i.e. Memory-size = <Size> Type Type of On-chip Program Memory Identifies the memory type on this silicon ...
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Bit Function RIX Redesign Index 0: This device is the original “Revision”. else: This device has experienced minor changes that are not reflected to the customer by the “Revision” bit field. RA Redundancy Activation 0: This device ...
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Parallel Ports M2 provides input/outputs, 6 output and 6 input multiple purpose ports. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports ...
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P2.15 P2.14 P2.13 P2.12 P2.11 P2. Bit Function P2.y Port data register P2 bit y. DP2 DP2. DP2. DP2. DP2. DP2 ...
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Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. All port lines can be switched into push/pull or open drain mode via the ...
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Bit Function ODP3.y Port 3 Open Drain control register bit y ODP3 Port line P3.y output driver in push/pull mode. ODP3 Port line P3.y output driver in open drain mode. Alternate Functions of Port 3 The ...
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P4L (during reset Bit Function P4L.0 BSLENA (Boot Strap Load Enable) P4L Boot strap loader enabled P4L Boot strap loader disabled P4L.1 CSENA (Chip Select Enable) ...
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The number of segment address lines is selected via P4 during reset. The selected value can be read from bit field SALSEL and CSENA of register RP0H e.g. in order to check the configuration during run time. Port 4 Altern. ...
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Port 5 Pin Alternate Function P5.0 ANA0 Analog Input 0 (Wake Up Function) P5.1 ANA1 Analog Input 1 P5.2 ANA2 Analog Input 2 P5.3 ANA3 Analog Input 3 P5.14 T4EUD Timer 4 External Up/Down Input P5.15 T2EUD Timer 2 External ...
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DP6 Bit Function DP6.y Port direction register DP6 bit y. DP6 Port line P6 input (high-impedance). DP6 Port line P6 output. ODP6 ...
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ALTSEL0P6 Bit Function SELP6.y Alternate Function Control Bit SELP6 General Purpose Port Functionality enabled for Line P6.y. SELP6 Alternate Function enabled for Line P6.y. Users Manual ...
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Peripherals ...
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Peripherals All of the peripherals described in the following paragraphs are clocked with the same f clock as the CPU ( ). Depending on the mode (normal or Idle), this frequency is hw_clk 33.33 MHz or 3 MHz. 7.1 ...
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Each timer has an input line (TxIN) associated with it which serves as the gate control in gated timer mode the count input in counter mode. The count direction (Up / Down) may be programmed via software or ...
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Run Control The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit). Setting bit T3R will start the timer, clearing T3R stops the timer. In gated timer mode, the timer will only run if ...
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Underflow Output Enable) in register T3CON enables the state of T3OTL to be monitored via an external line T3OUT. If this line is linked to an external port pin, which has to be configured as output, T3OTL can be used ...
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BPS1 TxI hw_clk TxUD EXOR TxEUD Figure 7-2 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode The gated timer mode for the core timer T3 is selected by ...
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If T3M = ‘010 ’, the timer is enabled when T3IN shows a low level. A high level at this B line stops the timer. If T3M = ‘011 the timer. In addition, the timer can be turned on or ...
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For counter operation, a port pin associated to line T3IN must be configured as input. The maximum input frequency which is allowed in counter mode is To ensure that a transition of the count input signal which is applied to ...
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T3 occurs. Count direction, changes in the count direction and count requests are monitored through the status bits T3RDIR, T3CHDIR and T3EDGE in register T3CON modified automatically according to the ...
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The maximum input frequency which is allowed in incremental interface mode is 8 (BPS = 01). To ensure that a transition of any input signal is correctly recognized, its level should be held high or low for at least 4 ...
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Forward T3IN T3EUD Contents of T3 Note: This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN, i.e. T3I = ’001 Figure 7-8 Evaluation of the Incremental Encoder Signals Note: Timer T3, operating in ...
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Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode, their operation is the same as described for the core timer T3. The ...
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Table 7-6 Auxiliary Timer (Counter Mode) Input Edge Selection T2I/T4I Triggering Edge for Counter Increment/Decrement None. Counter Tx is disabled Positive transition (rising edge) on TxIN Negative transition (falling edge) on ...
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BPS1 TyI hw_clk TyR ) * Edge Select TxR TxI Note: Line ‘*’ is only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 7-10 Concatenation of Core Timer T3 and ...
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Source/Edge Select TxIN TxI Input ) * Clock Note: Line ‘*’ is only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 7-11 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal loaded ...
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Figure 7-12 shows an example of the generation of a PWM signal using the alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal ...
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Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to ‘101 latched into an auxiliary timer register in response to a signal transition ...
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Functional Description of Timer Block 2 Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6 (referred to as the core timer), and the 16-bit capture/reload register CAPREL. The count direction (Up / ...
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Core Timer T6 The operation of the core timer T6 is controlled by its bit-addressable control register T6CON. Timer 6 Run Bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). Setting ...
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BPS2 T6I hw_clk Figure 7-15 Block Diagram of Core Timer T6 in Timer Mode 7.1.2.2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer mode using the same options for the timer ...
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Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer. Depending on which transition of T6OTL is selected to clock the auxiliary ...
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T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in register T5CON. The maximum input frequency for the capture trigger signal at CAPIN is (BPS2 = ‘01’). To ensure that a transition of ...
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Timer Block 2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for the core timer T6. This mode is selected by setting bit T6SR = ‘1’ in register T6CON. The operation causing ...
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Input Clock Edge Select CAPIN MUX T3IN/ T3EUD CT3 CI Input Clock Figure 7-19 Timer Block 2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a ...
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T6OTL will be toggled. This signal has 8 times more transitions than the signal which is applied to line CAPIN. A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time ...
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T3CON Timer 3 Control Register RDI CH EDG BPS1 R DIR E rh rwh rwh rw Field Bits Type Description T3I [2:0] rw T3M [5:3] rw T3R [6] rw T3UD [7] ...
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Field Bits T3OE [9] T3OTL [10] BPS1 [12:11] rw T3EDGE [13] T3CHDIR [14] T3RDIR [15] Users Manual Type Description rw Overflow/Underflow Output Enable 0 T3 overflow/underflow can not be externally monitored 1 T3 overflow/underflow may be externally monitored via T3OUT ...
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Table 7-9 Timer 3 Input Parameter Selection for Timer Mode and Gated Mode T3I Prescaler for f hw_clk (BPS1 = 00) 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 Table 7-10 Timer ...
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T2CON T4CON Timer 2/4 Control Register EDG IR RDIR DIR E DIS rh rwh rwh rw Field Bits TxI [2:0] TxM [5:3] TxR [6] TxUD [7] TxUDE [8] Users Manual ...
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Field Bits Type Description TxRC [9] rw TxIRDIS [12] rw TxEDGE [13] rwh TxCHDIR [14] rwh TxRDIR [15] rh Users Manual Timer x Remote Control 0 Timer/Counter x is controlled by its own run bit TxR 1 Timer/Counter x is ...
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Table 7-12 Timer x Input Parameter Selection for Timer Mode and Gated Mode T3I Prescaler for f hw_clk (BPS1 = 00) 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 Table 7-13 Timer ...
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T6CON Timer 6 Control Register BPS2 SR CLR Field Bits Type Description T6I [2:0] rw T6M [5:3] rw T6R [6] rw T6UD [7] rw T6OTL [10] rwh BPS2 ...
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Table 7-15 Timer 6 Input Parameter Selection for Timer Mode and Gated Mode T6I Prescaler for f (BPS2 = 00) hw_clk 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 512 Table 7-16 Timer ...
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T5CON Timer 5 Control Register CLR Field Bits Type Description T5I [2:0] rw T5M [5:3] rw T5R [6] rw T5UD [7] rw T5RC [9] rw ...
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Field Bits CI [13:12] rw T5CLR [14] T5SC [15] Table 7-17 Timer 5 Input Parameter Selection for Timer Mode and Gated Mode T5I Prescaler for f (BPS2 = 00) hw_clk 000 4 001 8 010 16 011 32 100 64 ...
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Table 7-18 Timer 5 Input Parameter Selection for Counter Mode T5I Triggering Edge for Counter Update X00 None. Counter T5 is disabled 001 Reserved. Do not use this combination. 010 Reserved. Do not use this combination. 011 Reserved. Do not ...
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Table 7-19 Peripheral Name Interrupt Sources (cont’d) Interrupt Interrupt Node Rotation T2IC Direction Change Timer 2 Edge Detection T2IC Timer 2 Rotation T3IC Direction Change Timer 3 Edge Detection T3IC Timer 3 Rotation T4IC Direction Change Timer 4 Edge Detection ...
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Real-time Clock 7.2.1 General Description The Real Time Clock (RTC) module basically an independent timer chain and counts time ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can ...
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MHz RTCR T14REL(16 Bit) T14_IN T14(16 Bit) Figure 7-21 RTC Block Diagram RTC Control The operating behavior of the RTC module is controlled by the RTCCON register. The RTC starts counting by setting the RTCR run bit. After reset, ...
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RTCRELH = FA04 , counter T14 generates one overflow per millisecond, RTCL0 one H per second, RTCL1 one per minute, RTCH2 one per hour and RTCH3 one per day. 48-bit Timer Operation The concatenation of the 16-bit reload timer T14 ...
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Note: Bit RTCR is set on hardware reset. T14 Bit Function TIMER14 16 Bit Timer Register (15 … 0) Timer T14 generates the input clock for the RTC register and the periodic interrupt. T14REL 15 ...
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RTCH RTCH3(9.. 0) Bit Function RTCH3 (9 … 0) High Word of 32 Bit Capture Register. RTCH2 (5 … 0) RTCRELL RTCRELL1 Bit Function RTCRELL1 (5 … 0) ...
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RTC Interrupt Subnode Control RTCISNC Bit Function T14IR T14 Overflow Interrupt Request Flag ‘0’: No request pending. ‘1’: This source has raised an interrupt request. T14IE T14 Overflow Interrupt Enable ...
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ISNC Bit Function RTCINTIR RTC Interrupt Request Flag ‘0’: No request pending. ‘1’: RTC has raised an interrupt request. RTCINTIE RTC Interrupt Enable Control Bit ‘0’: Interrupt request is disabled. ...
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Asynchronous/Synchronous Serial Interface The Asynchronous/Synchronous Serial Interface ASC0 provides serial communication between M2 and other microcontrollers, microprocessors or external peripherals. It provides the following features: • Full duplex asynchronous operating modes – 9-bit data frames, LSB first ...
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Asynchronous Mode Prescaler/ 33 MHz Fractional Divider Autobaud Detection RxD IrDA Decoding Synchronous Mode ÷ MOD ÷ 3 Shift Clock TxD Note: RxDI and RxDO are concatenated in the port logic to pin RxD. Figure 7-22 ...
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Ports & Direction Control Alternate Functions ODP3 DP3 P3 RxD0/P3.11 TxD0/P3.10 ODP3 Port 3 Open Drain Control Register DP3 Port 3 Direction Control Register S0BG ASC0 Baud Rate Generator/Reload Register S0TBUF ASC0 Transmit Buffer Register S0TIC ASC0 Transmit Interrupt Control ...
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Data reception is enabled by the receiver enable bit S0REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) receive ...