IDT74FCT388915T100 Integrated Device Technology, Inc., IDT74FCT388915T100 Datasheet
IDT74FCT388915T100
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IDT74FCT388915T100 Summary of contents
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... SYNC (1) REF_SEL 0 PLL_EN FREQ_SEL OE/RST The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER PIN CONFIGURATIONS FEEDBK 5 REF_SEL 6 SYNC(0) 7 J28-1, V (AN L28 GND(AN) 10 SYNC( PLCC/LCC TOP VIEW ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial TERM (2) V Terminal Voltage –0.5 to +4.6 –0.5 to +4.6 with Respect to GND TERM (3) V Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter I Quiescent Power Supply Current CC TTL Inputs HIGH I Dynamic Power Supply CCD (4) Current C Power Dissipation Capacitance PD I Total Power Supply Current ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol t Rise/Fall Time RISE/FALL All Outputs (between 0.8V and 2.0V) PULSE WIDTH (3) t Output Pulse Width Q/2 outputs Q0-Q4, 5, ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER NOTES: 7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER 10 F Low Freq. Bypass Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T NOTES: 1. Figure 2 shows a loop filter and analog isolation scheme which will be ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION- SHIP In this application, the Q/2 output ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER CLOCK @f SYSTEM CLOCK SOURCE DISTRIBUTE CLOCK @f CLOCK @2f at point of use Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication FCT388915T System Level Testing Functionality When the PLL_EN ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER TEST CIRCUITS AND WAVEFORMS / 20PF Pulse D.U.T. Generator R T PROPAGATION DELAY, OUTPUT SKEW SYNC INPUT (SYNC (1) or SYNC ...
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IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type Speed Package Process Blank 100 133 150 388915T 54 74 9.8 MILITARY AND COMMERCIAL ...