IDT74FCT388915T100 Integrated Device Technology, Inc., IDT74FCT388915T100 Datasheet

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IDT74FCT388915T100

Manufacturer Part Number
IDT74FCT388915T100
Description
Manufacturer
Integrated Device Technology, Inc.
Datasheet
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
• 3-State outputs
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from t
• 32/–16mA drive at CMOS output voltage levels
• V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
DESCRIPTION:
ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
FREQ_SEL
1995 Integrated Device Technology, Inc.
(FREQ_SEL = HIGH)
output, one 2 output; all outputs are TTL-compatible
REF_SEL
Integrated Device Technology, Inc.
SYNC (0)
SYNC (1)
The IDT54/74FCT388915T uses phase-lock loop technol-
PLL_EN
CC
OE/RST
= 3.3V
0.3V
0
1
M
u
x
PD
Phase/Freq.
Detector
0
Divide
-By-2
max. spec)
Mux
1
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
( 1)
( 2)
Charge Pump
9.8
9.8
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
the phase/frequency detector, charge pump, loop filter and
VCO. The VCO is designed for a 2Q operating frequency
range of 40MHz to f2Q Max.
skew. The
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
RST
registers at Q,
component as recommended in Figure 3.
1
0
The IDT54/74FCT388915T provides 8 outputs with 350ps
The FREQ_SEL control provides an additional 2 option in
The IDT54/74FCT388915T requires one external loop filter
M
u
x
is low, all the outputs are put in high impedance state and
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Q5
output is inverted from the Q outputs. The 2Q
Q
and Q/2 outputs are reset.
CP
CP
CP
D
D
D
CP
CP
CP
CP
CP
D
D
D
D
D
R
R
R
R
R
R
R
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Controlled
Oscilator
Voltage
IDT54/74FCT388915T
70/100/133/150
PRELIMINARY
LOCK
LF
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
AUGUST 1995
3052 drw 01
1
DSC-4243/1
1

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IDT74FCT388915T100 Summary of contents

Page 1

... SYNC (1) REF_SEL 0 PLL_EN FREQ_SEL OE/RST The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1995 Integrated Device Technology, Inc. 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device ...

Page 2

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER PIN CONFIGURATIONS FEEDBK 5 REF_SEL 6 SYNC(0) 7 J28-1, V (AN L28 GND(AN) 10 SYNC( PLCC/LCC TOP VIEW ...

Page 3

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER ABSOLUTE MAXIMUM RATINGS Symbol Rating Commercial TERM (2) V Terminal Voltage –0.5 to +4.6 –0.5 to +4.6 with Respect to GND TERM (3) V Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 ...

Page 4

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER POWER SUPPLY CHARACTERISTICS Symbol Parameter I Quiescent Power Supply Current CC TTL Inputs HIGH I Dynamic Power Supply CCD (4) Current C Power Dissipation Capacitance PD I Total Power Supply Current ...

Page 5

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE Symbol t Rise/Fall Time RISE/FALL All Outputs (between 0.8V and 2.0V) PULSE WIDTH (3) t Output Pulse Width Q/2 outputs Q0-Q4, 5, ...

Page 6

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER NOTES: 7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in ...

Page 7

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER 10 F Low Freq. Bypass Figure 2. Recommended Loop Filter and Analog Isolation Scheme for the FCT388915T NOTES: 1. Figure 2 shows a loop filter and analog isolation scheme which will be ...

Page 8

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION- SHIP In this application, the Q/2 output ...

Page 9

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER CLOCK @f SYSTEM CLOCK SOURCE DISTRIBUTE CLOCK @f CLOCK @2f at point of use Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication FCT388915T System Level Testing Functionality When the PLL_EN ...

Page 10

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER TEST CIRCUITS AND WAVEFORMS / 20PF Pulse D.U.T. Generator R T PROPAGATION DELAY, OUTPUT SKEW SYNC INPUT (SYNC (1) or SYNC ...

Page 11

IDT54/74FCT388915T 70/100/133/150 3.3V LOW SKEW PLL-BASED CLOCK DRIVER ORDERING INFORMATION IDT XX FCT XXXX Temp. Range Device Type Speed Package Process Blank 100 133 150 388915T 54 74 9.8 MILITARY AND COMMERCIAL ...

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