UPD70F3210GK-9EU Renesas Electronics Corporation., UPD70F3210GK-9EU Datasheet

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UPD70F3210GK-9EU

Manufacturer Part Number
UPD70F3210GK-9EU
Description
Manufacturer
Renesas Electronics Corporation.
Datasheet
User’s Manual
V850ES/KF1
32-bit Single-Chip Microcontrollers
Hardware
Document No. U16891EJ2V0UD00 (2nd edition)
Date Published September 2006 N CP(K)
Printed in Japan
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
PD703208
PD703208(A)
PD703208(A1)
PD703208(A2)
PD703208Y
PD703208Y(A)
PD703208Y(A1)
PD703208Y(A2)
PD703209
PD703209(A)
PD703209(A1)
PD703209(A2)
PD703209Y
PD703209Y(A)
PD703209Y(A1)
PD703209Y(A2)
2004
μ
μ
μ
μ
μ
μ
μ
μ
μ
μ
PD703210
PD703210(A)
PD703210(A1)
PD703210(A2)
PD703210Y
PD703210Y(A)
PD703210Y(A1)
PD703210Y(A2)
PD703211
PD703211Y
μ
μ
μ
μ
μ
μ
μ
μ
PD70F3210
PD70F3210(A)
PD70F3210Y
PD70F3210Y(A)
PD70F3210H
PD70F3210HY
PD70F3211H
PD70F3211HY

Related parts for UPD70F3210GK-9EU

UPD70F3210GK-9EU Summary of contents

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User’s Manual V850ES/KF1 32-bit Single-Chip Microcontrollers Hardware μ PD703208 μ PD703208(A) μ PD703208(A1) μ PD703208(A2) μ PD703208Y μ PD703208Y(A) μ PD703208Y(A1) μ PD703208Y(A2) μ PD703209 μ PD703209(A) μ PD703209(A1) μ PD703209(A2) μ PD703209Y μ PD703209Y(A) μ PD703209Y(A1) μ PD703209Y(A2) Document ...

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User’s Manual U16891EJ2V0UD ...

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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...

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Caution: PD70F3210H, 70F3210HY, 70F3211H, and 70F3211HY use SuperFlash licensed from Silicon Storage Technology, Inc. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and ...

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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of April, ...

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Readers This manual is intended for users who wish to understand the functions of the V850ES/KF1 and design application systems using these products. The target products are as follows. • Standard products: • Special products: Purpose This manual is intended ...

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To find the details of a register where the name is known → Refer to APPENDIX C REGISTER INDEX. To understand the details of an instruction function → Refer to the V850ES Architecture User’s Manual. Register format → The name ...

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Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/KF1 V850ES Architecture User’s Manual V850ES/KF1 Hardware User’s Manual Documents related to development tools (user’s manuals) ...

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CHAPTER 1 INTRODUCTION .................................................................................................................18 1.1 K1 Series Product Lineup ......................................................................................................... 18 1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup..................................................................................18 1.1.2 78K0/Kx1+, 78K0/Kx1 products lineup ...........................................................................................21 1.2 Features ...................................................................................................................................... 24 1.3 Applications................................................................................................................................ 25 1.4 Ordering Information ................................................................................................................. 26 1.5 Pin Configuration (Top View).................................................................................................... 30 ...

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Port CT ........................................................................................................................................ 115 4.3.10 Port DL......................................................................................................................................... 117 4.4 Block Diagrams ........................................................................................................................ 120 4.5 Port Register Setting When Alternate Function Is Used...................................................... 144 4.6 Cautions .................................................................................................................................... 149 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) .................................................. ...

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Functions .................................................................................................................................. 184 7.3 Configuration............................................................................................................................ 185 7.4 Registers................................................................................................................................... 187 7.5 Operation .................................................................................................................................. 198 7.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000)..................................................................199 7.5.2 External event count mode (TP0MD2 to TP0MD0 bits = 001)......................................................209 7.5.3 External trigger pulse output ...

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Functions .................................................................................................................................. 361 10.2 Configuration............................................................................................................................ 361 10.3 Registers ................................................................................................................................... 364 10.4 Operation .................................................................................................................................. 368 10.4.1 Operation as interval timer/square wave output........................................................................... 368 10.4.2 PWM output mode operation ....................................................................................................... 371 10.4.3 Carrier generator mode operation................................................................................................ 377 CHAPTER 11 INTERVAL TIMER, ...

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A/D conversion operation .............................................................................................................424 14.4.3 Power fail monitoring function.......................................................................................................424 14.4.4 Setting procedure .........................................................................................................................425 14.5 Cautions.................................................................................................................................... 426 14.6 How to Read A/D Converter Characteristics Table .............................................................. 432 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART) .....................................................436 15.1 Features .................................................................................................................................... 436 15.2 Configuration............................................................................................................................ ...

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Configuration............................................................................................................................ 527 18.3 Registers ................................................................................................................................... 529 18.4 Functions .................................................................................................................................. 543 18.4.1 Pin configuration .......................................................................................................................... 543 2 18 Bus Definitions and Control Methods .............................................................................. 544 18.5.1 Start condition.............................................................................................................................. 544 18.5.2 Addresses.................................................................................................................................... 545 18.5.3 Transfer direction specification .................................................................................................... 546 ...

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In-service priority register (ISPR)..................................................................................................618 19.3.7 ID flag ...........................................................................................................................................619 19.3.8 Watchdog timer mode register 1 (WDTM1) ..................................................................................620 19.4 External Interrupt Request Input Pins (NMI, INTP0 to INTP6) ............................................. 621 19.4.1 Noise elimination ..........................................................................................................................621 19.4.2 Edge detection..............................................................................................................................621 19.5 Software Exceptions................................................................................................................ 624 ...

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Overview ................................................................................................................................... 662 23.2 Operation .................................................................................................................................. 662 CHAPTER 24 ROM CORRECTION FUNCTION................................................................................. 664 24.1 Overview ................................................................................................................................... 664 24.2 Registers ................................................................................................................................... 665 24.3 ROM Correction Operation and Program Flow ..................................................................... 666 CHAPTER 25 FLASH MEMORY (SINGLE POWER) ........................................................................ 668 25.1 ...

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Setting ..........................................................................................................................................708 27.2 Cautions.................................................................................................................................... 709 CHAPTER 28 ELECTRICAL SPECIFICATIONS (256 KB MASK ROM VERSION, SINGLE- POWER FLASH MEMORY VERSION) .......................................................................710 CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION OF 128 KB OR LESS AND TWO-POWER FLASH MEMORY VERSION), ...

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K1 Series Product Lineup 1.1.1 V850ES/Kx1+, V850ES/Kx1 products lineup • 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) V850ES/KE1 μ PD70F3207HY μ PD70F3207H Single-power flash: 128 ...

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The function list of the V850ES/Kx1+ is shown below. Product Name V850ES/KE1+ Number of pins Internal Mask ROM 128 memory − Flash memory (KB) RAM Supply voltage 2.7 to 5.5 V Minimum instruction execution time 50 ns @20 MHz Clock ...

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The function list of the V850ES/Kx1 is shown below. Product Name V850ES/KE1 Number of pins Internal Mask ROM 128 memory (KB) − Flash memory RAM Supply voltage 2.7 to 5.5 V Minimum instruction execution time 50 ns @20 MHz Clock ...

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SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 μ PD78F0103 Two-power flash: 24 KB, RAM: 768 B 44-pin LQFP (10 × 0.8 mm pitch) 78K0/KC1 μ PD78F0114 Two-power flash: 32 KB, RAM: 1 ...

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The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 Item Number of pins Internal Mask ROM 8 memory (KB) Flash memory RAM 0.5 Power supply voltage Minimum instruction execution time 0.166 4.0 to 5.5 V) μ ...

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The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ Item Number of pins 30 pins Internal Flash memory 8 memory RAM 0.5 (KB) Power supply voltage Minimum instruction execution time 0.125 0.238 Clock Crystal/ceramic RC Subclock ...

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Features Minimum instruction execution time (operation at main clock (f General-purpose registers: 32 bits × 32 registers Signed multiplication (16 × 16 → 32 clocks CPU features: (Instructions without creating register hazards can be ...

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Serial interface Asynchronous serial interface (UART): 3-wire serial I/O (CSI0): 3-wire serial I/O (with automatic transmit/receive function) (CSIA): 1 channel bus interface (I μ ( PD703208Y, 703209Y, 703210Y, 703211Y, 70F3210Y, 70F3210HY, 70F3211HY) A/D converter: 10-bit resolution × ...

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Ordering Information <R> (1) Standard products (1/2) Part Number μ PD703208GC-xxx-8BT μ PD703208GC-xxx-8BT-A μ PD703208YGC-xxx-8BT μ PD703208YGC-xxx-8BT-A μ PD703208GK-xxx-9EU μ PD703208GK-xxx-9EU-A μ PD703208YGK-xxx-9EU μ PD703208YGK-xxx-9EU-A μ PD703209GC-xxx-8BT μ PD703209GC-xxx-8BT-A μ PD703209YGC-xxx-8BT μ PD703209YGC-xxx-8BT-A μ PD703209GK-xxx-9EU μ PD703209GK-xxx-9EU-A μ PD703209YGK-xxx-9EU ...

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Standard products (2/2) Part Number μ 80-pin plasticQFP (14 × 14) PD70F3210GC-8BT μ 80-pin plasticQFP (14 × 14) PD70F3210GC-8BT-A μ 80-pin plasticQFP (14 × 14) PD70F3210YGC-8BT μ 80-pin plasticQFP (14 × 14) PD70F3210YGC-8BT-A μ 80-pin plasticTQFP (fine pitch) (12 ...

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Part Number μ 80-pin plastic QFP (14 × 14) PD703208GC(A)-xxx-8BT μ 80-pin plastic QFP (14 × 14) PD703208GC(A)-xxx-8BT-A μ 80-pin plastic QFP (14 × 14) PD703208YGC(A)-xxx-8BT μ 80-pin plastic QFP (14 × 14) PD703208YGC(A)-xxx-8BT-A μ 80-pin ...

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Part Number μ 80-pin plastic QFP (14 × 14) PD703208GC(A1)-xxx-8BT μ 80-pin plastic QFP (14 × 14) PD703208YGC(A1)-xxx-8BT μ 80-pin plastic TQFP (fine pitch) (12 × 12) PD703208GK(A1)-xxx-9EU μ 80-pin plastic TQFP (fine ...

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Pin Configuration (Top View) 80-pin plastic QFP (14 × 14) 80-pin plastic TQFP (fine pitch) (12 × 12) μ PD703208GC-xxx-8BT μ PD703208GC-xxx-8BT-A μ PD703208YGC-xxx-8BT μ PD703208YGC-xxx-8BT-A μ PD703208GK-xxx-9EU μ PD703208GK-xxx-9EU-A μ PD703208YGK-xxx-9EU μ PD703208YGK-xxx-9EU-A μ PD703209GC-xxx-8BT μ PD703209GC-xxx-8BT-A μ ...

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AV 1 REF0 P00/TOH0 3 P01/TOH1 4 P02/NMI 5 P03/INTP0 6 P04/INTP1 7 Note 1 Note 1 ...

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Pin identification AD0 to AD15: Address/data bus Analog input ANI0 to ANI7: ASCK0: Asynchronous serial clock ASTB: Address strobe AV : Analog reference voltage REF0 AV : Ground for analog SS CLKOUT: Clock output CS0, CS1: Chip select EV : ...

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Function Block Configuration (1) Internal block diagram NMI INTC INTP0 to INTP6 16-bit TI000, TI001, TI010, TI011 timer/event counter TO00, TO01 16-bit timer/ Note 3 TIP00, TIP01 event counter Note 3 TOP00, TOP01 Note 3 P ...

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Internal units (a) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other types of instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 ...

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CHAPTER 1 INTRODUCTION (h) Watch timer This timer counts the reference time (0.5 seconds) for counting the clock from the subclock (32.768 kHz (32.768 kHz) from the clock generator. At the same time, the watch timer can be ...

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Ports As shown below, the following ports have general-purpose port functions and control pin functions. Port I/O P0 7-bit I/O NMI, external interrupt, timer output P3 8-bit I/O Serial interface, timer I/O P4 3-bit I/O Serial interface P5 6-bit ...

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Overview of Functions μ Part Number PD703208/ μ PD703208Y Internal ROM 64 KB memory High-speed RAM 4 KB Buffer RAM Memory Logical space space External memory area External bus interface General-purpose registers Main clock Ceramic/crystal/external clock (oscillation frequency) When ...

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The names and functions of the pins of the V850ES/KF1 are described below, divided into port pins and non-port pins. The pin I/O buffer power supplies are divided into two systems; AV power supplies and the pins is shown below. ...

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List of Pin Functions (1) Port pins Pin Name Pin No. I/O On-Chip Pull-up Resistor P00 3 I/O Yes P01 4 P02 5 P03 6 P04 7 P05 17 P06 18 P30 22 I/O Yes P31 23 P32 24 ...

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Pin Name Pin No. I/O On-Chip Pull-up Resistor P90 38 I/O Yes P91 39 P96 40 P97 41 P98 42 P99 43 P913 44 P914 45 P915 46 PCM0 49 I/O No PCM1 50 PCM2 51 PCM3 52 PCS0 47 ...

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Non-port pins Pin Name Pin No. I/O On-Chip Pull-up Resistor AD0 57 I/O No AD1 58 AD2 59 AD3 60 AD4 61 AD5 62 AD6 63 AD7 64 AD8 65 AD9 66 AD10 67 AD11 68 AD12 69 AD13 ...

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Pin Name Pin No. I/O On-Chip Pull-up Resistor INTP0 6 Input Yes INTP1 7 INTP2 17 INTP3 18 INTP4 44 INTP5 45 INTP6 46 KR0 32 Input Yes KR1 33 KR2 34 KR3 35 KR4 36 KR5 37 KR6 38 ...

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Pin Name Pin No. I/O On-Chip Pull-up Resistor SO00 20 Output Yes SO01 42 SOA0 36 TI000 25 Input Yes TI001 26 TI010 27 TI011 32 TI50 33 TI51 40 Note 1 TIP00 25 Note 1 TIP01 26 TO00 25 ...

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Pin Status The address bus becomes undefined during accesses to the internal RAM and ROM. The data bus goes into the high-impedance state without data output. The external bus control signal becomes inactive. During peripheral I/O access, the address ...

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Pin I/O Circuits and Recommended Connection of Unused Pins Pin Alternate Function P00 TOH0 P01 TOH1 P02 NMI P03 to P06 INTP0 to INTP3 P30 TXD0 P31 RXD0 P32 ASCK0 P33 TI000/TO00/TIP00 P34 TI001/TIP01 P35 TI010/TO01 Note 2 P38 ...

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Pin Alternate Function PDL0 to PDL4 AD0 to AD4 Note 1 PDL5 AD5/FLMD1 PDL6 to PDL15 AD6 to AD15 AV – REF0 AV – – – SS Note 1 FLMD0 – Note 2 IC – RESET ...

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Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type Data P-ch Output N-ch disable Input enable Type 5-A Pull-up enable V DD Data P-ch Output N-ch disable Input enable Type 5-W Pull-up enable ...

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Type 10-F Pull-up enable Data Open drain Output disable Input enable Type 13-AD <R> Data Output disable Input enable Remark Read Also, read CHAPTER 2 PIN FUNCTIONS V DD Type 13-AE P-ch ...

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The CPU of the V850ES/KF1 is based on the RISC architecture and executes most instructions in one clock cycle by using 5-stage pipeline control. 3.1 Features Number of instructions: Minimum instruction execution time: 50 MHz operation: 4.5 ...

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CPU Register Set The CPU registers of the V850ES/KF1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers have 32-bit width. For details, refer to the V850ES Architecture ...

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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers r31, are available. All of these registers can be used as a data variable ...

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System register set System registers control the status of the CPU and hold interrupt information. Read from and write to system registers are performed by setting the system register numbers shown below with the system register load/store instructions (LDSR, ...

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Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the ...

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NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the ...

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Program status word (PSW) The program status word (PSW collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the ...

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Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation ...

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Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and ...

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Operating Modes The V850ES/KF1 has the following operating modes. (1) Normal operating mode After the system has been released from the reset state, the pins related to the bus interface are set to the port mode, execution branches to ...

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Address Space 3.4.1 CPU address space For instruction addressing combined total external memory area and internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) ...

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Wraparound of CPU address space (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. Even if a carry or borrow ...

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Memory map The V850ES/KF1 has reserved areas as shown below. Figure 3-2. Data Memory Map (Physical Addresses) 3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH Use-prohibited area 0210000H 020FFFFH External memory area (64 KB) 0200000H 01FFFFFH (2 MB) 0000000H Note Fetch access ...

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CHAPTER 3 CPU FUNCTIONS Figure 3-3. Program Memory Map Use-prohibited area (Program fetch disabled area) Internal RAM area (60 KB) Use-prohibited area (Program fetch disabled ...

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Areas (1) Internal ROM area An area from 0000000H to 00FFFFFH is reserved for the internal ROM area. (a) Internal ROM (256 KB) A 256 KB area from 0000000H to 003FFFFH is provided in the following ...

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Internal ROM (96 KB area from 0000000H to 0017FFFH is provided in the following products. Addresses 0018000H to 00FFFFFH are an access-prohibited area. • μ PD703209, 703209Y (d) Internal ROM (64 KB area ...

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Internal RAM area An area maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area. (a) Internal RAM (12 KB area from 3FFC000H to 3FFEFFFH is provided as physical internal RAM ...

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Internal RAM (4 KB area from 3FFE000H to 3FFEFFFH is provided as physical internal RAM in the following products. Addresses 3FF0000H to 3FFD7FFH are an access-prohibited area. • μ PD703208, 703208Y, 703209, 703209Y Physical address space ...

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On-chip peripheral I/O area area from 3FFF000H to 3FFFFFFH is reserved as the on-chip peripheral I/O area. Figure 3-11. On-Chip Peripheral I/O Area Physical address space 3FFFFFFH 3FFF000H Peripheral I/O registers assigned with functions such as ...

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Recommended use of address space The architecture of the V850ES/KF1 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. The address stored in this pointer ...

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Data space With the V850ES/KF1, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25 26-bit address is sign-extended to 32 bits and ...

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Figure 3-12. Recommended Memory Map Program space ...

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Peripheral I/O registers Address Function Register Name FFFFF004H Port DL register FFFFF004H Port DL register L FFFFF005H Port DL register H FFFFF008H Port CS register FFFFF00AH Port CT register FFFFF00CH Port CM register FFFFF024H Port DL mode register FFFFF024H ...

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Address Function Register Name FFFFF128H Interrupt control register FFFFF12AH Interrupt control register FFFFF12CH Interrupt control register FFFFF12EH Interrupt control register FFFFF130H Interrupt control register FFFFF132H Interrupt control register FFFFF134H Interrupt control register FFFFF136H Interrupt control register FFFFF138H Interrupt control register ...

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Address Function Register Name FFFFF412H Port 9 register FFFFF412H Port 9 register L FFFFF413H Port 9 register H FFFFF420H Port 0 mode register FFFFF426H Port 3 mode register FFFFF426H Port 3 mode register L FFFFF427H Port 3 mode register H ...

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Address Function Register Name FFFFF5A4H TMP0 I/O control register 2 FFFFF5A5H TMP0 option register 0 FFFFF5A6H TMP0 capture/compare register 0 FFFFF5A8H TMP0 capture/compare register 1 FFFFF5AAH TMP0 counter read buffer register FFFFF5C0H 16-bit timer counter 5 FFFFF5C0H 8-bit timer counter ...

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Address Function Register Name FFFFF706H Port 3 function control expansion register FFFFF802H System status register FFFFF806H PLL control register FFFFF820H Power save mode register FFFFF828H Processor clock control register FFFFF840H Correction address register 0 FFFFF840H Correction address register 0L FFFFF842H ...

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Address Function Register Name FFFFFC40H Pull-up resistor option register 0 FFFFFC46H Pull-up resistor option register 3 FFFFFC48H Pull-up resistor option register 4 FFFFFC4AH Pull-up resistor option register 5 FFFFFC52H Pull-up resistor option register 9 FFFFFC52H Pull-up resistor option register 9L ...

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Address Function Register Name FFFFFD47H Automatic data transfer address count register 0 FFFFFD80H IIC shift register 0 FFFFFD82H IIC control register 0 FFFFFD83H Slave address register 0 FFFFFD84H IIC clock selection register 0 FFFFFD85H IIC function expansion register 0 FFFFFD86H ...

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Address Function Register Name FFFFFE16H CSIA0 buffer RAM B FFFFFE16H CSIA0 buffer RAM BL FFFFFE17H CSIA0 buffer RAM BH FFFFFE18H CSIA0 buffer RAM C FFFFFE18H CSIA0 buffer RAM CL FFFFFE19H CSIA0 buffer RAM CH FFFFFE1AH CSIA0 buffer RAM D FFFFFE1AH ...

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Special registers Special registers are registers that prevent invalid data from being written when an inadvertent program loop occurs. The V850ES/KF1 has the following three special registers. • Power save control register (PSC) • Processor clock control register (PCC) ...

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Command register (PRCMD) The PRCMD register is an 8-bit register used to prevent data from being written to registers that may have a large influence on the system, possibly causing the application system to unexpectedly stop, when an inadvertent ...

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CHAPTER 3 CPU FUNCTIONS The operation conditions of the PRERR flag are described below. (a) Set conditions (PRERR = 1) (i) When a write operation to the special register takes place without write operation being performed to the PRCMD register ...

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Cautions (1) Waits on register access Be sure to set the following register before using the V850ES/KF1. • System wait control register (VSWC) After setting the VSWC register, set the other registers as required. When using an external bus, ...

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Peripheral Function Watchdog timer 1 (WDT1) Watchdog timer 2 (WDT2) 16-bit timer/event counter P0 Note 2 (TMP0) 16-bit timer/event counters 00, 01 (TM00, TM01) Clocked serial interface 0 with automatic transmit/receive function (CSIA0) 2 Note Asynchronous serial ...

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Notes 1. In the calculation of number of waits, the fractional part of its result must be multiplied by (1/f and rounded down if (1/f μ 2. PD703211, 703211Y, 70F3211H, and 70F3211HY only available only ...

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Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before ...

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Features Input-only ports: 8 pins I/O ports: 59 pins • Fixed to N-ch open-drain output: 2 • Switchable to N-ch open-drain output: 6 Input/output can be specified in 1-bit units 4.2 Basic Port Configuration The V850ES/KF1 incorporates a total ...

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Port Configuration Item Control registers Port n register (Pn CM, CS, CT, DL) Port n mode register (PMn CM, CS, CT, DL) Port n ...

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Port n register (Pn) Data I/O with external devices is performed by writing to and reading from the Pn register. The Pn register is configured of a port latch that retains the output data and a circuit that reads ...

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Port n mode register (PMn) PMn specifies the input mode/output mode of the port. Each bit of the PMn register corresponds to one pin of port n and can be specified in 1-bit units. After reset: FFH R/W PMn ...

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Port n function control expansion register (PFCEn) PFCEn is a register that specifies the alternate function to be used when one pin has three or more alternate functions. Each bit of the PFCEn register corresponds to one pin of ...

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Pull-up resistor option register (PUn) PUn is a register that specifies the connection of an on-chip pull-up resistor. Each bit of the PUn register corresponds to one pin of port n and can be specified in 1-bit units. After ...

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Port settings Set the ports as follows. Figure 4-1. Register Settings and Pin Functions Port mode Output mode Input mode Alternate function (when two alternate functions are available) Alternate function 1 Alternate function 2 Alternate function (when three or ...

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Port 0 Port 7-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate functions. Table 4-4. Alternate-Function Pins of Port 0 Pin Name Pin No. Alternate Function ...

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Port 0 mode control register (PMC0) After reset: 00H R/W PMC0 0 PMC06 PMC06 0 I/O port INTP3 input 1 PMC05 0 I/O port 1 INTP2 input PMC04 0 I/O port INTP1 input 1 PMC03 0 I/O port INTP0 ...

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Port 3 Port 8-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate functions. Table 4-5. Alternate-Function Pins of Port 3 Pin Name Pin No. Alternate Function ...

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Port 3 register (P3) After reset: 00H (output latch) 15 Note P3 (P3H ) 0 (P3L) 0 P3n output output Note When reading from or writing to bits the ...

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Port 3 mode control register (PMC3) After reset: 0000H 15 Note 1 PMC3 (PMC3H ) 0 (PMC3L) 0 PMC39 0 1 PMC38 0 1 PMC35 0 1 PMC34 0 1 PMC33 0 1 PMC32 0 1 PMC31 0 1 ...

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Port 3 function register H (PF3H) After reset: 00H R/W PF3H 0 PF3n 0 When used as normal port (N-ch open-drain output) 1 When used as alternate-function (N-ch open-drain output) Caution When using P38 and P39 as N-ch open-drain-output ...

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Port 3 function control expansion register (PFCE3) μ Note Only in the PD703211, 703211Y, 70F3211H, 70F3211HY After reset: 00H R/W PFCE3 0 0 Remark For details of specification of alternate-function pins, refer to 4.3.2 (8) Specifying alternate-function pins of ...

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Port 4 Port 3-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 4 includes the following alternate functions. Table 4-6. Alternate-Function Pins of Port 4 Pin Name Pin No. Alternate Function ...

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Port 4 mode control register (PMC4) After reset: 00H R/W PMC4 0 0 PMC42 0 I/O port 1 SCK00 I/O PMC41 0 I/O port 1 SO00 output PMC40 0 I/O port 1 SI00 input (4) Port 4 function register ...

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Port 5 Port 6-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 5 includes the following alternate functions. Table 4-7. Alternate-Function Pins of Port 5 Pin Name Pin No. Alternate Function ...

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Port 5 mode control register (PMC5) After reset: 00H R/W PMC5 0 0 PMC55 0 I/O port/KR5 input 1 SCKA0 I/O/RTP05 output PMC54 0 I/O port/KR4 input 1 SOA0 output/RTP04 output PMC53 0 I/O port/KR3 input 1 SIA0 input/RTP03 ...

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Port 5 function control register (PFC5) After reset: 00H R/W PFC5 0 PFC55 0 SCKA0 I/O 1 RTP05 output PFC54 0 SOA0 output 1 RTP04 output PFC53 0 SIA0 input 1 RTP03 output PFC52 0 TO50 output 1 RTP02 ...

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Port 7 Port 8-bit input-only port for which all the pins are fixed to input. Port 7 includes the following alternate functions. Table 4-8. Alternate-Function Pins of Port 7 Pin Name Pin No. Alternate Function P70 ...

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Port 9 Port 9-bit I/O port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate functions. Table 4-9. Alternate-Function Pins of Port 9 Pin Name Pin No. Alternate Function ...

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Port 9 register (P9) After reset: 00H (output latch) 15 Note P9 (P9H ) P915 P914 (P9L) P97 P96 P9n output output Note When reading from or writing to bits ...

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Port 9 mode control register (PMC9) After reset: 0000H 15 Note PMC9 (PMC9H ) PMC915 PMC97 (PMC9L) PMC915 0 1 PMC914 0 1 PMC913 0 1 PMC99 0 1 PMC98 0 1 PMC97 0 1 PMC96 0 1 PMC91 ...

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Port 9 function register H (PF9H) After reset: 00H R/W PF9H 0 0 PF9n 0 Normal output 1 N-ch open-drain output Caution When using P98 and P99 as N-ch open-drain-output alternate-function pins, set in the following sequence. Be sure ...

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After reset: 0000H 15 Note PFC9 (PFC9H ) PFC910 PFC910 PFC97 (PFC9L) PFC915 1 PFC914 1 PFC913 1 PFC99 1 PFC98 1 PFC97 1 PFC96 1 PFC91 1 PFC90 1 Note When reading from or writing to bits 8 to ...

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Pull-up resistor option register 9 (PU9) After reset: 0000H 15 Note PU9 (PU9H ) PU915 PU914 (PU9L) PU97 PU96 PU9n Control of on-chip pull-up resistor connection ( 15) 0 Not connected ...

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Port CM Port 4-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate functions. Table 4-10. Alternate-Function Pins of Port CM Pin Name Pin No. Alternate Function ...

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Port CM mode control register (PMCCM) After reset: 00H R/W PMCCM 0 0 PMCCM3 0 I/O port 1 HLDRQ input PMCCM2 0 I/O port 1 HLDAK output PMCCM1 0 I/O port 1 CLKOUT output PMCCM0 0 I/O port 1 ...

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Port CS Port 2-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate functions. Table 4-11. Alternate-Function Pins of Port CS Pin Name Pin No. Alternate Function ...

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Port CT Port 4-bit I/O port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate functions. Table 4-12. Alternate-Function Pins of Port CT Pin Name Pin No. Alternate Function ...

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Port CT mode control register (PMCCT) After reset: 00H R/W PMCCT 0 PMCCT6 PMCCT6 0 I/O port 1 ASTB output PMCCT4 0 I/O port 1 RD output PMCCT1 0 I/O port 1 WR1 output PMCCT0 0 I/O port 1 ...

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Port DL Port 16-bit I/O port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate functions. Table 4-13. Alternate-Function Pins of Port DL Pin Name Pin No. Alternate Function ...

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Port DL register (PDL) After reset: 00H (output latch) 15 Note PDL (PDLH ) PDL15 PDL7 (PDLL) PDLn 0 1 Note When reading from or writing to bits the PDL register in 8-bit or 1-bit ...

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Port DL mode control register (PMCDL) After reset: 0000H 15 Note PMCDL (PMCDLH ) PMCDL15 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn 0 1 Note When reading from or writing to bits ...

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Block Diagrams RD WR PMC PORT RD alternate-function 1 120 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of Type A-1 P-ch A/D input signal N-ch Figure 4-3. Block Diagram of Type C-1 PMCmn PMmn Output ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type C-2 WR PMC PMCmn WR PM PMmn Output signal of alternate-function 1 WR PORT Output latch (Pmn) Address RD User’s Manual U16891EJ2V0UD Pmn 121 ...

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Output buffer off signal WR PMC WR PM Output signal of WR alternate-function 1 PORT Output latch RD Remark Output buffer off signal: Signal that is asserted in the IDLE or STOP mode, or when the bus is held. 122 ...

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Figure 4-6. Block Diagram of Type C-4 Output buffer off signal Output enable signal of alternate-function 1 WR PMC PMCmn WR PM PMmn Output signal of WR PORT alternate-function 1 Output latch (Pmn) Input enable signal of alternate-function 1 Input ...

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Figure 4-7. Block Diagram of Type D-1 PMC PORT RD alternate-function 1 Note There are no hysteresis characteristics in the port mode. 124 CHAPTER 4 PORT FUNCTIONS PUmn PMCmn PMmn Output latch (Pmn) Address ...

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Figure 4-8. Block Diagram of Type D-1 PMC PORT Output latch RD alternate-function 1 Note There are no hysteresis characteristics in the port mode. CHAPTER 4 PORT FUNCTIONS PUmn PMCmn PMmn (Pmn) Note Address ...

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PMC WR PM Output signal of WR PORT alternate-function 1 RD 126 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-2 PUmn PMCmn PMmn Output latch (Pmn) Address User’s Manual U16891EJ2V0UD EV DD P-ch Pmn ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type E PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 Output signal of WR alternate-function 1 PORT Output latch (Pmn) RD Address ...

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Figure 4-11. Block Diagram of Type E PFC PFCmn WR PMC PMCmn WR PM Output signal of alternate-function 2 WR PORT Output latch RD Input signal of alternate-function 1 Alternate-function input signal in port mode 128 CHAPTER ...

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Figure 4-12. Block Diagram of Type E PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Output signal of alternate-function 2 Output latch (Pmn) RD Input signal of alternate-function 1 Note There are no hysteresis ...

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Figure 4-13. Block Diagram of Type E PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Output latch (Pmn) RD Input signal of alternate-function 2 Alternate-function input signal in port mode 130 CHAPTER 4 PORT ...

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Figure 4-14. Block Diagram of Type E PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Output latch RD Input signal of alternate-function 2 Note There are no hysteresis characteristics in the port mode. CHAPTER ...

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Figure 4-15. Block Diagram of Type E PUmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 WR PORT Output latch (Pmn) RD Address 132 CHAPTER 4 PORT FUNCTIONS Alternate-function input signal in ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type F PUmn WR PF PFmn WR PMC PMCmn WR PM PMmn WR PORT Output signal of alternate-function 1 Output latch (Pmn) Address RD User’s Manual U16891EJ2V0UD EV DD ...

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Figure 4-17. Block Diagram of Type F PUmn WR PF PFmn WR PMC PMCmn WR PM PMmn WR Output signal of PORT alternate-function 1 Output latch (Pmn) Address Input signal of alternate-function 1 RD Note There are no ...

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CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type G PUmn WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 WR Output signal of PORT alternate-function 1 Output latch ...

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Figure 4-19. Block Diagram of Type G PUmn WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 WR Output signal of PORT alternate-function 1 Output latch (Pmn) RD Address Output ...

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Figure 4-20. Block Diagram of Type G-7 PUmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 4 WR PORT Output signal of alternate-function 2 Output latch (Pmn) Address RD Input ...

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Figure 4-21. Block Diagram of Type G-7 PUmn WR PFCE PFCEmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR Output signal of PORT alternate-function 4 Output latch (Pmn) Address RD Input signal of alternate-function 1 Input ...

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Figure 4-22. Block Diagram of Type G PUmn WR PF PFmn Output enable signal of alternate-function 2 WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 WR PORT Output latch (Pmn) Address Output ...

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Figure 4-23. Block Diagram of Type G PUmn WR PF PFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn Output signal of alternate-function 2 WR PORT Output latch (Pmn) Address RD 140 CHAPTER 4 PORT FUNCTIONS User’s ...

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Figure 4-24. Block Diagram of Type H PUmn WR INTR INTRmn WR INTF INTFmn WR PMC PMCmn WR PM PMmn WR PORT Output latch (Pmn) Address RD Input signal of alternate-function 1 Notes 1. Refer to 19.4 External ...

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Figure 4-25. Block Diagram of Type H PUmn WR INTR INTRmn WR INTF INTFmn WR PFC PFCmn WR PMC PMCmn WR PM PMmn WR PORT Output latch (Pmn) RD Input signal of alternate-function 2 Notes 1. Refer to ...

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Figure 4-26. Block Diagram of Type PFmn WR PMC PMCmn WR PM PMmn Output signal of WR PORT alternate-function 1 Output latch (Pmn) Address RD alternate-function 1 Note There are no hysteresis characteristics in the port mode. ...

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Port Register Setting When Alternate Function Is Used Table 4-14 shows the port register settings when each port is used for an alternate function. When using a port pin as an alternate-function pin, refer to description of each pin. ...

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Table 4-14. Settings When Port Pins Are Used for Alternate Functions (1/4) Pin Name Alternate Function Pnx Bit of Pn Register Function Name I/O P00 TOH0 Output P00 = Setting not required P01 TOH1 Output P01 = Setting not required ...

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Table 4-14. Settings When Port Pins Are Used for Alternate Functions (2/4) Pin Name Alternate Function Pnx Bit of Pn Register Function Name I/O P50 TI011 Input P50 = Setting not required RTP00 Output P50 = Setting not required KR0 ...

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Table 4-14. Settings When Port Pins Are Used for Alternate Functions (3/4) Pin Name Alternate Function Pnx Bit of Pn Register Function Name I/O P90 TXD1 Output P90 = Setting not required KR6 Input P90 = Setting not required P91 ...

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Table 4-14. Settings When Port Pins Are Used for Alternate Functions (4/4) Pin Name Alternate Function Pnx Bit of Pn Register Function Name I/O PDL0 AD0 I/O PDL0 = Setting not required PDL1 AD1 I/O PDL1 = Setting not required ...

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Cautions 4.6.1 Cautions on bit manipulation instruction for port n register (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port ...

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Hysteresis characteristics In port mode, the following ports do not have hysteresis characteristics. P02 to P06 P31 to P35, P38, P39 P40, P42 P97, P99, P913 to P915 150 CHAPTER 4 PORT FUNCTIONS User’s Manual U16891EJ2V0UD ...

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CHAPTER 5 BUS CONTROL FUNCTION The V850ES/KF1 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. 5.1 Features 16-bit data bus Multiplex bus output with a minimum ...

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Bus Control Pins The pins used to connect an external device are listed in the table below. Bus Control Pin Alternate-Function Pin AD0 to AD15 PDL0 to PDL15 WAIT PCM0 CLKOUT PCM1 CS0, CS1 PCS0, PCS1 WR0, WR1 PCT0, ...

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Memory Block Function The 64 MB memory space is divided into chip select areas of (lower and 64 KB. The programmable wait function and bus cycle operation mode for each of these chip select areas can be ...

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Chip select control function Of the 64 MB (linear) address space, two 64 KB spaces (0100000H to 010FFFFH/0200000H to 020FFFFH) include two chip select control functions, CS0 and CS1. The areas that can be selected by CS0 and CS1 ...

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Bus Access 5.4.1 Number of clocks for access The following table shows the number of base clocks required for accessing each resource. Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Notes ...

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Access by bus size The V850ES/KF1 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 ...

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CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) Address Byte data External data bus (b) 8-bit data bus width <1> ...

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Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) Address Halfword External data data bus (b) 8-bit data bus width ...

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CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Address ...

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Access to address ( First access Address Word data External data bus <4> ...

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CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address ...

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Access to address ( First access Second access Address Word ...

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Wait Function 5.5.1 Programmable wait function (1) Data wait control register 0 (DWC0) To realize interfacing with a low-speed memory or I/ seven data wait states can be inserted in the bus cycle that is executed for ...

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External wait function To synchronize an extremely slow memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). Access to each area of the internal ...

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Programmable address wait function Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register. Address wait insertion is set for each chip select area (CS0 and CS1 address ...

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Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by CSn. By inserting idle states, the ...

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Bus Hold Function 5.7.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to their alternate functions. When the HLDRQ pin is asserted (low level), indicating that another bus master has ...

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Bus hold procedure The bus hold status transition procedure is shown below. <1> Low-level input to HLDRQ pin acknowledged <2> All bus cycle start requests inhibited <3> End of current bus cycle <4> Shift to bus idle status. <5> ...

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Bus Priority Bus hold, instruction fetch (branch), instruction fetch (successive), and operand data access are executed in the external bus cycle. Bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). ...

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Bus Timing Figure 5-4. Read Timing (Bus Size: 16 Bits, 16-bit Access CLKOUT ASTB CS1, CS0 WAIT A1 D1 AD15 to AD0 RD 8-bit access AD15 to AD8 AD7 to AD0 Remark The broken lines indicate ...

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Figure 5-6. Write Timing (Bus Size: 16 Bits, 16-bit Access CLKOUT ASTB CS1, CS0 WAIT A1 D1 AD15 to AD0 11 00 WR1, WR0 8-bit access AD15 to AD8 AD7 to AD0 WR1, WR0 Figure 5-7. Write Timing ...

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Figure 5-8. Bus Hold Timing (Bus Size: 16 Bits, 16-bit Access CLKOUT HLDRQ HLDAK A1 D1 AD15 to AD0 ASTB RD CS1, CS0 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1. ...

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Cautions With the external bus function, signals may not be output at the correct timing under the following conditions. <Operating conditions> • CLKOUT asynchronous (2.7 V ≤ V When 1/ < CPU <Countermeasure> When used under ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.1 Overview The following clock generation functions are available. Main clock oscillator <In PLL (×4) mode> • MHz: 4.5 V ≤ MHz ( ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.2 Configuration FRC bit XT1 f Subclock XT oscillator XT2 MCK MFRC PLLON bit bit bit X1 f Main clock X PLL oscillator X2 Main clock oscillator stop control STOP mode SELPLL bit IDLE mode ...

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CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main clock oscillator oscillates the following frequencies (f • MHz (REGC = • MHz (REGC = V ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.3 Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (refer to 3.4.7 Special registers). This register ...

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CHAPTER 6 CLOCK GENERATION FUNCTION CK3 CK2 × 1 Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT ...

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CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read ...

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CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3> CK3 ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.4 Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and Operation Status CLS bit = 0, MCK bit ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.5 PLL Function 6.5.1 Overview The PLL function is used to output the operating clock of the CPU and on-chip peripheral function at a frequency 4 times higher than the oscillation frequency, and select the ...

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CHAPTER 6 CLOCK GENERATION FUNCTION 6.5.3 Usage (1) When PLL is used • After reset has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP 16-bit timer/event counter. The following products of the V850ES/KF1 have TMP0. μ PD703211, 703211Y, 70F3211H, 70F3211HY 7.1 Overview An outline of TMP0 is shown below. • Clock selection: ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.3 Configuration TMP0 includes the following hardware. Item Timer register 16-bit counter Registers TMP0 capture/compare registers 0, 1 (TP0CCR0, TP0CCR1) TMP0 counter read buffer register (TP0CNT) CCR0, CCR1 buffer registers Timer inputs 2 ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TP0CNT register. When the TP0CTL0.TP0CE bit = 0, ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.4 Registers (1) TMP0 control register 0 (TP0CTL0) The TP0CTL0 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) TMP0 control register 1 (TP0CTL1) The TP0CTL1 register is an 8-bit register that controls the operation of TMP0. This register can be read or written in 8-bit or 1-bit units. Reset sets ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMP0 I/O control register 0 (TP0IOC0) The TP0IOC0 register is an 8-bit register that controls the timer output (TOP00, TOP01 pins). This register can be read or written in 8-bit or 1-bit ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMP0 I/O control register 1 (TP0IOC1) The TP0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIP00, TIP01 pins). This register can be read ...

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TMP0 I/O control register 2 (TP0IOC2) The TP0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIP00 pin) and external trigger input signal (TIP00 pin). This register can be read ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMP0 option register 0 (TP0OPT0) The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMP0 capture/compare register 0 (TP0CCR0) The TP0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR0 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR0 register is transferred to the CCR0 buffer register. When ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMP0 capture/compare register 1 (TP0CCR1) The TP0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TP0CCR1 register can be rewritten even when the TP0CTL0.TP0CE bit = 1. The set value of the TP0CCR1 register is transferred to the CCR1 buffer register. When ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMP0 counter read buffer register (TP0CNT) The TP0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TP0CTL0.TP0CE ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5 Operation TMP0 can perform the following operations. TP0CTL1.TP0EST Bit Operation Interval timer mode Note 1 External event count mode Note 2 External trigger pulse output mode Note 2 One-shot pulse output mode ...

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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TP0MD2 to TP0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTP0CC0) is generated at the specified interval if the TP0CTL0.TP0CE bit is set to ...

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When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin ...

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