PM7364-BI PMC-Sierra Inc, PM7364-BI Datasheet
PM7364-BI
Specifications of PM7364-BI
Related parts for PM7364-BI
PM7364-BI Summary of contents
Page 1
... RELEASED DATA SHEET PMC-1960758 FRAME ENGINE AND DATALINK PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM™ 32 MANAGER DATA SHEET ISSUE 7: JANUARY 2006 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER ...
Page 2
... Patent information added to legal footer. Document re-issue. Document re-issue. Document re-formatted. Pin Diagram page replaced. Two entries added to Pin table diagram. Added AC, DC Timing section and 256 BGA mechanical package information. Creation of Data Sheet PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER i ...
Page 3
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 LINE INTERFACE..........................................................34 PRIORITY ENCODER ...................................................34 CHANNEL ASSIGNER...................................................34 LOOPBACK CONTROLLER..........................................35 HDLC PROCESSOR .....................................................35 PARTIAL PACKET BUFFER PROCESSOR ..................36 DATA STRUCTURES.....................................................38 DMA TRANSACTION CONTROLLER ...........................48 WRITE DATA PIPELINE/MUX .......................................48 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER ii ...
Page 4
... ERROR / BUS CONTROL .............................................55 DATA STRUCTURES.....................................................56 TASK PRIORITIES ........................................................68 DMA TRANSACTION CONTROLLER ...........................68 READ DATA PIPELINE ..................................................68 DESCRIPTOR INFORMATION CACHE ........................68 FREE QUEUE CACHE ..................................................68 TRANSMIT HDLC PROCESSOR ..................................69 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR70 LINE INTERFACE..........................................................73 PRIORITY ENCODER ...................................................73 CHANNEL ASSIGNER...................................................74 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER iii ...
Page 5
... D.C. CHARACTERISTICS....................................................................302 17 FREEDM-32 TIMING CHARACTERISTICS .........................................304 18 ORDERING AND THERMAL INFORMATION.......................................310 19 MECHANICAL INFORMATION............................................................. 311 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 IDENTIFICATION REGISTER .....................................265 BOUNDARY SCAN REGISTER ..................................265 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER iv ...
Page 6
... REGISTER 0X200 : RHDL INDIRECT CHANNEL SELECT............................127 REGISTER 0X204 : RHDL INDIRECT CHANNEL DATA REGISTER #1.........129 REGISTER 0X208 : RHDL INDIRECT CHANNEL DATA REGISTER #2.........132 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER v ...
Page 7
... REGISTER 0X2B4 : RMAC PACKET DESCRIPTOR REFERENCE SMALL BUFFER FREE QUEUE END...............................................................168 REGISTER 0X2B8 : RMAC PACKET DESCRIPTOR REFERENCE READY QUEUE START.....................................................................................170 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER vi ...
Page 8
... REGISTER 0X334 : TMAC DESCRIPTOR REFERENCE READY QUEUE END ..............................................................................................................203 REGISTER 0X380 : THDL INDIRECT CHANNEL SELECT ............................205 REGISTER 0X384 : THDL INDIRECT CHANNEL DATA #1 ............................207 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER vii ...
Page 9
... REGISTER 0X08 : REVISION IDENTIFIER/CLASS CODE ............................258 REGISTER 0X0C : CACHE LINE SIZE/LATENCY TIMER/HEADER TYPE....259 REGISTER 0X10 : CBI MEMORY BASE ADDRESS REGISTER ...................260 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER viii ...
Page 10
... RELEASED DATA SHEET PMC-1960758 REGISTER 0X3C : INTERRUPT LINE / INTERRUPT PIN / MIN_GNT / MAX_LAT..............................................................................................262 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER ix ...
Page 11
... FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS ..............................................................................................................279 FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ......................................281 FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE ........................283 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER x ...
Page 12
... FIGURE 42 – PCI INTERFACE TIMING..........................................................308 FIGURE 43 – JTAG PORT INTERFACE TIMING ............................................309 FIGURE 44 – 256 PIN ENHANCED BALL GRID ARRAY (SBGA)................... 311 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER xi ...
Page 13
... TABLE 18 – RPQ_LFN[1:0] SETTINGS ..........................................................145 TABLE 19 – RPQ_SFN[1:0] SETTINGS..........................................................145 TABLE 20 – TDQ_RDYN[2:0] SETTINGS .......................................................179 TABLE 21 – TDQ_FRN[1:0] SETTINGS..........................................................180 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER xii ...
Page 14
... TABLE 35 – JTAG PORT INTERFACE (FIGURE 43) ......................................308 TABLE 36 – FREEDM 32 ORDERING INFORMATION ..................................310 TABLE 37 – FREEDM 32 THERMAL INFORMATION.....................................310 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER xiii ...
Page 15
... CRC-CCITT and CRC-32 frame check sequences. The transmitter also aborts packets under the direction of the host or automatically when the channel underflows. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 1 ...
Page 16
... Supports 3.3 and 5 Volt PCI signaling environments. • Low power CMOS technology. • 256 pin enhanced ball grid array (SBGA) package ( mm). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 2 ...
Page 17
... FUNI or Frame Relay service inter-working interfaces for ATM switches and multiplexors. • D-channel processing in ISDN terminals and switches. • Internet/Intranet access equipment. • Packet-based DSLAM equipment. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 3 ...
Page 18
... RFC-1662 - "PPP in HDLC-like Framing" Internet Engineering Task Force, July 1994. 3. PCI Special Interest Group, PCI Local Bus Specification, June 1, 1995, Version 2.1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 4 ...
Page 19
... ATM CELL BASED UPLINK SIDE PM7364 FREEDM-32 SAR PCI Bus Packet Micro- Memory processor PM7322 RCMP Processor Module PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER HDLC BASED UPLINK SIDE HSSI HSSI Module DS3/E3 Framer LIU DS3/E3/J2 HDLC Based Uplink Module ...
Page 20
... RELEASED DATA SHEET PMC-1960758 5 BLOCK DIAGRAM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 6 ...
Page 21
... RELEASED DATA SHEET PMC-1960758 . RSTB RBCLK RBD PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER PMCTEST TDO TDI TCK TMS TRSTB TBCLK TBD 7 ...
Page 22
... DATA SHEET PMC-1960758 6 DESCRIPTION The PM7364 FREEDM-32 Frame Engine and Datalink Manager device is a monolithic integrated circuit that implements HDLC processing, and PCI Bus memory management functions for a maximum of 128 bi-directional channels. For channelised links, the FREEDM-32 allows up to 128 bi-directional HDLC channels to be assigned to individual time-slots within a maximum of 32 independently timed links ...
Page 23
... The FREEDM-32 is implemented in low power CMOS technology. It has TTL compatible inputs and outputs and is packaged in a 256 pin enhanced ball grid array (SBGA) package. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 9 ...
Page 24
... TCLK[25] TD[28] TD[30] TD[18] TD[20] TD[22] TCLK[23] TD[25] TD[27] TCLK[28] TCLK[30] TD[19] TCLK[20] TCLK[22] TD[23] TCLK[24] TCLK[26] TCLK[27] TCLK[29] TCLK[31] VSS VSS TD[24] TD[26] VSS PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER RD[27] RD[29] VSS VSS VSS B RD[24] RD[26] RCLK[27] RCLK[29] VDD VDD VSS RD[25] RCLK[26] RCLK[28] PCICLK VDD ...
Page 25
... B8 format payload (i.e. not part of the HDLC A7 packet). RCLK[2:0] is nominally a 50% duty D8 cycle clock between 0 and 52 MHz. A6 RCLK[31:3] is nominally a 50% duty cycle C6 clock between 0 and 10 MHz PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 11 ...
Page 26
... RBD reports the data on the selected one of the receive data signals (RD[31:0]) and is updated on the falling edge of RBCLK. RBD may be tri-stated by setting the RBEN bit in the FREEDM-32 Master BERT Control register low. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 12 ...
Page 27
... TCLK[31:3] is nominally a 50% duty cycle W10 clock between 0 and 10 MHz. TCLK[2:0] is U10 nominally a 50% duty cycle clock between 0 W9 and 52 MHz. Typical values for TCLK[31:0] W8 include 1.544 MHz (for T1 links) and 2.048 V8 MHz (for E1 links PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 13 ...
Page 28
... When the TBERTEN bit in the BERT Control register is set high, the data on TBD is transmitted on the selected one of the transmit data signals (TD[31:0]). TBD is sampled on the rising edge of TBCLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 14 ...
Page 29
... TBCLK is a buffered version of the selected one of the transmit clock signals (TCLK[31:0]). TBCLK may be tri-stated by setting the TBEN bit in the FREEDM-32 Master BERT Control register low. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 15 ...
Page 30
... For write transactions, AD[31:0] F2 remains an input bus during the data phases of F3 the transaction. For read transactions, AD[31: output bus during the data phases When the FREEDM-32 is not involved in the E3 current transaction, AD[31:0] is tri-stated. D1 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 16 ...
Page 31
... When the FREEDM-32 is the target, C/BEB[3: input bus. When the FREEDM-32 is not involved in the current transaction, C/BEB[3:0] is tri-stated output bus, C/BEB[3:0] is updated on the rising edge of PCICLK input bus, C/BEB[3:0] is sampled on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 17 ...
Page 32
... When the FREEDM-32 is the target, FRAMEB is an input. When the FREEDM-32 is not involved in the current transaction, FRAMEB is tri-stated output signal, FRAMEB is updated on the rising edge of PCICLK input signal, FRAMEB is sampled on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 18 ...
Page 33
... PCICLK cycles. When the FREEDM-32 is not involved in the current transaction, TRDYB is tri-stated output signal, TRDYB is updated on the rising edge of PCICLK input signal, TRDYB is sampled on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 19 ...
Page 34
... When the FREEDM-32 is the target, IRDYB is an input. When the FREEDM-32 is not involved in the current transaction, IRDYB is tri-stated. IRDYB is updated on the rising edge of PCICLK or sampled on the rising edge of PCICLK depending on whether output or an input. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 20 ...
Page 35
... C/BEB[3:0] code indicates a register read or write, the FREEDM-32 performs a PCI configuration register transaction and asserts the DEVSELB signal in the next PCICLK period. IDSEL is sampled on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 21 ...
Page 36
... The FREEDM-32 will continue to reject other initiators until its owner releases the lock by forcing both FRAMEB and LOCKB high initiator, the FREEDM-32 will never lock a target. LOCKB is sampled using the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 22 ...
Page 37
... The FREEDM-32 may be enabled to report many alarms or events via interrupts. PCIINTB returns high when the interrupt is acknowledged via an appropriate register access. PCIINTB is an open drain output and is updated on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 23 ...
Page 38
... Configuration registers space. Regardless of the setting of SERREN, parity errors are always reported by the SERR bit in the Control/Status register in the PCI Configuration registers space. SERRB is an open drain output and is updated on the rising edge of PCICLK. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 24 ...
Page 39
... K19 The test data input signal (TDI) carries test data into the FREEDM-32 via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 25 ...
Page 40
... PCI Host Interface Signals to operate in the 5V PCI signalling environment when set high and the 3.3V PCI signalling environment when set low. EN5V is an asynchronous input with an integral pull up resistor. U17 This pin must be left unconnected. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 26 ...
Page 41
... FREEDM-32 register write accesses during production test (PMCTEST set high). The contents of the test data bus (TDAT[15:0]) are clocked into the addressed register on the rising edge of TWRB. TWRB replaces RD[23] when PMCTEST is set high. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 27 ...
Page 42
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Pin Function No. The bi-directional test mode data bus (TDAT[15:0]) carries data read from or written to FREEDM-32 registers during production test. TDAT[15:0] replace TD[31:16] when PMCTEST is set high. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 28 ...
Page 43
... ISSUE 7 Pin Function No. B2 The DC power pins should be connected well decoupled +3 supply. B18 B19 C2 C3 C18 C19 D7 D10 D14 G4 G17 K17 L4 P4 P17 U7 U11 U14 V2 V3 V18 V19 W2 W3 W18 W19 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 29 ...
Page 44
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Pin Function No. A1 The DC ground pins should be connected to A2 ground A10 A13 A18 A19 A20 B1 B20 C1 C20 H1 J20 K20 L1 M1 N20 V1 V20 W1 W20 Y11 Y12 Y18 Y19 Y20 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 30 ...
Page 45
... Inputs TMS, TDI, TRSTB and EN5V are Schmitt triggered and have internal pull-up resistors. 5. Inputs RD[31:0], RCLK[31:0], TCLK[31:0], SYSCLK, PCICLK, TBD, RSTB, GNTB, IDSEL, LOCKB, TCK and PMCTEST are Schmitt triggered. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 31 ...
Page 46
... The first FCS bit received is the residue of the highest term. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 FCS HDLC Packet PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Flag Flag 2 n +… The 2 n ...
Page 47
... Transmit data of that channel is substituted in its place. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE Parity Check Digits PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER g n-1 Message D n-1 MSB 33 ...
Page 48
... RAM word include the channel number and a time-slot enable flag. The time-slot enable flag labels the current time-slot as belonging to the channel indicted by the channel number field. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 34 ...
Page 49
... The HDLC processor is a time-slice state machine which can process up to 128 independent channels. The state vector and provisioning information for each PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 35 ...
Page 50
... HDLC processor in the channel FIFO with an over-run flag and ignores the rest of the packet. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 36 ...
Page 51
... RMAC until the channel transfer size is reached or an end of packet is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Block 0 Block 1 Block 2 Block 3 Block 200 Block 511 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Block Pointer RAM XX 0x03 XX 0xC8 0x01 ...
Page 52
... For packet data, the RMAC communicates with the host using Receive Packet Descriptors (RPD), Receive Packet Descriptor References (RPDR), the Receive PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 38 ...
Page 53
... Description The Data Buffer Start Address[31:0] bits point to the data buffer in host memory. This field is expected to be configured by the Host during initialisation. The Data Buffer Start Address field is valid in all RPDs. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 0 CE RCC [6:0] ...
Page 54
... For a linked list of RPDs, only the last RPD's Status field is valid. All other RPD Status fields of the linked list are invalid and should be ignored. When a packet requires only one RPD, the Status field is valid. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 40 ...
Page 55
... RPD's data buffer. This field is expected to be configured by the Host during initialisation. The Receive Buffer Size must be a non-zero integer multiple of four and less than or equal to 32764. The Receive Buffer Size field is valid in all RPDs. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 41 ...
Page 56
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Bit 31 RPDTB[31:4] + RPDR[13:0] = RPD_ADDR[31:0] Bit 31 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 0000 0000 Bit 0 Dword 0 Dword 1 Dword 2 Dword 3 ...
Page 57
... A queue is full when the read index is equal to the write index. Figure 6 shows the RPDR reference queues. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 43 ...
Page 58
... RPDRSFQE[15:0] = RPDR Small Free Queue End register Base Address + Index Register ------------------------- Host Address Bit 0 RQB RPDR RPDR RPDR RPDR RPDR RPDR RPDR RPDR RPDR RPDR RPDR RPDR PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER RQB[31: Index[15:0] 00 AD[31:0] Host Memory 256KB RPD Reference Queues Valid RPDR 44 ...
Page 59
... RPDs are linked to the first RPD as shown in Figure 7. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 RPDR[13: Successful reception of packet Unsuccessful reception of packet Unprovisioned partial packet Reserved. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 45 ...
Page 60
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Bit 31 Bit 0 RPD - 16 bytes STATUS + RPDR STATUS + RPDR RPD - 16 bytes STATUS + RPDR RPD - 16 bytes RPD - 16 bytes RPD - 16 bytes PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER buffer -packet M buffer -packet N buffer -start of packet O buffer -middle of packet O ...
Page 61
... This field contains the pointer to the current RPD. This field contains the size in bytes of the buffer currently being written to. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 RPD Pointer[13:0] Start RPD Pointer[13:0] ...
Page 62
... This field contains the pointer to the first RPD for the packet being received. The DMA Current Address [31:0] bits holds the host address of the next dword in the current buffer. The RMAC increments this field on each access to the buffer. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 48 ...
Page 63
... PCI bus. The internal microprocessor bus interface block contains configuration and status registers together with the production test logic for the GPIC block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 49 ...
Page 64
... FIFO with data before the GPIC requires it. (If a write transaction is terminated early due to data starvation, the GPIC will automatically PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 50 ...
Page 65
... GPIC will discard the REQUEST and indicate to the local master that the cycle is complete. This action will result in any write data being lost and any read data being erroneous. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 51 ...
Page 66
... GPIC need not be dword aligned with the data presented on the PCI bus. The GPIC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 52 ...
Page 67
... The FREEDM will also disconnect on every read and write access to configuration space after transferring one Dword of data. Figure 9 illustrates the GPIC address space. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 53 ...
Page 68
... The GPIC will perform a Target-Abort termination only in the case of an address parity error in an address that the GPIC claims. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PCI ADDRESS MAP 0B CBI Registers 4GB PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 4KB 54 ...
Page 69
... The descriptor contains the size and location of buffers in host memory and the packet status information associated with the data in each buffer. TDs are PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 55 ...
Page 70
... TMAC Next TD Pointer [13:0] Reserved (16) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Data Buffer Start Address [31:0] Reserved (5) P ABT IOC Transmit Buffer Size [15:0] PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit TCC[6:0] Host Next TD Pointer [13:0] 56 ...
Page 71
... set to logic 0, this TD either describes the entire packet (in the single TD packet case) or describes the end of a packet (in the multiple TD packet case). Note: When M is set to logic 1, the only valid value for CE is logic 0. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 57 ...
Page 72
... When ABT is set to logic 1, the packet will be aborted after all the data in the buffer has been transmitted. If ABT is set to logic 1 in the current TD, the M bit must be set low and the CE bit must be set to high.. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 58 ...
Page 73
... TMAC. The Transmit Buffer Size[15:0] field is used to indicate the size in bytes of the current TD's data buffer. (N.B. The TMAC does not make use of this field.) PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 59 ...
Page 74
... ISSUE 7 TDTB[31: Descriptor Table Base register TDR[13:0] = Transmit Descriptor Reference TD_ADDR[31:0] = Transmit Descriptor Address Bit 31 TDTB[31:4] + TDR[13:0] = TD_ADDR[31:0] Bit 31 TD1 TD2 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 0000 0000 Bit 0 Dword 0 Dword 1 Dword 2 Dword 3 Dword 0 Dword 3 Dword 0 Dword 3 ...
Page 75
... An end pointer must not be set to 0 hex in an attempt to include offset 3FFFC hex in a queue. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 61 ...
Page 76
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Base Address + Index Register ------------------------- PCI Address Bit 0 TQB TDR TDR TDR TDR TDR TDR PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER TQB[31: Index[15:0] 00 AD[31:0] PCI Host Memory 256KB TDR Reference Queues Valid TDR. Only least significant 17 bits are valid. ...
Page 77
... Last or only buffer of packet, buffer read. Buffer of partial packet, buffer read. Unprovisioned channel, buffer not read. Malformed packet (e.g. Bytes In Buffer field set to 0), buffer not read. Description No underflow detected. Underflow detected. PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 63 ...
Page 78
... Last TD Pointer [13:0] A Bytes to Tx [15:0] Abrt IOC DMA Current Address [31:0] Last Reserved PiP PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Bit 0 D Current TD Pointer [13:0] Host TD Pointer [13:0] V Next TD Pointer [13:0] D Current TD Pointer [13:0] Host TD Pointer [13:0] V Next TD Pointer [13:0] D Current TD Pointer [13:0] Host TD Pointer [13:0] V Next TD Pointer [13:0] ...
Page 79
... Indicates that a underflow has occurred on this channel. This bit is set in response to an underflow indication for the downstream THDL block and is cleared when a TDR is written to the TDR Free Queue (or to the free queue cache). PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 65 ...
Page 80
... TD pointer fields are valid. If the V bit is set to logic 0, the list is either empty or contains only one host-linked chain and the next and last TD pointer fields are invalid read. (See Figure 14) PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 66 ...
Page 81
... V bit to logic 1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE V=1 TMAC Link V=1 M=1 M=1 CE=0 CE=0 Data Host Link M=1 M=0 CE=0 CE=1 Data P1 M=0 CE=0 Data P2 M=0 CE=1 Data PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER TD P4 TMAC Link V=0 M=0 CE=1 Data Data 67 ...
Page 82
... The Free Queue Cache block implements the 6 element TDR Free Queue cache. Caching TDRs reduces the number of host bus accesses that the TMAC makes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 68 ...
Page 83
... When an indirect operation is performed, the information is accessed from RAM during a null clock cycle inserted by the TCAS block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 69 ...
Page 84
... HDLC processor when the HDLC processor requests it buffer under-run occurs for a channel, the reader informs the HDLC processor and purges the rest of the packet. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 70 ...
Page 85
... FIFOs. When the reader signals that a block has been read, the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Block 0 Block 1 Block 2 Block 3 Block 200 Block 511 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER Block Pointer RAM XX 0x03 XX 0xC8 0x01 ...
Page 86
... With knowledge of the transmit link PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 72 ...
Page 87
... SYSCLK timing domain. Requests are serviced on a fixed priority scheme where highest to lowest priority is assigned from line interface TD[0] to line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 73 ...
Page 88
... The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The FREEDM-32 identification code is 173640CD hexadecimal. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 74 ...
Page 89
... GPIC Control 0x044 - 0x07C GPIC Reserved 0x080 - 0x0FC Reserved 0x100 RCAS Indirect Channel and Time-slot Select 0x104 RCAS Indirect Channel Data PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 75 ...
Page 90
... RMAC Packet Descriptor Reference Large Buffer Free Queue Write 0x2A0 RMAC Packet Descriptor Reference Large Buffer Free Queue Read PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 76 ...
Page 91
... TMAC Descriptor Reference Ready Queue Write 0x330 TMAC Descriptor Reference Ready Queue Read 0x334 TMAC Descriptor Reference Ready Queue End 0x338 - 0x37C TMAC Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 77 ...
Page 92
... PMON Receive FIFO Overflow Count 0x508 PMON Transmit FIFO Underflow Count 0x50C PMON Configurable Count #1 0x510 PMON Configurable Count #2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 78 ...
Page 93
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Register Vendor Identification/Device Identification Command/Status Revision Identifier/Class Code Cache Line Size/Latency Timer/Header Type/BIST CBI Memory Base Address Register Unused Base Address Register Reserved Reserved Reserved Reserved Reserved Interrupt Line/Interrupt Pin/MIN_GNT/MAX_LAT PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 79 ...
Page 94
... Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all four byte enables are negated, no access is made to the register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 80 ...
Page 95
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Reset 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 81 ...
Page 96
... PCI pins tri-state. Transmit link data pins (TD[31:0]) are forced high. In addition, all registers except the GPIC PCI Configuration registers, are reset to their default values. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 82 ...
Page 97
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TFUDRE 0 IOCE 0 TDFQEE 0 TDQRDYE 0 TDQFE 0 RPDRQEE 0 RPDFQEE 0 RPQRDYE 0 RPQLFE 0 RPQSFE 0 RFOVRE 0 RPFEE 0 RABRTE 0 RFCSEE 0 PERRE 0 SERRE 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 83 ...
Page 98
... PCIINTB output. Interrupts are masked when RPFEE is set low. However, the RPFEI bit remains valid when PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 84 ...
Page 99
... However, the RPQRDYI bit remains valid when interrupts are disabled and may be polled to detect RPDR ready queue write events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 85 ...
Page 100
... PCIINTB output. Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 86 ...
Page 101
... TFUDRE is set low. However, the TFUDRI bit remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 87 ...
Page 102
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TFUDRI X IOCI X TDFQEI X TDQRDYI X TDQFI X RPDRQEI X RPDFQEI X RPQRDYI X RPQLFI X RPQSFI X RFOVRI X RPFEI X RABRTI X RFCSEI X PERRI X SERRI X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 88 ...
Page 103
... FIFO overrun error interrupts to the PCI host. RFOVRI is set high on attempts to write data into the logical FIFO of a channel when it is already full. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 89 ...
Page 104
... RPDRQEI remains valid when interrupts are disabled and may be polled to detect RPDR ready queue full error events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 90 ...
Page 105
... FIFO when it is already empty. TFUDRI remains valid when interrupts are disabled and may be polled to detect transmit FIFO underflow events. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 91 ...
Page 106
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TBDA X SYSCLKA X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 92 ...
Page 107
... The transmit BERT data active bit (TBDA) monitors for low to high transitions on the TBD input. TBDA is set high on a rising edge of TDB, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 93 ...
Page 108
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TLGA[7] X TLGA[6] X TLGA[5] X TLGA[4] X TLGA[3] X TLGA[2] X TLGA[1] X TLGA[0] X RLGA[7] X RLGA[6] X RLGA[5] X RLGA[4] X RLGA[3] X RLGA[2] X RLGA[1] X RLGA[0] X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 94 ...
Page 109
... RLGA[6]: The receive link group #6 active bit (RLGA[6]) monitors for transitions on the RD[27:24] and RCLK[27:24] inputs. RLGA[6] is set high when each of PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 95 ...
Page 110
... The transmit link group #5 active bit (TLGA[5]) monitors for low to high transitions on the TCLK[23:20] inputs. TLGA[5] is set high when rising edges PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 96 ...
Page 111
... TCLK[31:28] inputs. TLGA[7] is set high when rising edges have been observed on all the signals on the TCLK[31:28] inputs, and is set low when this register is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 97 ...
Page 112
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH LLBEN[15] 0 LLBEN[14] 0 LLBEN[13] 0 LLBEN[12] 0 LLBEN[11] 0 LLBEN[10] 0 LLBEN[9] 0 LLBEN[8] 0 LLBEN[7] 0 LLBEN[6] 0 LLBEN[5] 0 LLBEN[4] 0 LLBEN[3] 0 LLBEN[2] 0 LLBEN[1] 0 LLBEN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 98 ...
Page 113
... When LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 99 ...
Page 114
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH LLBEN[31] 0 LLBEN[30] 0 LLBEN[29] 0 LLBEN[28] 0 LLBEN[27] 0 LLBEN[26] 0 LLBEN[25] 0 LLBEN[24] 0 LLBEN[23] 0 LLBEN[22] 0 LLBEN[21] 0 LLBEN[20] 0 LLBEN[19] 0 LLBEN[18] 0 LLBEN[17] 0 LLBEN[16] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 100 ...
Page 115
... When LLBEN[n] is set high, the data on RD[n] is passed verbatim to TD[n] which is then updated on the falling edge of RCLK[n]. TCLK[n] is ignored. When LLBEN[n] is set low, TD[n] is processed normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 101 ...
Page 116
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TBEN 0 Unused X Unused X TBSEL[4] 0 TBSEL[3] 0 TBSEL[2] 0 TBSEL[1] 0 TBSEL[0] 0 RBEN 0 Unused X Unused X RBSEL[4] 0 RBSEL[3] 0 RBSEL[2] 0 RBSEL[1] 0 RBSEL[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 102 ...
Page 117
... TBCLK. When TBEN is set low, all transmit links are processed normally and TBCLK is held tri-stated. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 103 ...
Page 118
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X TP2EN 0 TABRT2EN 0 RP2EN 0 RLENE2EN 0 RABRT2EN 0 RFCSE2EN 0 RSPE2EN 0 Unused X TP1EN 0 TABRT1EN 0 RP1EN 0 RLENE1EN 0 RABRT1EN 0 RFCSE1EN 0 RSPE1EN 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 104 ...
Page 119
... HDLC abort events. When TABRT1EN is set high, insertion of an abort in the outgoing stream will cause the PMON Configurable Accumulator PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 105 ...
Page 120
... PMON Configurable Accumulator #2 register to increment. Receive packet length errors are ignored when RLENE2EN is set low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 106 ...
Page 121
... When TP2EN is set high, transmission of an error-free packet will cause the PMON Configurable Accumulator #2 register to increment. Transmit error-free packets are ignored when TP2EN is set low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 107 ...
Page 122
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X RPWTH[4] 0 RPWTH[3] 0 RPWTH[2] 0 RPWTH[1] 0 RPWTH[0] 0 Unused X Unused X Unused X Unused X PONS_E 0 SOE_E 0 LENDIAN 1 Reserved 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 108 ...
Page 123
... BYTE n-4 BYTE n-3 Bit BYTE 3 BYTE 2 BYTE 7 BYTE 6 • • • • • • BYTE n-1 BYTE n-2 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER BYTE 2 BYTE 3 BYTE 6 BYTE 7 • • • • • • BYTE n-2 BYTE n ...
Page 124
... GPIC will begin requesting access to the PCI bus when the number of dwords of packet data loaded by the RMAC reaches the threshold specified by RPWTH[4:0]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 110 ...
Page 125
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH BUSY X RWB 0 Unused X LINK[4] 0 LINK[3] 0 LINK[2] 0 LINK[1] 0 LINK[0] 0 Unused X Unused X Unused X TSLOT[4] 0 TSLOT[3] 0 TSLOT[2] 0 TSLOT[1] 0 TSLOT[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 111 ...
Page 126
... RCAS Indirect Channel Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 112 ...
Page 127
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X CDLBEN 0 PROV 0 Unused X CHAN[6] 0 CHAN[5] 0 CHAN[4] 0 CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 113 ...
Page 128
... CDLBEN reflects the value written until the completion of a subsequent indirect read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 114 ...
Page 129
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X FTHRES[6] 0 FTHRES[5] 1 FTHRES[4] 1 FTHRES[3] 1 FTHRES[2] 1 FTHRES[1] 1 FTHRES[0] 1 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 115 ...
Page 130
... The default value of this register is inconsistent with that of the TCAS Framing Bit Threshold register 0x408. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 116 ...
Page 131
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH CHDIS 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X DCHAN[6] 0 DCHAN[5] 0 DCHAN[4] 0 DCHAN[3] 0 DCHAN[2] 0 DCHAN[1] 0 DCHAN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 117 ...
Page 132
... DCHAN[6:0] is disabled. Data in timeslots associated with the specified channel is ignored. When CHDIS is set low, the channel specified by DCHAN[6:0] operates normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 118 ...
Page 133
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X BSYNC CEN 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 119 ...
Page 134
... When BSYNC is set low, gaps in RCLK[0] carry no special significance. BSYNC is ignore when CEN is set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 120 ...
Page 135
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X BSYNC CEN 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 121 ...
Page 136
... When BSYNC is set low, gaps in RCLK[n] carry no special significance. BSYNC is ignore when CEN is set high. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 122 ...
Page 137
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused CEN 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 123 ...
Page 138
... RCLK[3] after an extended quiescent period is considered to be the most significant bit of time-slot 1. Link data is present at time-slots ignored when CEN is set low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 124 ...
Page 139
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused CEN 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 125 ...
Page 140
... Link data is present at time-slots ignored when CEN is set low. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 126 ...
Page 141
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH BUSY X CRWB 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X CHAN[6] 0 CHAN[5] 0 CHAN[4] 0 CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 127 ...
Page 142
... RHDL Indirect Channel Data #1 and #2 registers or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 128 ...
Page 143
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH PROV 0 CRC[1] 0 CRC[0] 0 STRIP 0 DELIN 0 TAVAIL X Unused X FPTR[8] X FPTR[7] X FPTR[6] X FPTR[5] X FPTR[4] X FPTR[3] X FPTR[2] X FPTR[1] X FPTR[0] X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 129 ...
Page 144
... The value of STRIP is ignored when DELIN is low. STRIP reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 130 ...
Page 145
... CHAN[6:0]. PROV reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 CRC[0] Operation 0 No Verification 1 CRC-CCITT 0 CRC-32 1 Reserved PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 131 ...
Page 146
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH 7BIT 0 PRIORITY 0 INVERT 0 Unused X Unused X Unused X OFFSET[1] 0 OFFSET[0] 0 Unused X Unused X Unused X Unused[ X Unused X XFER[2] X XFER[1] 0 XFER[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 132 ...
Page 147
... RMAC block for transfer to the PCI host. The value of PRIORITY to be written to the channel provision RAM indirect channel write operation, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 133 ...
Page 148
... When 7BIT is set low, the entire receive data stream is processed. 7BIT reflects the value written until the completion of a subsequent indirect channel read operation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 134 ...
Page 149
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH BUSY X BRWB X Unused X Unused X Unused X Unused X Unused X BLOCK[8] X BLOCK[7] X BLOCK[6] X BLOCK[5] X BLOCK[4] X BLOCK[3] X BLOCK[2] X BLOCK[1] X BLOCK[0] X PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 135 ...
Page 150
... RHDL Indirect Block Data register or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 136 ...
Page 151
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X BPTR[8] 0 BPTR[7] 0 BPTR[6] 0 BPTR[5] 0 BPTR[4] 0 BPTR[3] 0 BPTR[2] 0 BPTR[1] 0 BPTR[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 137 ...
Page 152
... BPTR[8:0] reflects the value written until the completion of a subsequent indirect block read operation. When provisioning a channel FIFO, all blocks pointers must be re-written to properly initialize the FIFO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 138 ...
Page 153
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X LENCHK 0 TSTD 0 Unused X Unused X Unused X Unused X Unused X Reserved[2] 1 Reserved[1] 1 Reserved[0] 1 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 139 ...
Page 154
... MAX[15:0]. When LENCHK is set low, receive packets are not checked for maximum size and MAX[15:0] must be set to 'hFFFF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 140 ...
Page 155
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH MAX[15] 1 MAX[14] 1 MAX[13] 1 MAX[12] 1 MAX[11] 1 MAX[10] 1 MAX[9] 1 MAX[8] 1 MAX[7] 1 MAX[6] 1 MAX[5] 1 MAX[4] 1 MAX[3] 1 MAX[2] 1 MAX[1] 1 MAX[0] 1 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 141 ...
Page 156
... FCS fields, greater than MAX[15:0] bytes are aborted. When LENCHK is set low, aborts are not generated regardless of packet length and MAX[15:0] must be set to 'hFFFF. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 142 ...
Page 157
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X RPQ_SFN[1] 0 RPQ_SFN[0] 0 RPQ_LFN[1] 0 RPQ_LFN[0] 0 RPQ_RDYN[2] 0 RPQ_RDYN[1] 0 RPQ_RDYN[0] 0 RAWMAX[1] 1 RAWMAX[0] 1 SCACHE 1 LCACHE 1 ENABLE 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 143 ...
Page 158
... RPDR ready interrupt (RPQRDYI) is asserted, as follows: Table 17 – RPQ_RDYN[2:0] settings RPQ_RDYN[2:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE RPDRs 000 1 001 4 010 6 011 8 100 16 101 32 110 Reserved PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 144 ...
Page 159
... Table 19 – RPQ_SFN[1:0] Settings RPQ_SFN[1:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE RPDRs 111 Reserved No of Reads Reserved No of Reads Reserved PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 145 ...
Page 160
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH BUSY X RWB 0 Unused X Unused X Unused X Unused X Unused X Unused X PROV 1 CHAN[6] 0 CHAN[5] 0 CHAN[4] 0 CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 146 ...
Page 161
... This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 147 ...
Page 162
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDTB[15] 0 RPDTB[14] 0 RPDTB[13] 0 RPDTB[12] 0 RPDTB[11] 0 RPDTB[10] 0 RPDTB[9] 0 RPDTB[8] 0 RPDTB[7] 0 RPDTB[6] 0 RPDTB[5] 0 RPDTB[4] 0 RPDTB[3] 0 RPDTB[2] 0 RPDTB[1] 0 RPDTB[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 148 ...
Page 163
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDTB[31] 0 RPDTB[30] 0 RPDTB[29] 0 RPDTB[28] 0 RPDTB[27] 0 RPDTB[26] 0 RPDTB[25] 0 RPDTB[24] 0 RPDTB[23] 0 RPDTB[22] 0 RPDTB[21] 0 RPDTB[20] 0 RPDTB[19] 0 RPDTB[18] 0 RPDTB[17] 0 RPDTB[16] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 149 ...
Page 164
... Packet Descriptor Table Base (RPDTB[31:4]). The table must byte boundary and thus the least significant four bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 150 ...
Page 165
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RQB[15] 0 RQB[14] 0 RQB[13] 0 RQB[12] 0 RQB[11] 0 RQB[10] 0 RQB[9] 0 RQB[8] 0 RQB[7] 0 RQB[6] 0 RQB[5] 0 RQB[4] 0 RQB[3] 0 RQB[2] 0 RQB[1] 0 RQB[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 151 ...
Page 166
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RQB[31] 0 RQB[30] 0 RQB[29] 0 RQB[28] 0 RQB[27] 0 RQB[26] 0 RQB[25] 0 RQB[24] 0 RQB[23] 0 RQB[22] 0 RQB[21] 0 RQB[20] 0 RQB[19] 0 RQB[18] 0 RQB[17] 0 RQB[16] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 152 ...
Page 167
... The base address must be dword aligned and thus the least significant two bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 153 ...
Page 168
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRLFQS[15] 0 RPDRLFQS[14] 0 RPDRLFQS[13] 0 RPDRLFQS[12] 0 RPDRLFQS[11] 0 RPDRLFQS[10] 0 RPDRLFQS[9] 0 RPDRLFQS[8] 0 RPDRLFQS[7] 0 RPDRLFQS[6] 0 RPDRLFQS[5] 0 RPDRLFQS[4] 0 RPDRLFQS[3] 0 RPDRLFQS[2] 0 RPDRLFQS[1] 0 RPDRLFQS[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 154 ...
Page 169
... The physical start address of the RPDRLF queue is the sum of RPDRLFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 155 ...
Page 170
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRLFQW[15] 0 RPDRLFQW[14] 0 RPDRLFQW[13] 0 RPDRLFQW[12] 0 RPDRLFQW[11] 0 RPDRLFQW[10] 0 RPDRLFQW[9] 0 RPDRLFQW[8] 0 RPDRLFQW[7] 0 RPDRLFQW[6] 0 RPDRLFQW[5] 0 RPDRLFQW[4] 0 RPDRLFQW[3] 0 RPDRLFQW[2] 0 RPDRLFQW[1] 0 RPDRLFQW[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 156 ...
Page 171
... The physical write address in the RPDRLF queue is the sum of RPDRLFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 157 ...
Page 172
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRLFQR[15] 0 RPDRLFQR[14] 0 RPDRLFQR[13] 0 RPDRLFQR[12] 0 RPDRLFQR[11] 0 RPDRLFQR[10] 0 RPDRLFQR[9] 0 RPDRLFQR[8] 0 RPDRLFQR[7] 0 RPDRLFQR[6] 0 RPDRLFQR[5] 0 RPDRLFQR[4] 0 RPDRLFQR[3] 0 RPDRLFQR[2] 0 RPDRLFQR[1] 0 RPDRLFQR[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 158 ...
Page 173
... The physical read address in the RPDRLF queue is the sum of RPDRLFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 159 ...
Page 174
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRLFQE[15] 0 RPDRLFQE[14] 0 RPDRLFQE[13] 0 RPDRLFQE[12] 0 RPDRLFQE[11] 0 RPDRLFQE[10] 0 RPDRLFQE[9] 0 RPDRLFQE[8] 0 RPDRLFQE[7] 0 RPDRLFQE[6] 0 RPDRLFQE[5] 0 RPDRLFQE[4] 0 RPDRLFQE[3] 0 RPDRLFQE[2] 0 RPDRLFQE[1] 0 RPDRLFQE[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 160 ...
Page 175
... The physical end address in the RPDRLF queue is the sum of RPDRLFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 161 ...
Page 176
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRSFQS[15] 0 RPDRSFQS[14] 0 RPDRSFQS[13] 0 RPDRSFQS[12] 0 RPDRSFQS[11] 0 RPDRSFQS[10] 0 RPDRSFQS[9] 0 RPDRSFQS[8] 0 RPDRSFQS[7] 0 RPDRSFQS[6] 0 RPDRSFQS[5] 0 RPDRSFQS[4] 0 RPDRSFQS[3] 0 RPDRSFQS[2] 0 RPDRSFQS[1] 0 RPDRSFQS[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 162 ...
Page 177
... The physical start address of the RPDRSF queue is the sum of RPDRSFQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 163 ...
Page 178
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRSFQW[15] 0 RPDRSFQW[14] 0 RPDRSFQW[13] 0 RPDRSFQW[12] 0 RPDRSFQW[11] 0 RPDRSFQW[10] 0 RPDRSFQW[9] 0 RPDRSFQW[8] 0 RPDRSFQW[7] 0 RPDRSFQW[6] 0 RPDRSFQW[5] 0 RPDRSFQW[4] 0 RPDRSFQW[3] 0 RPDRSFQW[2] 0 RPDRSFQW[1] 0 RPDRSFQW[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 164 ...
Page 179
... The physical write address in the RPDRSF queue is the sum of RPDRSFQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 165 ...
Page 180
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRSFQR[15] 0 RPDRSFQR[14] 0 RPDRSFQR[13] 0 RPDRSFQR[12] 0 RPDRSFQR[11] 0 RPDRSFQR[10] 0 RPDRSFQR[9] 0 RPDRSFQR[8] 0 RPDRSFQR[7] 0 RPDRSFQR[6] 0 RPDRSFQR[5] 0 RPDRSFQR[4] 0 RPDRSFQR[3] 0 RPDRSFQR[2] 0 RPDRSFQR[1] 0 RPDRSFQR[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 166 ...
Page 181
... The physical read address in the RPDRSF queue is the sum of RPDRSFQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 167 ...
Page 182
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRSFQE[15] 0 RPDRSFQE[14] 0 RPDRSFQE[13] 0 RPDRSFQE[12] 0 RPDRSFQE[11] 0 RPDRSFQE[10] 0 RPDRSFQE[9] 0 RPDRSFQE[8] 0 RPDRSFQE[7] 0 RPDRSFQE[6] 0 RPDRSFQE[5] 0 RPDRSFQE[4] 0 RPDRSFQE[3] 0 RPDRSFQE[2] 0 RPDRSFQE[1] 0 RPDRSFQE[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 168 ...
Page 183
... The physical end address in the RPDRSF queue is the sum of RPDRSFQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 169 ...
Page 184
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRRQS[15] 0 RPDRRQS[14] 0 RPDRRQS[13] 0 RPDRRQS[12] 0 RPDRRQS[11] 0 RPDRRQS[10] 0 RPDRRQS[9] 0 RPDRRQS[8] 0 RPDRRQS[7] 0 RPDRRQS[6] 0 RPDRRQS[5] 0 RPDRRQS[4] 0 RPDRRQS[3] 0 RPDRRQS[2] 0 RPDRRQS[1] 0 RPDRRQS[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 170 ...
Page 185
... The physical start address of the RPDRR queue is the sum of RPDRRQS[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 171 ...
Page 186
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRRQW[15] 0 RPDRRQW[14] 0 RPDRRQW[13] 0 RPDRRQW[12] 0 RPDRRQW[11] 0 RPDRRQW[10] 0 RPDRRQW[9] 0 RPDRRQW[8] 0 RPDRRQW[7] 0 RPDRRQW[6] 0 RPDRRQW[5] 0 RPDRRQW[4] 0 RPDRRQW[3] 0 RPDRRQW[2] 0 RPDRRQW[1] 0 RPDRRQW[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 172 ...
Page 187
... The physical write address in the RPDRR queue is the sum of RPDRRQW[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 173 ...
Page 188
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRRQR[15] 0 RPDRRQR[14] 0 RPDRRQR[13] 0 RPDRRQR[12] 0 RPDRRQR[11] 0 RPDRRQR[10] 0 RPDRRQR[9] 0 RPDRRQR[8] 0 RPDRRQR[7] 0 RPDRRQR[6] 0 RPDRRQR[5] 0 RPDRRQR[4] 0 RPDRRQR[3] 0 RPDRRQR[2] 0 RPDRRQR[1] 0 RPDRRQR[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 174 ...
Page 189
... The physical read address in the RPDRR queue is the sum of RPDRRQR[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 175 ...
Page 190
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH RPDRRQE[15] 0 RPDRRQE[14] 0 RPDRRQE[13] 0 RPDRRQE[12] 0 RPDRRQE[11] 0 RPDRRQE[10] 0 RPDRRQE[9] 0 RPDRRQE[8] 0 RPDRRQE[7] 0 RPDRRQE[6] 0 RPDRRQE[5] 0 RPDRRQE[4] 0 RPDRRQE[3] 0 RPDRRQE[2] 0 RPDRRQE[1] 0 RPDRRQE[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 176 ...
Page 191
... The physical end address in the RPDRR queue is the sum of RPDRRQE[15:0] left shifted by 2 bits with the RQB[31:0] bits in the RMAC Receive Queue Base register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 177 ...
Page 192
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X Unused X TDQ_FRN[1] 0 TDQ_FRN[0] 0 TDQ_RDYN[2] 0 TDQ_RDYN[1] 0 TDQ_RDYN[0] 0 CACHE 1 ENABLE 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 178 ...
Page 193
... TDR Free Queue Interrupt (TDQFI) is asserted, as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE TDRs 000 1 001 4 010 6 011 8 100 16 101 32 110 Reserved 111 Reserved PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 179 ...
Page 194
... RELEASED DATA SHEET PMC-1960758 Table 21 – TDQ_FRN[1:0] Settings TDQ_FRN[1:0] PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE Reads Reserved PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 180 ...
Page 195
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH BUSY X RWB 0 Unused X Unused X Unused X Unused X Unused X Unused X PROV 0 CHAN[6] 0 CHAN[5] 0 CHAN[4] 0 CHAN[3] 0 CHAN[2] 0 CHAN[1] 0 CHAN[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 181 ...
Page 196
... This register should be polled to determine when data from an indirect read operation is available or to determine when a new indirect write operation may commence. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 182 ...
Page 197
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TDTB[15] 0 TDTB[14] 0 TDTB[13] 0 TDTB[12] 0 TDTB[11] 0 TDTB[10] 0 TDTB[9] 0 TDTB[8] 0 TDTB[7] 0 TDTB[6] 0 TDTB[5] 0 TDTB[4] 0 TDTB[3] 0 TDTB[2] 0 TDTB[1] 0 TDTB[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 183 ...
Page 198
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TDTB[31] 0 TDTB[30] 0 TDTB[29] 0 TDTB[28] 0 TDTB[27] 0 TDTB[26] 0 TDTB[25] 0 TDTB[24] 0 TDTB[23] 0 TDTB[22] 0 TDTB[21] 0 TDTB[20] 0 TDTB[19] 0 TDTB[18] 0 TDTB[17] 0 TDTB[16] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 184 ...
Page 199
... The table must byte boundary and thus the least significant four bits must be written to logic zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 185 ...
Page 200
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE ISSUE 7 Function Default Unused XXXXH TQB[15] 0 TQB[14] 0 TQB[13] 0 TQB[12] 0 TQB[11] 0 TQB[10] 0 TQB[9] 0 TQB[8] 0 TQB[7] 0 TQB[6] 0 TQB[5] 0 TQB[4] 0 TQB[3] 0 TQB[2] 0 TQB[1] 0 TQB[0] 0 PM7364 FREEDM 32 FRAME ENGINE AND DATA LINK MANAGER 186 ...