PM8313-RI PMC-Sierra Inc, PM8313-RI Datasheet
PM8313-RI
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... DATA SHEET PMC-920702 M13 MULTIPLEXER PMC-Sierra, Inc. ISSUE 5 PM8313 D3MX ISSUE 5: JULY 1998 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM8313 D3MX M13 MULTIPLEXER ...
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... DATA SHEET PMC-920702 PMC-Sierra, Inc. ISSUE 5 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PM8313 D3MX M13 MULTIPLEXER ...
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... PATH MAINTENANCE DATA LINK TRANSMITTER ...........................................38 8.7 ALARM AND CONTROL CHANNEL BIT ORIENTED CODE TRANSMITTER ..39 8.8 M23 MULTIPLEXER ...........................................................................................39 8.9 DS2 FRAMER.....................................................................................................40 8.10 M12 MULTIPLEXER ...........................................................................................42 8.11 LOOPBACK MODES ..........................................................................................43 8.12 MICROPROCESSOR INTERFACE ....................................................................46 9 REGISTER MEMORY MAP.............................................................................................47 10 NORMAL MODE REGISTER DESCRIPTION.................................................................51 10.1 DS3 PMON REGISTERS ...................................................................................75 ISSUE 5 i PM8313 D3MX M13 MULTIPLEXER ...
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... USING THE INTERNAL DATA LINK RECEIVER ..............................................142 12.2.1 KEY USED ON SUBSEQUENT DIAGRAMS: .....................................145 13 FUNCTIONAL TIMING...................................................................................................150 14 ABSOLUTE MAXIMUM RATINGS .................................................................................158 15 D.C. CHARACTERISTICS..............................................................................................159 16 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS...............................161 17 D3MX TIMING CHARACTERISTICS.............................................................................166 18 ORDERING AND THERMAL INFORMATION ...............................................................179 19 MECHANICAL INFORMATION......................................................................................180 ISSUE 5 ii PM8313 D3MX M13 MULTIPLEXER ...
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... REGISTER 17H: DS3 FERR COUNT MSB..................................................................................78 REGISTER 18H: DS3 EXZS COUNT LSB ...................................................................................79 REGISTER 19H: DS3 EXZS COUNT MSB ..................................................................................79 REGISTER 1AH: DS3 PERR COUNT LSB ..................................................................................80 REGISTER 1BH: DS3 PERR COUNT MSB .................................................................................80 REGISTER 1CH: DS3 CPERR COUNT LSB ...............................................................................81 ISSUE 5 iii PM8313 D3MX M13 MULTIPLEXER ...
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... REGISTER 33H: RBOC INTERRUPT STATUS ..........................................................................103 REGISTER 34H: DS3 FRMR CONFIGURATION .......................................................................103 REGISTER 35H: DS3 FRMR INTERRUPT ENABLE (ACE=0) ..................................................106 REGISTER 35H: DS3 FRMR ADDITIONAL CONFIGURATION REGISTER (ACE=1) ..............108 REGISTER 36H: DS3 FRMR INTERRUPT STATUS ..................................................................111 ISSUE 5 iv PM8313 D3MX M13 MULTIPLEXER ...
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... REGISTERS 4AH, 5AH, 6AH, 7AH, 8AH, 9AH AND AAH: MX12 AIS INSERT REGISTER......129 REGISTERS 4BH, 5BH, 6BH, 7BH, 8BH, 9BH AND ABH: MX12 LOOPBACK ACTIVATE REGISTER.....................................................................................................................130 REGISTERS 4CH, 5CH, 6CH, 7CH, 8CH, 9CH AND ACH: MX12 LOOPBACK INTERRUPT REGISTER.....................................................................................................................131 ISSUE 5 v PM8313 D3MX M13 MULTIPLEXER ...
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... INPUT DS3 OVERHEAD SERIAL STREAM .....................................................156 FIGURE 18 - OUTPUT DS3 OVERHEAD SERIAL STREAM .................................................157 FIGURE 19 - MICROPROCESSOR READ ACCESS TIMING ................................................162 FIGURE 20 - MICROPROCESSOR WRITE ACCESS TIMING...............................................164 FIGURE 21 - RECEIVE DS3 INPUT TIMING ..........................................................................166 FIGURE 22 - TRANSMIT DS3 INPUT TIMING........................................................................167 ISSUE 5 vi PM8313 D3MX M13 MULTIPLEXER ...
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... RECEIVE OVERHEAD OUTPUT TIMING .........................................................176 FIGURE 30 - TRANSMIT OVERHEAD OUTPUT TIMING.......................................................177 FIGURE 31 - RECEIVE TRIBUTARY OUTPUT TIMING .........................................................177 FIGURE 32 - RECEIVE DATA LINK OUTPUT TIMING............................................................178 FIGURE 33 - 208 PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX): ...180 ISSUE 5 vii PM8313 D3MX M13 MULTIPLEXER ...
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... D3MX RECEIVE OVERHEAD OUTPUT (FIGURE 29) .....................................175 TABLE 18 - D3MX TRANSMIT OVERHEAD OUTPUT (FIGURE 30) ...................................176 TABLE 19 - D3MX RECEIVE TRIBUTARY OUTPUT (FIGURE 31) ......................................177 TABLE 20 - D3MX RECEIVE DATA LINK OUTPUT (FIGURE 32) ........................................177 TABLE 21 - D3MX ORDERING INFORMATION...................................................................179 TABLE 22 - D3MX THERMAL INFORMATION .....................................................................179 ISSUE 5 viii PM8313 D3MX M13 MULTIPLEXER ...
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... P-bit parity error events per second, 1023 F-bit or M-bit (framing bit) events per second, 65,535 excessive zero (EXZ) events per second, and when enabled for C-bit ISSUE 5 1 PM8313 D3MX M13 MULTIPLEXER -3 bit error rate. ...
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... C-bit parity application, C-bit parity error events, and far end block error events. Inserts bit-oriented codes in the C-bit parity far end alarm and control channel. Optionally inserts the C-bit parity path maintenance data link with an integral HDLC transmitter. Supports polled, interrupt-driven, or DMA access. ISSUE 5 2 PM8313 D3MX M13 MULTIPLEXER ...
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... Supports two asynchronous multiplexing standards: the combination of four DS1 bit streams into a single M12 format DS2 bit stream and the combination of three 2048 kbit/s tributaries into a 6312 kbit/s high speed signal according to CCITT Recommendation G.747. Frames to either a DS2 or G.747 signal. ISSUE 5 3 PM8313 D3MX M13 MULTIPLEXER ...
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... Performs required inversion of second and fourth multiplexed DS1 streams as required by ANSI T1.107 Section 7.2. Allows insertion of per DS1 payload loopback requests encoded in the transmitted C-bits to be activated or cleared under microprocessor control. Inserts X, F, and M bits into transmitted DS2 bit stream. ISSUE 5 4 PM8313 D3MX M13 MULTIPLEXER ...
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... Allows inversion of inserted frame alignment signal for diagnostic purposes. Allows inversion of the C-bits in anticipation of remote loopback recommendations. Demultiplexes a single G.747 format 6312 kbit/s bit stream into three 2048 kbit/s bit streams. ISSUE 5 5 PM8313 D3MX M13 MULTIPLEXER ...
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... DATA SHEET PMC-920702 2 APPLICATIONS M23 Based M13 Multiplexer C-Bit Parity Based M13 Multiplexer M23 Multiplexer M13 Multiplexer Supporting G.747 Tributary Format ISSUE 5 6 PM8313 D3MX M13 MULTIPLEXER ...
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... CCITT Blue Book, Recommendation Q.921 - "ISDN User-Network Interface Data Link Layer Specification", Volume VI, Fascicle VI.10, 1988. 12. CCITT Blue Book, Recommendation G.747 - "Second Order Digital Multiplex Equipment Operating at 6312 kbit/s and Multiplexing Three Tributaries at 2048 kbit/s", Volume III, Fascicle III.4, 1988. ISSUE 5 7 PM8313 D3MX M13 MULTIPLEXER ...
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... DATA SHEET PMC-920702 13. International Organization for Standardization, ISO 3309:1984 - "High-Level Data Link Control Procedures -- Frame Structure". ISSUE 5 8 PM8313 D3MX M13 MULTIPLEXER ...
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... A[7: AT28 LK28 D [7: AT28 ALE TD 1C LK28 PM8313 D3MX M13 MULTIPLEXER (7 Quad D SX-1/E1 line in terfaces TXTIP [ [1] TC LKI[1] TXR [ XTIP [ LKO [1] R XRIN G[1] ...
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... A cce X icrop ro cesso I/F A cce ss 10 PM8313 D3MX M13 MULTIPLEXER # [ ...
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... DATA SHEET PMC-920702 DESCRIPTION The PM8313 D3MX M13 Multiplexer supports asynchronous multiplexing and demultiplexing of 28 DS1s, 21 E1s or 7 DS2s into a DS3 signal. The device supports ANSI T1.107, Bell Communications Research TR-TSY-000009 and CCITT Recommendation G.747 standards. Receive DS3 framing is provided by the DS3 FRMR Framer Block. The FRMR accepts either a B3ZS encoded bipolar unipolar signal compatible with M23 and C-bit parity applications ...
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... The C-bits are set appropriately, with the option of inserting DS1 loopback requests. The MX12 block may be configured to generate an interrupt upon the detection of loopback requests in the received DS2. AIS may be inserted in any of the low speed tributaries in both directions. ISSUE 5 12 PM8313 D3MX M13 MULTIPLEXER ...
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... D0 D1 VSSO VDDO D7 CSB ALE PIN 52 ISSUE 5 PM8313 D3MX 13 PM8313 D3MX M13 MULTIPLEXER PIN 156 TD1CLK9 RD1CLK9 TD1DAT10 RD1DAT10 TD1CLK10 RD1CLK10 TD1DAT11 RD1DAT11 TD1CLK11 NC RD1CLK11 TD1DAT12 RD1DAT12 TD1CLK12 RD1CLK12 TD1DAT13 NC RD1DAT13 TD1CLK13 RD1CLK13 TD1DAT14 RD1DAT14 ...
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... RCLK. 10 The receive output clock (ROCLK) signal provides timing for downstream processing. ROCLK is nominally a 44.736 MHz, 50% duty cycle clock. RODAT, RMFP , RMSFP, RLOS, REXZ and ROHP are updated on the falling edge of ROCLK. ROCLK is a buffered version of RCLK. 14 PM8313 D3MX M13 MULTIPLEXER ...
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... When the framer is out-of-frame, ROHP continues to operate with timing aligned to the old M-frame position. When the framer regains frame alignment the ROHP timing is updated, which may result in a change of frame alignment. ROHP is updated on the falling edge of ROCLK. 15 PM8313 D3MX M13 MULTIPLEXER ...
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... DS3 bipolar stream. REXZ pulses high for one ROCLK cycle whenever 3 or more consecutive zeros are detected. When the Receive DS3 interface is configured to for uni-polar data, the REXZ output is forced low. REXZ is updated on the falling edge of ROCLK. 16 PM8313 D3MX M13 MULTIPLEXER ...
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... DS3 loss of signal condition has been present for either 2.23ms or 13.5 ms. The RRED output is set low when a DS3 out-of- frame condition or DS3 loss of signal condition has been absent for either 2.23ms or 13.5 ms. RRED is updated on the falling edge of ROHCLK. 17 PM8313 D3MX M13 MULTIPLEXER ...
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... X1 • the current M-frame. The RFERF output latency provides a better than 99.99% chance of freezing (i.e. holding RFERF in its previous state) upon a valid state value during the occurrence of an out of frame. RFERF is updated once per M-frame on the falling edge of ROHCLK. 18 PM8313 D3MX M13 MULTIPLEXER ...
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... Typically, RDLINT would be connected to an external DMA device. If the supervising microprocessor is desired to service the RFDL, this output can be wired-ORed with the INTB output when RDLINT is configured as an active-low open drain output. 19 PM8313 D3MX M13 MULTIPLEXER ...
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... Typically, RDLEOM would be connected to the supervising microprocessor when an external DMA is used, signaling the microprocessor that a complete message is ready. In this case the RDLEOM is configured as an active-low open drain output and wired-ORed with the INTB output. 20 PM8313 D3MX M13 MULTIPLEXER ...
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... The internal M12 multiplexers may be 110 bypassed or configured for G.747 multiplexing on an individual basis. Thus the configuration 106 of each of the seven blocks of four RD1CLK 102 signals is independently programmable PM8313 D3MX M13 MULTIPLEXER ...
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... The internal M12 multiplexers may be bypassed or configured for G.747 multiplexing 124 on an individual basis. Thus the configuration 118 of each of the seven blocks of four RD1DAT 114 signals is independently programmable. 108 104 100 PM8313 D3MX M13 MULTIPLEXER ...
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... The internal M12 multiplexers may be 112 bypassed or configured for G.747 multiplexing on an individual basis. Thus the configuration 107 of each of the seven blocks of four TD1CLK 103 signals is independently programmable PM8313 D3MX M13 MULTIPLEXER ...
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... The internal M12 multiplexers may be bypassed or configured for G.747 multiplexing 126 on an individual basis. Thus the configuration 120 of each of the seven blocks of four TD1DAT 115 signals is independently programmable. 109 105 101 PM8313 D3MX M13 MULTIPLEXER ...
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... GD2CLK may be connected to the TD2CLK input clock. GD2CLK is updated on the falling edge of TCLK. 206 The transmit DS2 clock (TD2CLK) signal provides timing for the multiplex side of all of the MX12 TSBs. TD2CLK is nominally a 6.312 MHz, 50% duty cycle clock. 25 PM8313 D3MX M13 MULTIPLEXER ...
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... Typically, TDLUDR would be connected to the supervising microprocessor when an external DMA is used, signaling the microprocessor that a severe error has occurred causing the transmit buffer to underrun. In this case the TDLUDR is configured as an active-low open drain output and wired-ORed with the INTB output. 26 PM8313 D3MX M13 MULTIPLEXER ...
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... Typically, TDLINT would be connected to an external DMA device. If the supervising microprocessor is desired to service the XFDL, this output can be wired-ORed with the INTB output when TDLINT is configured as an active- low open drain output. 27 PM8313 D3MX M13 MULTIPLEXER ...
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... TIMFP is sampled on the rising edge of TICLK. 17 The transmit overhead data (TOH) signal contains the overhead bits ( and M) that may be inserted in the transmitted DS3 stream. TOH is sampled on the rising edge of TOHCLK. 28 PM8313 D3MX M13 MULTIPLEXER ...
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... TCLK. The transmit data output (TDAT) signal represents a unipolar DS3 output stream when configured for single rail operation. TDAT is updated on the falling edge of TCLK by default but may be enabled to be updated on the rising edge of TCLK. 29 PM8313 D3MX M13 MULTIPLEXER ...
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... RDB and WRB determine register accesses 57 The active low read enable (RDB) signal is low during D3MX register read accesses. The D3MX drives the D7-D0 bus with the contents of the addressed register while RDB and CSB are low. 30 PM8313 D3MX M13 MULTIPLEXER ...
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... The TRS input has an integral pull down resistor. TRS should be connected to ground for normal mode register access. 58 The active low reset (RSTB) signal provides an asynchronous D3MX reset. RSTB is a Schmitt triggered input with an integral pull up resistor. 31 PM8313 D3MX M13 MULTIPLEXER ...
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... The pad ring power (VDDO) pins should be connected to a well decoupled + common with VDDI 121 164 200 The pad ring ground (VSSO) pins should be connected to GND in common with VSSI 111 163 183 27 80 132 32 PM8313 D3MX M13 MULTIPLEXER ...
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... The VDDO and VDDI power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the D3MX. 208-pin QFP pins # 13, 28, 40, 61, 67, 73, 79, 85, 93, 113, 119, 125, 131, 140, 147, 165, 171, 178, 185, 192, 197 are all "no-connect". ISSUE 5 33 PM8313 D3MX M13 MULTIPLEXER ...
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... These error indications, as well as the line code violation and excessive zeros indication, may be accumulated over 1 second intervals with the T3 Performance Monitor (PMON). Note that the framer is an ISSUE 5 34 PM8313 D3MX M13 MULTIPLEXER 3 bit error rate than the 3 ...
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... FERF definition. Once correct frame alignment has been found and OOF is deasserted, the buffer location corresponding to the last M- frame will contain valid FERF status and the buffer location corresponding to the second to last M-frame is enabled to be updated every M-frame. ISSUE 5 35 PM8313 D3MX M13 MULTIPLEXER ...
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... The counters are reset in such a manner that error events occurring during the reset period are not missed. ISSUE 5 36 PM8313 D3MX M13 MULTIPLEXER ...
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... Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC bits are set to all ones ("111111" valid code has been detected. The RBOC can be programmed to generate an interrupt when a detected code has been validated and when the code disappears. ISSUE 5 th code ("111111") is similar to the 37 PM8313 D3MX M13 MULTIPLEXER ...
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... Data to be transmitted is provided on an interrupt- driven basis by writing to a double-buffered transmit data register. Upon completion of the frames, a CRC-CCITT frame check sequence is transmitted, followed by idle flag sequences. If the transmit data register underflows, an abort sequence is automatically transmitted. ISSUE 5 38 PM8313 D3MX M13 MULTIPLEXER ...
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... MX23 TSB performs rate adaptation to the DS3 by integral FIFO buffers, controlled by timing circuitry. The FIFO buffers accommodate in excess of 5.0 UIpp of sinusoidal jitter on TD2CLK for all jitter frequencies. The C-bits are also ISSUE 5 th possible code (111111) is similar to the HDLC idle 39 PM8313 D3MX M13 MULTIPLEXER ...
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... DS2 signal or provides indications of the frame boundaries and overhead bit positions in the incoming G.747 signal. Depending on configuration, declaration of DS2 out-of-frame occurs when 2 out out of 5 consecutive F-bits are in error (These two ratios are ISSUE 5 40 PM8313 D3MX M13 MULTIPLEXER ...
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... G.747 frame is continually updated every M-frame/G.747 frame based on the above FERF definition. Once correct frame alignment has been found and OOF is deasserted, the first buffer location will contain a valid FERF status and the ISSUE 5 41 PM8313 D3MX M13 MULTIPLEXER -3 . Each "valid" ...
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... As per TR-TSY-000009 Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. ISSUE 5 42 PM8313 D3MX M13 MULTIPLEXER ...
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... LCVs; if the UNI bit is clear, then the interface is configured for bipolar signals RPOS and RNEG, therefore the TNEG is fed directly to the RNEG input. This loopback mode is shown diagrammatically, below: ISSUE 5 43 PM8313 D3MX M13 MULTIPLEXER ...
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... DS3-FRMR receive interface for this mode to work properly. This loopback mode is shown diagrammatically, below: ISSUE PM8313 D3MX M13 MULTIPLEXER ...
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... ISSUE ptional AIS Insertion 45 PM8313 D3MX M13 MULTIPLEXER ...
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... PM8313 D3MX M13 MULTIPLEXER ptional AIS ...
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... DS3 PMON LCV Count (MSB) 16H DS3 PMON FERR Count (LSB) 17H DS3 PMON FERR Count (MSB) 18H DS3 PMON EXZS Count (LSB) 19H DS3 PMON EXZS Count (MSB) 1AH DS3 PMON PERR Count (LSB) ISSUE 5 47 PM8313 D3MX M13 MULTIPLEXER ...
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... MX23 Loopback Request Interrupt 2FH MX23 Reserved 30H FEAC XBOC Reserved 31H FEAC XBOC Code 32H FEAC RBOC Configuration/Interrupt Enable 33H FEAC RBOC Interrupt Status 34H DS3 FRMR Configuration 35H DS3 FRMR Interrupt Enable/Additional Configuration ISSUE 5 48 PM8313 D3MX M13 MULTIPLEXER ...
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... DS2 #4 MX12 Registers 80H - 87H DS2 #5 FRMR Registers 88H - 8CH DS2 #5 MX12 Registers 90H - 97H DS2 #6 FRMR Registers 98H - 9CH DS2 #6 MX12 Registers A0H - A7H DS2 #7 FRMR Registers A8H - ACH DS2 #7 MX12 Registers ISSUE 5 49 PM8313 D3MX M13 MULTIPLEXER ...
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... DATA SHEET PMC-920702 Address Register ACH - FFH Reserved 100H-1FFH Reserved for Test For all register accesses, CSB must be low. ISSUE 5 50 PM8313 D3MX M13 MULTIPLEXER ...
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... D3MX to determine the programming state of the block. 3. Writeable normal mode register bits are cleared to logic 0 upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect D3MX operation unless otherwise noted. ISSUE 5 51 PM8313 D3MX M13 MULTIPLEXER ...
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... The DS2 Transmit Clock Activity (DS2TCACT) bit indicates at least one low to high transition has occurred on the TD2CLK input since the last read of this register. The DS2TCACT bit is set to a logic rising edge on the ISSUE 5 Function Default DS3RCACT X DS3TCACT X DS2TCACT X Unused X Unused X Unused X Unused X RESET 0 52 PM8313 D3MX M13 MULTIPLEXER ...
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... DATA SHEET PMC-920702 TD2CLK input and is cleared to a logic read of this register. Note that if the TD2CLK signal is absent for a period of time (i.e., TD2CLK clock failure), the D3MX must be reset once the TD2CLK signal is restored. ISSUE 5 53 PM8313 D3MX M13 MULTIPLEXER ...
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... D3MX. These bits can be read by software to determine the version number. Writing to this register causes all performance monitor counters (DS3 and DS2/G.747 updated simultaneously. ISSUE 5 Function Default ID7 0 ID6 0 ID5 0 ID4 0 ID3 0 ID2 0 ID1 0 ID0 0 54 PM8313 D3MX M13 MULTIPLEXER ...
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... A nominally 6.312 MHz clock is presented on RD1CLK(4n data stream synchronous to RD1CLK(4n) is presented on RD1DAT(4n). 7. The signals on RD1CLK(4n-1), RD1CLK(4n-2), RD1CLK(4n-3), RD1DAT(4n-1), RD1DAT(4n-2) and RD1DAT(4n-3) are always low. ISSUE 5 Function Default EXD2CLK 0 BYP7 0 BYP6 0 BYP5 0 BYP4 0 BYP3 0 BYP2 0 BYP1 0 55 PM8313 D3MX M13 MULTIPLEXER ...
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... DS3 transmit TICLK clock. The generated DS2 clock is nominally 6.306272 MHz while in C-bit parity mode and while in M23 mode nominally 6.311993 MHz. If EXD2CLK is a logic 1, the transmit DS2 clock becomes TD2CLK. ISSUE 5 56 PM8313 D3MX M13 MULTIPLEXER ...
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... HDLC transmitter. When the TEXHDLC bit is a logic 1, the use of an external HDLC transmitter is selected; the TDLSIG/TDLUDR pin is configured to input the data link data ISSUE 5 Function Default REXHDLC 0 TEXHDLC 1 Unused X Unused X REOMPOL 0 TUDRPOL 0 RINTPOL 0 TINTPOL 0 57 PM8313 D3MX M13 MULTIPLEXER ...
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... TDLINT output. If TINTPOL is a logic 0, the TDLINT output is an active low open-drain output. If TINTPOL is a logic 1, the TDLINT output is asserted high and always has a strong drive. If the TEXHDLC bit is a logic 1, this bit has no effect. ISSUE 5 58 PM8313 D3MX M13 MULTIPLEXER ...
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... The LINEAIS[1:0] option is expected to be used when the diagnostic loopback is invoked, ensuring that only a valid DS3 stream enters the network. The LINEAIS[1:0] bits select one of the following AIS patterns for transmission: ISSUE 5 Function Default Unused X Unused X Unused X Unused X LINEAIS[1] 0 LINEAIS[0] 0 LLBE 0 DLBE 0 59 PM8313 D3MX M13 MULTIPLEXER ...
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... If the intention is to loopback the AIS, the AIS bit in the DS3 TRAN Configuration Register should be written instead. ISSUE 5 AIS Transmitted none Framed, repetitive 1010… pattern with C-bits forced to logic 0 Framed, repetitive 1111… pattern with C-bits forced to logic 0 Unframed, all-ones pattern 60 PM8313 D3MX M13 MULTIPLEXER ...
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... TPOS and TNEG. TRISE: The transmit falling edge select (TRISE) bit configures the updating edge used on the DS3 transmit interface. When TRISE is a logic 1, the DS3 ISSUE 5 Function Default Unused X Unused X Unused X TINV 0 TRISE 0 TUNI 0 RINV 0 RFALL 0 61 PM8313 D3MX M13 MULTIPLEXER ...
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... When TINV is a logic 1, the TPOS and TNEG signals are active low. When TINV is a logic 0, the TPOS and TNEG signals are active high. Inversion only takes place when the DS3 transmit interface is configured for dual rail operation. ISSUE 5 62 PM8313 D3MX M13 MULTIPLEXER ...
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... DS2 AIS. When DS3ALME is set to logic 1 and REDALME is set to logic 0, any occurrence of LOS or OOF generates the DS2 AIS. If DS3ALME is a logic 0, the REDALME bit is ignored. ISSUE 5 Function Default TNR 1 RNR X ALTFEBE 0 REDO 0 RED2ALME 0 DS2ALME 0 RED3ALME 0 DS3ALME 0 63 PM8313 D3MX M13 MULTIPLEXER ...
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... FEBE is generated. If ALTFEBE is a logic 0, a FEBE indication is generated if either one or more framing bit errors or a C-bit parity error has occurred in the last received M-frame framing bit errors nor C-bit parity errors have occurred, then no FEBE is generated. ISSUE 5 64 PM8313 D3MX M13 MULTIPLEXER ...
Page 75
... AIS in C-bit parity mode. ISSUE 5 ) bit presented in the second C-bit overhead bit timeslot. If C-bit parity is not selected, the r ) bit transmitted in the second C-bit overhead bit timeslot. The TNR bit is set bit PM8313 D3MX M13 MULTIPLEXER ...
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... CSB pin high causes the D3MX to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the ISSUE 5 Function Default VCLK_IOTST X Unused X Unused X PMCTST X DBCTRL X IOTST X HIZDATA X HIZIO X 66 PM8313 D3MX M13 MULTIPLEXER ...
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... HIZIO bit is a logic 1, all output pins of the D3MX except the data bus are held in a high-impedance state. The microprocessor interface is still active. While the HIZDATA bit is a logic 1, the data bus is also held in a high- impedance state which inhibits microprocessor read cycles. ISSUE 5 67 PM8313 D3MX M13 MULTIPLEXER ...
Page 78
... HDLC, i.e. REXHDLC=0). RFDLINT: If the RFDLINT bit is a logic 1, the RFDL TSB is generating an interrupt (also visible on the RDLINT output when configured for internal HDLC, i.e. REXHDLC=0). ISSUE 5 Function Default REG2 0 REG3 0 XFDLINT 0 MX23 0 DS3FRMR 0 RFDLINT 0 RFDLEOM 0 RBOC 0 68 PM8313 D3MX M13 MULTIPLEXER ...
Page 79
... Register is set, that is, at least one DS2 Framer or the XFDL is generating an interrupt. REG3: If the REG3 bit is a logic 1, at least one bit in the Master Interrupt Source #3 Register is set, that is, at least one M12 Multiplexer is generating an interrupt. ISSUE 5 69 PM8313 D3MX M13 MULTIPLEXER ...
Page 80
... If the XFDLUDR bit is a logic 1, the XFDL TSB is generating an interrupt due to an underrun of the transmit data buffer (also visible on the TDLUDR output when configured for internal HDLC, i.e. TEXHDLC=0). ISSUE 5 Function Default XFDLUDR 0 DS2FRMR #7 0 DS2FRMR #6 0 DS2FRMR #5 0 DS2FRMR #4 0 DS2FRMR #3 0 DS2FRMR #2 0 DS2FRMR # PM8313 D3MX M13 MULTIPLEXER ...
Page 81
... Reading this register does not remove the interrupt indication; the corresponding TSB's interrupt status register must be read to remove the interrupt indication. ISSUE 5 Function Default DS3PMON 0 MX12 #7 0 MX12 #6 0 MX12 #5 0 MX12 #4 0 MX12 #3 0 MX12 #2 0 MX12 # PM8313 D3MX M13 MULTIPLEXER ...
Page 82
... When AIS is a logic 1, the transmit DS3 payload (on the TDAT/TPOS and TNEG outputs) is overwritten with the pattern 1010... When IDL is a logic 1, the transmit DS3 payload is overwritten with the pattern 1100... ISSUE 5 Function Default CBTRAN 0 AIS 0 IDL 0 FERF 0 SBOW 0 Unused X Unused X CBIT 0 72 PM8313 D3MX M13 MULTIPLEXER ...
Page 83
... When CBTRAN is a logic 1 and the M23 application is enabled, the C-bits pass through transparently during AIS transmission. When CBTRAN is a logic 1, and the C-bit parity application is enabled, the C-bits are overwritten with the appropriate C-bit parity functions during AIS transmission. ISSUE 5 73 PM8313 D3MX M13 MULTIPLEXER ...
Page 84
... The DFERR controls the insertion of framing errors (F-bit errors) in the outgoing DS3 stream. When DFERR is set to a logic 1, the F-bits are inverted before insertion in the DS3 stream. ISSUE 5 Function Default DLOS 0 DLCV 0 Unused X DFERR 0 DMERR 0 DCPERR 0 DPERR 0 DFEBE 0 74 PM8313 D3MX M13 MULTIPLEXER ...
Page 85
... PMON registers should not be read until 6 µs have elapsed since the microprocessor write was performed. The data contained in the holding registers are subsequently read from the PMON registers by the microprocessor. The loading is synchronized to the internal event timing so that no events are missed. ISSUE 5 75 PM8313 D3MX M13 MULTIPLEXER ...
Page 86
... DS3 PMON from generating an interrupt. When the TSB is reset, the INTE bit is set to logic 0, disabling the interrupt. The interrupt is cleared when this register is read. ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 INTR 0 OVR 0 76 PM8313 D3MX M13 MULTIPLEXER ...
Page 87
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either LCV Count Register. ISSUE 5 Function Default LCV[7] X LCV[6] X LCV[5] X LCV[4] X LCV[3] X LCV[2] X LCV[1] X LCV[0] X Function Default LCV[15] X LCV[14] X LCV[13] X LCV[12] X LCV[11] X LCV[10] X LCV[9] X LCV[ PM8313 D3MX M13 MULTIPLEXER ...
Page 88
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FERR Count Register. ISSUE 5 Function Default FERR[7] X FERR[6] X FERR[5] X FERR[4] X FERR[3] X FERR[2] X FERR[1] X FERR[0] X Function Default Unused X Unused X Unused X Unused X Unused X Unused X FERR[9] X FERR[ PM8313 D3MX M13 MULTIPLEXER ...
Page 89
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either EXZS Count Register. ISSUE 5 Function Default EXZS[7] X EXZS[6] X EXZS[5] X EXZS[4] X EXZS[3] X EXZS[2] X EXZS[1] X EXZS[0] X Function Default EXZS[15] X EXZS[14] X EXZS[13] X EXZS[12] X EXZS[11] X EXZS[10] X EXZS[9] X EXZS[ PM8313 D3MX M13 MULTIPLEXER ...
Page 90
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either PERR Count Register. ISSUE 5 Function Default PERR[7] X PERR[6] X PERR[5] X PERR[4] X PERR[3] X PERR[2] X PERR[1] X PERR[0] X Function Default Unused X Unused X PERR[13] X PERR[12] X PERR[11] X PERR[10] X PERR[9] X PERR[ PM8313 D3MX M13 MULTIPLEXER ...
Page 91
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either CPERR Count Register. ISSUE 5 Function Default CPERR[7] X CPERR[6] X CPERR[5] X CPERR[4] X CPERR[3] X CPERR[2] X CPERR[1] X CPERR[0] X Function Default Unused X Unused X CPERR[13] X CPERR[12] X CPERR[11] X CPERR[10] X CPERR[9] X CPERR[ PM8313 D3MX M13 MULTIPLEXER ...
Page 92
... A transfer operation of all counter registers within the selected PMON can be triggered by writing to either FEBE Count Register. ISSUE 5 Function Default FEBE[7] X FEBE[6] X FEBE[5] X FEBE[4] X FEBE[3] X FEBE[2] X FEBE[1] X FEBE[0] X Function Default Unused X Unused X FEBE[13] X FEBE[12] X FEBE[11] X FEBE[10] X FEBE[9] X FEBE[ PM8313 D3MX M13 MULTIPLEXER ...
Page 93
... The INTE bit enables the generation of an interrupt via the TDLINT output. Setting the INTE bit to logic 1 enables the generation of an interrupt by asserting the TDLINT output; setting INTE to logic 0 disables the generation of an interrupt. ISSUE 5 Function Default Unused X Unused X Unused X EOM 0 INTE 0 ABT 0 CRC PM8313 D3MX M13 MULTIPLEXER ...
Page 94
... FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is automatically cleared before transmission of the next data packet begins. The EOM register bit value can also be set to logic 1 by pulsing the TDLEOMI input pin. ISSUE 5 84 PM8313 D3MX M13 MULTIPLEXER ...
Page 95
... XFDL will continuously transmit the all-ones idle pattern. The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in this register. ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X INT 0 UDR 0 85 PM8313 D3MX M13 MULTIPLEXER ...
Page 96
... At a nominal 28.2 kbit/sec link data rate the required write interval is 110µsec. ISSUE 5 Function Default TD7 X TD6 X TD5 X TD4 X TD3 X TD2 X TD1 X TD0 X 86 PM8313 D3MX M13 MULTIPLEXER ...
Page 97
... The RFDL TSB handles the TR input in the same manner as clearing and setting the EN bit, therefore, the RFDL state machine will begin searching for flags and an interrupt will be generated when the first flag is detected. ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused PM8313 D3MX M13 MULTIPLEXER ...
Page 98
... OVR (FIFO overrun), detection of the abort sequence while not ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X INTC1 0 INTC0 0 INT 0 Description Disable interrupts (All sources) Enable interrupt when FIFO receives data Enable interrupt when FIFO has 2 bytes of data Enable interrupt when FIFO has 3 bytes of data 88 PM8313 D3MX M13 MULTIPLEXER ...
Page 99
... FIFO overrun. The interrupt due to a FIFO overrun is cleared on a Status register read, by disabling the TSB setting TR high. The contents of the Interrupt Control/Status register should only be changed when the RFDL TSB is disabled to prevent any erroneous interrupt generation. ISSUE 5 89 PM8313 D3MX M13 MULTIPLEXER ...
Page 100
... The End of Message bit (EOM) follows the RDLEOM output set when: 1. The last byte in the LAPD frame (EOM) is being read from the Receive Data Register, ISSUE 5 Function Default FE X OVR X FLG X EOM X CRC X NVB2 X NVB1 X NVB0 X 90 PM8313 D3MX M13 MULTIPLEXER ...
Page 101
... If the Receive Data register is read while there is no valid data, then a FIFO underrun condition occurs. The underrun condition is reflected in the Status register by forcing all bits to logic zero on the first Status register read immediately following the Received Data register read which caused the underrun condition. ISSUE 5 91 PM8313 D3MX M13 MULTIPLEXER ...
Page 102
... If the Receive Data register read causes an FIFO underrun, then the pointer is inhibited from incrementing. The underrun condition will be signaled in the next Status read by returning all zeros. ISSUE 5 Function Default RD7 X RD6 X RD5 X RD4 X RD3 X RD2 X RD1 X RD0 X 92 PM8313 D3MX M13 MULTIPLEXER ...
Page 103
... C-bits of the DS3 signals. Transmit and receive are not independent; the same code is expected in the receive DS3 as is inserted in the transmitted DS3. The following table gives the correspondence between LBCODE[1:0] bits and the valid codes: ISSUE 5 Function Default Unused X Unused X Unused X Unused X LBCODE[1] 0 LBCODE[0] 0 CBE 0 INTE 0 93 PM8313 D3MX M13 MULTIPLEXER ...
Page 104
... Section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported. LBCODE[1:0]: The LBCODE[1:0] bits become logical 0 upon either a hardware or software reset. ISSUE 5 Loopback Code and and and and PM8313 D3MX M13 MULTIPLEXER ...
Page 105
... DS2 loopback may be invoked using the Loopback Activate register thus allowing demux AIS to be inserted into the through path while a DS2 loopback is activated, if desired. ISSUE 5 Function Default Unused X DAIS[7] 0 DAIS[6] 0 DAIS[5] 0 DAIS[4] 0 DAIS[3] 0 DAIS[2] 0 DAIS[ PM8313 D3MX M13 MULTIPLEXER ...
Page 106
... TDAT. Mux AIS insertion takes place before the point where per DS2 loopback may be invoked using the Loopback Activate register and thus mux AIS cannot be inserted while a DS2 loopback is activated. ISSUE 5 Function Default Unused X MAIS[7] 0 MAIS[6] 0 MAIS[5] 0 MAIS[4] 0 MAIS[3] 0 MAIS[2] 0 MAIS[ PM8313 D3MX M13 MULTIPLEXER ...
Page 107
... DS3 signal to the output DS3 signal. The demultiplexed DS2 signals continue to present valid payloads while loopbacks are activated. The MX23 Demux AIS Insert Register allows insertion of DS2 AIS if required. ISSUE 5 Function Default Unused X LBA[7] 0 LBA[6] 0 LBA[5] 0 LBA[4] 0 LBA[3] 0 LBA[2] 0 LBA[ PM8313 D3MX M13 MULTIPLEXER ...
Page 108
... Setting any of the ILBR[7:1] bits enables the insertion of a loopback request in the corresponding DS2 stream in the output DS3 signal. The format of the loopback request is determined by the LBCODE[1:0] bits in the MX23 Configuration Register. ISSUE 5 Function Default Unused X ILBR[7] 0 ILBR[6] 0 ILBR[5] 0 ILBR[4] 0 ILBR[3] 0 ILBR[2] 0 ILBR[ PM8313 D3MX M13 MULTIPLEXER ...
Page 109
... Section 3.7, the loopback request must be present for five successive M-frames before declaration of detection. Removal of the loopback request is declared when it has been absent for five successive M-frames. ISSUE 5 Function Default Unused X LBRD[7] X LBRD[6] X LBRD[5] X LBRD[4] X LBRD[3] X LBRD[2] X LBRD[ PM8313 D3MX M13 MULTIPLEXER ...
Page 110
... INTB, is activated. The LBRI[7:1] bits are to logic 0 immediately following a read of the register, acknowledging the interrupt and deactivating the INTB output. ISSUE 5 Function Default Unused X LBRI[7] X LBRI[6] X LBRI[5] X LBRI[4] X LBRI[3] X LBRI[2] X LBRI[1] X 100 PM8313 D3MX M13 MULTIPLEXER ...
Page 111
... When the register is written with 111111, the XBOC TSB is disabled. ISSUE 5 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 101 PM8313 D3MX M13 MULTIPLEXER ...
Page 112
... BOC to idle code. A logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 102 PM8313 D3MX M13 MULTIPLEXER ...
Page 113
... BOC to idle code has been detected. IDLEI is cleared to logic 0 when the register is read. Register 34H: DS3 FRMR Configuration Bit Type Bit7 R/W Bit6 R/W Bit5 R/W ISSUE 5 Function Default IDLEI X BOCI X BOC[5] X BOC[4] X BOC[3] X BOC[2] X BOC[1] X BOC[0] X Function Default AISPAT 1 FDET 0 MBDIS 0 103 PM8313 D3MX M13 MULTIPLEXER ...
Page 114
... When a logic 0 is written to UNI, the FRMR accepts bipolar data on its inputs and performs B3ZS decoding and line code violation reporting. ISSUE 5 Function Default M3O8 0 UNI 0 REFR 0 AISC 0 CBE 0 104 PM8313 D3MX M13 MULTIPLEXER ...
Page 115
... The C-bits are checked for the value specified by the AISC bit setting. When a logic 0 is written to AISPAT, the AIS detection algorithm is determined solely by the settings of AISC and AISONES register bits (see bit mapping table in the Additional Configuration Register description). ISSUE 5 105 PM8313 D3MX M13 MULTIPLEXER ...
Page 116
... AISV bit location in the DS3 FRMR Status register and on the RAIS pin. When AISE is set to logic 1, the interrupt output, INTB, is set low when the state of the AIS detector changes. ISSUE 5 Function Default COFAE 0 REDE 0 CBITE 0 FERFE 0 IDLE 0 AISE 0 OOFE 0 LOSE 0 106 PM8313 D3MX M13 MULTIPLEXER ...
Page 117
... The COFAE bit enables an interrupt to be generated when a change of frame alignment (i.e. a COFA event ) occurs. When COFAE is set to logic 1, the interrupt output, INTB, is set low when the COFA event occurs. A FRMR-generated interrupt is cleared when the FRMR Interrupt Status Register is read. ISSUE 5 107 PM8313 D3MX M13 MULTIPLEXER ...
Page 118
... LCV. For example sequence of 15 consecutive zeros were received, with EXZDET=1 only a single LCV would be indicated for this string of excessive zeros; with ISSUE 5 Function Default Unused X Unused X AISONES 0 BPVO 0 EXZSO 0 EXZDET 0 SALGO 0 DALGO 0 108 PM8313 D3MX M13 MULTIPLEXER ...
Page 119
... AIS. In this case all the bits, including the overhead, are observed to follow an all-ones pattern. The valid combinations of AISPAT, AISC, and AISONES bits are summarized below: ISSUE 5 109 PM8313 D3MX M13 MULTIPLEXER ...
Page 120
... Framed DS3 stream containing C-bits all logic 0; payload bits ignored. X Framed DS3 stream containing repeating 1010… pattern and C-bits all logic 0. 0 Framed DS3 stream containing all-ones payload pattern; overhead bits ignored. 1 Unframed all-ones DS3 stream. 110 PM8313 D3MX M13 MULTIPLEXER ...
Page 121
... DS3 FRMR Status register and on the RAIS pin. When the AISI bit is a logic 1, a change in the AIS detector state has occurred. When the AISI bit is logic 0, no change in the AIS detector state has occurred. ISSUE 5 Function Default COFAI X REDI X CBITI X FERFI X IDLI X AISI X OOFI X LOSI X 111 PM8313 D3MX M13 MULTIPLEXER ...
Page 122
... When the COFAI bit is logic 0, there was no difference from the current frame alignment and the previous frame alignment. The interrupt status bits are cleared when the FRMR Interrupt Status Register is read. ISSUE 5 112 PM8313 D3MX M13 MULTIPLEXER ...
Page 123
... When the IDLV bit is a logic 1, the DS3 IDLE pattern has been received for 2.23ms (or for 13.5ms when FDET is logic 0). When the IDLV bit is logic 0, the DS3 IDLE pattern has not been received for either 2.23ms or 13.5ms. ISSUE 5 Function Default ACE 0 REDV X CBITV X FERFV X IDLV X AISV X OOFV X LOSV X 113 PM8313 D3MX M13 MULTIPLEXER ...
Page 124
... OOFV=0) for 2.23ms ( or 13.5ms if FDET=0). ACE: The ACE bit selects the Additional Configuration Register. This register is located at address 35H, and is only accessible when the ACE bit is set to logic 1. When ACE is set to logic 0, the Interrupt Enable register is accessible at address 35H. ISSUE 5 114 PM8313 D3MX M13 MULTIPLEXER ...
Page 125
... When the FRMR is configured for G.747 operation (the G747 bit is set to logic 1), the OOF status is declared when 4 consecutive framing word errors occur (as per CCITT Rec. G747 Section 4), regardless of the M2O5 bit setting. ISSUE 5 Function Default G747 0 Unused X WORD 0 M2O5 0 MBDIS 0 REFR 0 Unused X Unused X 115 PM8313 D3MX M13 MULTIPLEXER ...
Page 126
... The G747 bit configures the FRMR for G.747 operation. If the G747 bit is a logic 1, the FRMR will process a G.747 signal. If the G747 bit is a logic 0, the FRMR will process a DS2 signal as defined in ANSI T1.107 Section 7. ISSUE 5 116 PM8313 D3MX M13 MULTIPLEXER ...
Page 127
... The RESE bit has no effect in DS2 mode. The interrupt output, INTB, is deasserted when the Interrupt Status Register is read if its assertion was a result an OOF, AIS, FERF, RED, RES, or COFA event. ISSUE 5 Function Default COFAE 0 Unused X REDE 0 FERFE 0 RESE 0 AISE 0 OOFE 0 Unused X 117 PM8313 D3MX M13 MULTIPLEXER ...
Page 128
... The interrupt status bits are cleared when the DS2 FRMR Interrupt Status Register is read. ISSUE 5 Function Default COFAI X Unused X REDI X FERFI X RESI X AISI X OOFI X Unused X 118 PM8313 D3MX M13 MULTIPLEXER ...
Page 129
... G.747 mode). This is less than 1.5 times the maximum average reframe time allowed. The REDV status will remain asserted for 9.9 ms (6.9ms in G.747 mode) after frame alignment has been declare and then become logic 0. ISSUE 5 Function Default Unused X Unused X REDV X FERFV X RESV X AISV X OOFV X Unused X 119 PM8313 D3MX M13 MULTIPLEXER ...
Page 130
... DATA SHEET PMC-920702 RESV: The RESV bit reflects the debounced state of the reserved bit in Set II when in G.747 mode. The debounced value of the reserved bit only changes when the reserved bit is the same for two consecutive frames. ISSUE 5 120 PM8313 D3MX M13 MULTIPLEXER ...
Page 131
... Holding Registers have been overwritten. A logic 0 indicates that no overrun has occurred. This bit is reset to logic 0 when this register is read. ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X INTE 0 INTR 0 OVR 0 121 PM8313 D3MX M13 MULTIPLEXER ...
Page 132
... DATA SHEET PMC-920702 To generate a transfer of the counters to the holding registers, a microprocessor write to the Global PMON Update Register is required. ISSUE 5 122 PM8313 D3MX M13 MULTIPLEXER ...
Page 133
... DS2 framing bit error event is either an M-bit or and F-bit error. One or more bit errors in a G.747 frame alignment signal results in a single framing word error. A transfer operation can be triggered by writing to the Global PMON Update Register. ISSUE 5 Function Default FERR[7] X FERR[6] X FERR[5] X FERR[4] X FERR[3] X FERR[2] X FERR[1] X FERR[0] X 123 PM8313 D3MX M13 MULTIPLEXER ...
Page 134
... A transfer operation can be triggered by writing to the Global PMON Update Register. ISSUE 5 Function Default PERR[7] X PERR[6] X PERR[5] X PERR[4] X PERR[3] X PERR[2] X PERR[1] X PERR[0] X Function Default Unused X Unused X Unused X PERR[12] X PERR[11] X PERR[10] X PERR[9] X PERR[8] X 124 PM8313 D3MX M13 MULTIPLEXER ...
Page 135
... When set high, the XAIS bit enables the transmission of the alarm indication signal (AIS) in the 6312 kbit/s output stream. When XAIS is set high, the transmitted data is set to all ones; otherwise the transmitted data is not affected. ISSUE 5 Function Default G747 0 PINV 0 MINV 0 FINV 0 XAIS 0 XFERF 0 XRES 0 INTE 0 125 PM8313 D3MX M13 MULTIPLEXER ...
Page 136
... When G747 is high, the MX12 supports CCITT Recommendation G.747. In this mode, three 2048 kbit/s tributaries are multiplexed into and demultiplex out of a 840 bit frame. If G747 is low, the frame format is compatible with DS2 as specified in the ANSI T1.107 Standard. ISSUE 5 126 PM8313 D3MX M13 MULTIPLEXER ...
Page 137
... C-bits of the G.747 formatted signal. Again, the transmit and ISSUE 5 Function Default Unused X Unused X Unused X Unused X Unused X Unused X LBCODE[1] 0 LBCODE[0] 0 Loopback Code and and and and 127 PM8313 D3MX M13 MULTIPLEXER ...
Page 138
... G.747 stream as is inserted in the G.747 stream to be multiplexed. The valid codes are the same as those for the DS2 formatted stream given in the table above. The LBCODE[1:0] bits become logical 0 upon either a hardware or software reset. ISSUE 5 128 PM8313 D3MX M13 MULTIPLEXER ...
Page 139
... Mux AIS insertion takes place before the point where remote loopback may be invoked using the Loopback Activate register and thus mux AIS cannot be inserted while a loopback is activated. ISSUE 5 Function Default MAIS[4] 0 MAIS[3] 0 MAIS[2] 0 MAIS[1] 0 DAIS[4] 0 DAIS[3] 0 DAIS[2] 0 DAIS[1] 0 129 PM8313 D3MX M13 MULTIPLEXER ...
Page 140
... The format of the loopback request is determined by the LBCODE[1:0] bits in the Loopback Code Select MX12 Register. In G.747 mode, ILBR[j] inverts bit the G.747 frame in an analogous fashion ISSUE 5 Function Default ILBR[4] 0 ILBR[3] 0 ILBR[2] 0 ILBR[1] 0 LBA[4] 0 LBA[3] 0 LBA[2] 0 LBA[1] 0 130 PM8313 D3MX M13 MULTIPLEXER ...
Page 141
... Configuration register then the interrupt output, INTB, is activated. The LBRI[4:1] bits are cleared low immediately following a read of the register, acknowledging the interrupt and deactivating the INTB output. ISSUE 5 Function Default LBRI[4] X LBRI[3] X LBRI[2] X LBRI[1] X LBRD[4] X LBRD[3] X LBRD[2] X LBRD[1] X 131 PM8313 D3MX M13 MULTIPLEXER ...
Page 142
... PMON Test Register 0 111H PMON Test Register 1 112H PMON Test Register 2 113H - 11FH Reserved 120H XFDL Test Register 0 121H XFDL Test Register 1 122H - 123H Reserved 124H RFDL Test Register 0 125H RFDL Test Register 1 126H-127H Reserved ISSUE 5 132 PM8313 D3MX M13 MULTIPLEXER ...
Page 143
... DS2 #1 MX12 Test Register 2 14BH - 14FH Reserved 150H DS2 #2 FRMR Test Register 0 151H DS2 #2 FRMR Test Register 1 152H DS2 #2 FRMR Test Register 2 153H - 157H Reserved 158H DS2 #2 MX12 Test Register 0 159H DS2 #2 MX12 Test Register 1 ISSUE 5 133 PM8313 D3MX M13 MULTIPLEXER ...
Page 144
... DS2 #5 FRMR Test Register 2 183H - 187H Reserved 188H DS2 #5 MX12 Test Register 0 189H DS2 #5 MX12 Test Register 1 18AH DS2 #5 MX12 Test Register 2 18BH - 18FH Reserved 190H DS2 #6 FRMR Test Register 0 191H DS2 #6 FRMR Test Register 1 ISSUE 5 134 PM8313 D3MX M13 MULTIPLEXER ...
Page 145
... Writing values into unused register bits has no effect. Reading back unused bits can produce either a logic one or a logic zero; hence unused bits should be masked off by software when read. 2. Writeable register bits are not initialized upon reset unless otherwise noted. ISSUE 5 135 PM8313 D3MX M13 MULTIPLEXER ...
Page 146
... D3MX to drive the data bus and holding the CSB pin low tri- states the data bus. The DBCTRL bit overrides the HIZDATA bit. The ISSUE 5 Function Default VCLK_IOTST X Unused X Unused X PMCTST X DBCTRL X IOTST X HIZDATA X HIZIO X 136 PM8313 D3MX M13 MULTIPLEXER ...
Page 147
... Reading the following address locations returns the values for the indicated inputs : ISSUE 5 137 PM8313 D3MX M13 MULTIPLEXER ...
Page 148
... TD1DAT18 TD1DAT17 TD1CLK20 TD1DAT22 TD1DAT21 TD1CLK24 TD1DAT26 TD1DAT25 TD1CLK28 Bit 5 Bit 4 Bit 3 TNEG/ TPOS/ TMFP 1,3 TDAT 2,3 TDLCLK/ TDLINT 5 138 PM8313 D3MX M13 MULTIPLEXER Bit 2 Bit 1 Bit 0 TOH TOHEN TDLEOMI RCLK 2 RNEG/ RPOS/ RLCV 1,4 RDAT 1,4 TD1CLK3 TD1CLK2 TD1CLK1 TD1CLK7 TD1CLK6 TD1CLK5 TD1CLK11 ...
Page 149
... RD1DAT6 RD1DAT5 RD1CLK8 RD1DAT10 RD1DAT9 RD1CLK12 RD1DAT14 RD1DAT13 RD1CLK16 RD1DAT18 RD1DAT17 RD1CLK20 RD1DAT22 RD1DAT21 RD1CLK24 RD1DAT26 RD1DAT25 RD1CLK28 139 PM8313 D3MX M13 MULTIPLEXER Bit 2 Bit 1 Bit 0 TDLSIG/ TDLCLK/ TDLUDR 6 TDLINT 6 RDLSIG/ RDLCLK/ RDLEOM 9 RDLINT 9 INTB 7 RMFP RODAT ROCLK ROHCLK RDLCLK/ RDLSIG/ ...
Page 150
... ISSUE 5 (Clears BYP[7:1]) (Sets REXHDLC and TEXHDLC) (Sets REOMPOL,TUDRPOL,RINTPOL, TINTPOL). (Clears LINEAIS[1:0], LLBE and DLBE.) (Sets TRISE. Clears TINV, TUNI, RINV, RFALL.) (Sets IOTST to put device into test mode.) (Clears DS3 FRMR UNI bit.) 140 PM8313 D3MX M13 MULTIPLEXER ...
Page 151
... EOM bit in the XFDL Configuration Register to logic 1, and set the INTE bit to logic 0. Alternatively, assert the TDLEOMI input. 4. Read the Status Register and check the UDR bit. ISSUE 5 141 PM8313 D3MX M13 MULTIPLEXER ...
Page 152
... The first interrupt and data byte read after the RFDL is enabled (or TR bit set to logic indication of the link status, and the data byte should therefore be discarded the controlling processor to keep track of the ISSUE 5 142 PM8313 D3MX M13 MULTIPLEXER ...
Page 153
... If FE=0, then go to step 1, else wait for the next interrupt. The interrupt service routine can optionally read the Status Register first to check for an overrun condition, and then for available data, before advancing to step one above. ISSUE 5 143 PM8313 D3MX M13 MULTIPLEXER ...
Page 154
... The DMA controller is inhibited from reading any more bytes, and the processor is interrupted. The processor can then halt the DMA controller, read the Status Register, process the frame, and finally reset the DMA controller to process the data for the next frame. ISSUE 5 144 PM8313 D3MX M13 MULTIPLEXER ...
Page 155
... CRC-CCITT information B1, B2 groupings of 8 bits ISSUE Address (high) (low) CONTROL Frame Check Sequence (FCS 145 PM8313 D3MX M13 MULTIPLEXER RECEIVE 1 FLAG 0 data bytes received and transferred to the FIFO, bit 1 first 0 FLAG ...
Page 156
... EOMR and FLG bits, and set the RDLEOM output low. The FIFO buffer is not cleared when an abort is detected. All bytes received up to the abort are available to be read. ISSUE Dn-3 Dn-2 146 PM8313 D3MX M13 MULTIPLEXER Flag D1 R Abort Dn EOM ...
Page 157
... RFDL is still held disabled when it occurs. Consequently, the RFDL will ignore the entire frame including the abort sequence (since it has not occurred in a valid frame or during flag reception, according to the RFDL). ISSUE 147 PM8313 D3MX M13 MULTIPLEXER Flag D1 R Abort STATUSRD OVR ...
Page 158
... Whenever new data is ready, the TDLINT signal can be re-enabled by setting the INTE bit in the Configuration/Control Register to logic 1, and the cycle starts again. ISSUE EOM INTE 148 PM8313 D3MX M13 MULTIPLEXER Flag D1 CRC1 CRC2 INTE ...
Page 159
... TDLINT interrupt should also be disabled at this time by setting the INTE bit in the Configuration/Control Register to logic 0. The data frame can then be restarted as usual, by setting the INTE bit logic to 1. Transmission of the frame then proceeds normally. ISSUE Abort D3 UDR INTE INTE 149 PM8313 D3MX M13 MULTIPLEXER Flag ...
Page 160
... DATA SHEET PMC-920702 13 FUNCTIONAL TIMING Figure 11 - Receive DS3 High Speed Output Timing ROCLK RODAT INFO INFO INFO RMFP RMSFP ROHP ISSUE 5 INFO X1 BIT INFO INFO 150 PM8313 D3MX M13 MULTIPLEXER INFO C BIT INFO INFO X2 BIT BIT OR F BIT ...
Page 161
... DATA SHEET PMC-920702 Figure 12 - Receive DS3 Low Speed Timing ISSUE 5 151 PM8313 D3MX M13 MULTIPLEXER ...
Page 162
... DATA SHEET PMC-920702 Figure 13 - Transmit DS3 Timing ISSUE 5 152 PM8313 D3MX M13 MULTIPLEXER ...
Page 163
... The underrun will be indicated on the TDLUDR output and in the UDR status bit within the XFDL Interrupt Status register. ISSUE 5 min. 216 µs max. 311 µs Write of a byte of packet. 153 PM8313 D3MX M13 MULTIPLEXER min. 216 µs max. 311 µs Write of next byte has not occurred ...
Page 164
... XFDL TSB is awaiting the first byte of a new packet, an underrun condition cannot occur. Once the first byte is written, however, the ISSUE 5 Last byte + FCS transmission 850 µs Assertion suppressed by TDLEOMI < 846 µs 154 PM8313 D3MX M13 MULTIPLEXER FLAG transmission Write of 1st byte of next packet. ...
Page 165
... Once the first byte is written, however, the XFDL must be serviced within 210µs of each TDLINT assertion, otherwise an underrun condition occurs (see Figure 10). ISSUE 5 Last byte + FCS transmission 850 µs Assertion suppressed by TDLEOMI 155 PM8313 D3MX M13 MULTIPLEXER FLAG transmission Write of 1st byte of next packet. > ...
Page 166
... 156 PM8313 D3MX M13 MULTIPLEXER don't care bit Block ...
Page 167
... 157 PM8313 D3MX M13 MULTIPLEXER ...
Page 168
... Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature ISSUE 5 -40°C to +85°C -40°C to +125°C -0.5V to +6.0V -0. ±500 V ±100 mA ±20 mA +300°C +150°C 158 PM8313 D3MX M13 MULTIPLEXER +0.5V DD ...
Page 169
... Typ Max -0.5 0.8 2 +0.5 0.4 2.4 3.5 1.0 1.0 +200 µA -10 +10 -10 +10 159 PM8313 D3MX M13 MULTIPLEXER Units Conditions Volts Guaranteed Input LOW Voltage Volts Guaranteed Input HIGH Voltage Volts V = min for Data Bus Pins and high speed transmit outputs and 2 mA for all others, ...
Page 170
... Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). ISSUE 5 Min Typ Max -10 + 160 PM8313 D3MX M13 MULTIPLEXER Units Conditions µA VIH = VDD, Notes Excluding Package, Package Typically Excluding Package, Package Typically ...
Page 171
... Latch to Read Hold LR tP Valid Read to Valid Data Propagation RD Delay tZ Valid Read Deasserted to Output Tri- RD state tP Valid Read Deasserted to INTB Tri- INTH state ISSUE ±10%) DD 161 PM8313 D3MX M13 MULTIPLEXER Min Max Units ...
Page 172
... A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. Microprocessor timing applies to normal mode register accesses only. ISSUE Valid Address tS ALR 162 PM8313 D3MX M13 MULTIPLEXER ALR INTH tZ RD Valid Data ...
Page 173
... Address to Valid Write Hold Time AW tV Valid Write Pulse Width WR ISSUE and tS ALR and tS are not applicable if address latching is used. AR 163 PM8313 D3MX M13 MULTIPLEXER are not applicable. Min Max Units ...
Page 174
... Volt point of the input to the 1.4 Volt point of the clock. ISSUE 5 Valid Address tS tH ALW Valid Data , and tS ALW and tS are not applicable if address latching is used. AW 164 PM8313 D3MX M13 MULTIPLEXER ALW are not applicable. ...
Page 175
... DATA SHEET PMC-920702 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. ISSUE 5 165 PM8313 D3MX M13 MULTIPLEXER ...
Page 176
... RPOS tS RNEG/RLCV Set-Up Time RNEG tH RNEG/RLCV Hold Time RNEG Figure 21 - Receive DS3 Input Timing RCLK RPOS/RDAT RNEG/RCLV ISSUE ±10 RPOS tS tH RNEG 166 PM8313 D3MX M13 MULTIPLEXER Min Max Units -20 +20 ppm RPOS RNEG ...
Page 177
... Description TICLK Frequency (nominally 44.736 MHz ) TICLK Duty Cycle tS TIMFP Set-up Time TIMFP tH TIMFP Hold Time TIMFP Figure 22 - Transmit DS3 Input Timing TICLK TIMFP ISSUE TIMFP TIMFP 167 PM8313 D3MX M13 MULTIPLEXER Min Max Units -20 +20 ppm ...
Page 178
... TOH Set-up Time TOH tH TOH Hold Time TOH tS TOHEN Set-up Time TOHEN tH TOHEN Hold Time TOHEN Figure 23 - Transmit Overhead Input Timing TOHCLK TOH TOHEN ISSUE TOH tS tH TOHEN TOHEN 168 PM8313 D3MX M13 MULTIPLEXER Min Max Units TOH ...
Page 179
... TD2CLK Duty Cycle tS TD1DAT Set-up Time TD1DAT tH TD1DAT Hold Time TD1DAT Figure 24 - Transmit Tributary Input Timing TD1CLK TD1DAT ISSUE TD1DAT TD1DAT 169 PM8313 D3MX M13 MULTIPLEXER Min Max Units -130 +130 ppm -50 +50 ppm -33 +33 ppm -33 +33 ppm ...
Page 180
... Table 13 - D3MX Transmit Data Link Input (Figure 25) Symbol Description tS TDLSIG TDLSIG to TDLCLK Set-up Time tH TDLSIG TDLSIG to TDLCLK Hold Time Figure 25 - Transmit Data Link Input Timing TDLCLK TDLSIG ISSUE TDLSIG TDLSIG 170 PM8313 D3MX M13 MULTIPLEXER Min Max Units ...
Page 181
... When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. ISSUE tS1 TEOMI tS3 TEOMI 171 PM8313 D3MX M13 MULTIPLEXER Min Max Units 210 µ ...
Page 182
... TCLK Duty Cycle tP TPOS TCLK Low to TPOS/TDAT Valid Prop. Delay tP TNEG TCLK Low to TNEG/TMFP Valid Prop. Delay Figure 27 - Transmit DS3 Output Timing TCLK TPOS/TDAT TNEG/TMFP ISSUE 5 tP TPOS tP TNEG 172 PM8313 D3MX M13 MULTIPLEXER Min Max Units TICLK- TICLK % ...
Page 183
... RMFP ROCLK Low to RMFP Valid Propagation Delay tP RMSFP ROCLK Low to RMSFP Valid Prop. Delay tP ROHP ROCLK Low to ROHP Valid Propagation Delay tP RLOS ROCLK Low to RLOS Valid Propagation Delay ISSUE 5 173 PM8313 D3MX M13 MULTIPLEXER Min Max Units - ...
Page 184
... DATA SHEET PMC-920702 Figure 28 - Receive DS3 Output Timing ROCLK RODAT RMFP RMSFP ROHP RLOS ISSUE 5 tP RODAT tP RMFP tP RMSFP tP ROHP tP RLOS 174 PM8313 D3MX M13 MULTIPLEXER ...
Page 185
... ROHFP ROHCLK Low to ROHFP Valid Prop. Delay tP RAIS ROHCLK Low to RAIS Valid Propagation Delay tP ROOF ROHCLK Low to ROOF Valid Prop. Delay tP RFERF ROHCLK Low to RFERF Valid Prop. Delay ISSUE 5 175 PM8313 D3MX M13 MULTIPLEXER Min Max Units - ...
Page 186
... Receive Overhead Output Timing ROHCLK ROH ROHFP RAIS ROOF/RRED RFERF Table 18 - D3MX Transmit Overhead Output (Figure 30) Symbol Description tP TOHFP TOHCLK Low to TOHFP Valid Prop. Delay ISSUE 5 tP ROH tP ROHFP tP RAIS tP ROOF tP RFERF 176 PM8313 D3MX M13 MULTIPLEXER Min Max Units - ...
Page 187
... Delay Figure 31 - Receive Tributary Output Timing RD1CLK RD1DAT Table 20 - D3MX Receive Data Link Output (Figure 32) Symbol Description tP RDLSIG RDLCLK Low to RDLSIG Valid Prop. Delay ISSUE 5 tP TOHFP tP RD1DAT 177 PM8313 D3MX M13 MULTIPLEXER Min Max Units - Min Max Units - ...
Page 188
... Volt point of the output. 2. Maximum output propagation delays are measured with load on the high-speed DS3 outputs (TCLK, TPOS/TDAT, TNEG/TMFP , ROCLK, RODAT, RMFP , RMSFP , and ROHP) and load on the remaining outputs. ISSUE 5 tP RDLSIG 178 PM8313 D3MX M13 MULTIPLEXER ...
Page 189
... ORDERING AND THERMAL INFORMATION Table 21 - D3MX Ordering Information PART NO. DESCRIPTION PM8313-RI 208 Pin Copper Leadframe Plastic Quad Flat Pack Table 22 - D3MX Thermal Information PART NO. AMBIENT TEMPERATURE PM8313-RI -40°C to 85°C ISSUE 5 179 PM8313 D3MX M13 MULTIPLEXER Theta Ja Theta Jc 50 °C/W 15 °C/W ...
Page 190
... Pin 1 Designator STANDOFF A1 0-7 DEG b LEAD COPLANARITY DETAIL 3.39 30.40 27.90 30.40 27.90 3.49 30.60 28.00 30.60 28.00 3.59 30.80 28.10 30.80 28.10 180 PM8313 D3MX M13 MULTIPLEXER A 8-12 DEG. 8-12 DEG. A2 NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE. C ccc ccc L 0.17 0.50 0.60 0.50 0.22 0.75 0.27 0.10 ...
Page 191
... DATA SHEET PMC-920702 NOTES ISSUE 5 181 PM8313 D3MX M13 MULTIPLEXER ...
Page 192
... PMC-Sierra, Inc. has been advised of the possibility of such damage. © 1998PMC-Sierra, Inc. PMC-920702 (R5) ref 911105 (R13) PMC-Sierra, Inc. ISSUE 5 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com Issue date: July 1998 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 PM8313 D3MX M13 MULTIPLEXER ...