XPC862PZP100B Freescale Semiconductor, Inc, XPC862PZP100B Datasheet

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XPC862PZP100B

Manufacturer Part Number
XPC862PZP100B
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor
Technical Data
MPC862/857T/857DSL
PowerQUICC™ Family
Hardware Specifications
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC862/857T/857DSL family
(refer to
contains a PowerPC™ core processor, is the superset device
of the MPC862/857T/857DSL family. For functional
characteristics of the processor, refer to the MPC862
PowerQUICC™ Family Users Manual (MPC862UM/D).
© Freescale Semiconductor, Inc., 2006. All rights reserved.
Table 1
for a list of devices). The MPC862P, which
10. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 44
11. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 46
12. UTOPIA AC Electrical Specifications . . . . . . . . . . . 68
13. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 69
14. Mechanical Data and Ordering Information . . . . . . . 72
15. Document Revision History . . . . . . . . . . . . . . . . . . . 86
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 8
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 10
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7. Thermal Calculation and Measurement . . . . . . . . . . 12
8. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Document Number: MPC862EC
Contents
Rev. 3, 2/2006

Related parts for XPC862PZP100B

XPC862PZP100B Summary of contents

Page 1

... The MPC862P, which contains a PowerPC™ core processor, is the superset device of the MPC862/857T/857DSL family. For functional characteristics of the processor, refer to the MPC862 PowerQUICC™ Family Users Manual (MPC862UM/D). © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: MPC862EC Rev. 3, 2/2006 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...

Page 2

Overview 1 Overview The MPC862/857T/857DSL is a derivative of Freescale’s MPC860 PowerQUICC™ family of devices versatile single-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications and communications and networking systems. ...

Page 3

The MPC862/857T/857DSL provides enhanced ATM functionality over that of the MPC860SAR. The MPC862/857T/857DSL adds major new features available in “enhanced SAR” (ESAR) mode, including the following: — Improved operation, administration and maintenance (OAM) support — OAM performance monitoring (PM) ...

Page 4

Features • System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer — Decrementer, time base, and real-time clock (RTC) from the PowerPC architecture — Reset controller — ...

Page 5

Universal asynchronous receiver transmitter (UART) — Synchronous UART — Serial infrared (IrDA) — Binary synchronous communication (BISYNC) — Totally transparent (bit streams) — Totally transparent (frame based with optional cyclic redundancy check (CRC)) • Two SMCs (serial management channels) ...

Page 6

Features — Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast wake up — Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer. — Power down mode— All units powered ...

Page 7

Instruction Bus Embedded MPC8xx Processor Load/Store Core Bus Fast Ethernet Controller DMAs FIFOs 10/100 Base-T Media Access Control Parallel Interface Port MII *The MPC862T contains 4-Kbyte instruction cache and 4-Kbyte data cache. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale ...

Page 8

Maximum Tolerated Ratings Instruction Bus Embedded MPC8xx Processor Load/Store Core Bus Fast Ethernet Controller DMAs FIFOs 10/100 Base-T Media Access Control Parallel Interface Port MII *The MPC857DSL does not contain SMC2 nor the Time Slot Assigner, and provides eight SDMA ...

Page 9

Table 2. Maximum Tolerated Ratings (continued) Rating 2 Input voltage 3 4 Temperature (standard) 3 Temperature (extended) Storage temperature range 1 The power supply of the device must start its ramp from 0 Functional operating conditions are provided ...

Page 10

Thermal Characteristics 4 Thermal Characteristics Table 3 shows the thermal characteristics for the MPC862/857T/857DSL. Table 3. MPC862/857T/857DSL Thermal Resistance Data Rating 1 Junction to ambient Natural Convection Air flow (200 ft/min) 4 Junction to board 5 Junction to case 6 ...

Page 11

Die Revision A.1, B.0 (2:1 Mode) B.0 (2:1 Mode) 1 Typical power dissipation is measured at 3 Maximum power dissipation is measured at 3.5 V. Values in Table 4 power dissipation over VDDH. I/O power dissipation varies widely ...

Page 12

Thermal Calculation and Measurement Table 5. DC Electrical Specifications (continued) Characteristic Output Low Voltage IOL = 2.0 mA (CLKOUT) 3 IOL = 3 IOL = 5.3 mA IOL = 7.0 mA (TXD1/PA14, TXD2/PA12) IOL = 8.9 mA (TS, ...

Page 13

Estimation with Junction-to-Case Thermal Resistance Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θJA θJC θCA where junction-to-ambient thermal ...

Page 14

Thermal Calculation and Measurement If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation +(R ) θ where ...

Page 15

References Semiconductor Equipment and Materials International 805 East Middlefield Rd. Mountain View, CA 94043 MIL-SPEC and EIA/JESD (JEDEC) Specifications (Available from Global Engineering Documents) JEDEC Specifications 1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA ...

Page 16

Bus Signal Timing Table 7 provides the bus operation timing for the MPC862/857T/857DSL at 33 MHz, 40 Mhz, 50 MHz and 66 Mhz. The timing for the MPC862/857T/857DSL bus shown assumes a 50-pF load for maximum delays and a 0-pF ...

Page 17

Num Characteristic B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3) BDIP, PTR valid (MAX = 0. 6.3) B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), 4 STS Valid (MAX = 0. 6.3) B9 ...

Page 18

Bus Signal Timing Num Characteristic B17a CLKOUT to KR, RETRY, CR valid (hold time) (MIN = 0. 2.00) B18 D(0:31), DP(0:3) valid to CLKOUT 8 rising edge (setup time 6.00) B19 CLKOUT rising edge ...

Page 19

Num Characteristic B27 A(0:31) and BADDR(28:30 asserted GPCM ACS = 10, TRLX = 1 (MIN = 1. 2.00) B27a A(0:31) and BADDR(28:30 asserted GPCM ACS = 11, TRLX = 1 (MIN = 1.50 ...

Page 20

Bus Signal Timing Num Characteristic B29d WE(0:3) negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 1, CSNT = 1, EBDF = 0 (MIN = 1. 2.00) B29e CS negated to D(0:31), DP(0:3) High-Z GPCM write ...

Page 21

Num Characteristic B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid GPCM write access, TRLX = 0, CSNT = 1. CS negated to A(0:31) invalid GPCM write access, TRLX = 0, CSNT = 1 ACS = 10, ACS == 11, EBDF = ...

Page 22

Bus Signal Timing Num Characteristic B32c CLKOUT rising edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM (MAX = 0. 6.80) B32d CLKOUT falling edge to BS valid- ...

Page 23

Num Characteristic B37 UPWAIT valid to CLKOUT falling edge 12 (MIN = 0. 6.00) B38 CLKOUT falling edge to UPWAIT valid 12 (MIN = 0. 1.00) B39 AS valid to CLKOUT rising edge (MIN ...

Page 24

Bus Signal Timing Figure 4 is the control timing diagram. 2.0 V CLKOUT B Outputs Outputs Inputs Inputs Legend: A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time ...

Page 25

Figure 6 provides the timing for the synchronous output signals. CLKOUT B7 Output Signals B7a Output Signals B7b Output Signals Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. ...

Page 26

Bus Signal Timing Figure 8 provides the timing for the synchronous input signals. CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also ...

Page 27

Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) ...

Page 28

Bus Signal Timing CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ...

Page 29

CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B12 B8 B22a B27 B27a B22b B22c B18 ACS = 10, ACS = ...

Page 30

Bus Signal Timing Figure 15 through Figure 17 provide the timing for the external bus write controlled by various GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0,1 CSNT ...

Page 31

CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0,1 CSNT = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c ...

Page 32

Bus Signal Timing CLKOUT B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0,1, CSNT = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B12 B8 B22 B28b B28d B25 B26 ...

Page 33

Figure 18 provides the timing for the external bus controlled by the UPM. CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B8 B31a B31d ...

Page 34

Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Figure 20 provides the timing ...

Page 35

Figure 21 provides the timing for the synchronous external master access controlled by the GPCM. CLKOUT TS A[0:31], TSIZ[0:1], R/W, BURST CSx Figure 21. Synchronous External Master Access Timing Figure 22 provides the timing for the asynchronous external master memory ...

Page 36

Bus Signal Timing Table 8 provides interrupt timing for the MPC862/857T/857DSL. Num I39 IRQx valid to CLKOUT rising edge (set up time) I40 IRQx hold time after CLKOUT I41 IRQx pulse width low I42 IRQx pulse width high I43 IRQx ...

Page 37

Table 9 shows the PCMCIA timing for the MPC862/857T/857DSL. Num Characteristic A(0:31), REG valid to PCMCIA 1 P44 Strobe asserted. (MIN = 0. 2.00) A(0:31), REG valid to ALE 1 P45 negation. (MIN = 1. ...

Page 38

Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. ...

Page 39

Figure 27 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IOWR ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. ...

Page 40

Bus Signal Timing Table 10 shows the PCMCIA port timing for the MPC862/857T/857DSL. Num Characteristic CLKOUT to OPx Valid (MAX = 0.00 x P57 B1 + 19.00) HRESET negated to OPx drive P58 (MIN = 0. 3.00) ...

Page 41

Table 11 shows the debug port timing for the MPC862/857T/857DSL. Num Characteristic D61 DSCK cycle time D62 DSCK clock pulse width D63 DSCK rise and fall times D64 DSDI input data setup time D65 DSDI data hold time D66 DSCK ...

Page 42

Bus Signal Timing Table 12 shows the reset timing for the MPC862/857T/857DSL. Num Characteristic CLKOUT to HRESET high impedance R69 (MAX = 0. 20.00) CLKOUT to SRESET high impedance R70 (MAX = 0. 20.00) ...

Page 43

Figure 33 shows the reset timing for the data bus configuration. HRESET RSTCONF D[0:31] (IN) Figure 33. Reset Timing—Configuration from Data Bus Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF D[0:31] ...

Page 44

IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. CLKOUT SRESET DSCK, DSDI Figure 35. Reset Timing—Debug Port Configuration 10 IEEE 1149.1 Electrical Specifications Table 13 provides the JTAG timings for the MPC862/857T/857DSL shown ...

Page 45

TCK TCK TMS, TDI TDO Figure 37. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor J82 J83 ...

Page 46

CPM Electrical Characteristics 11 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC862/857T/857DSL. 11.1 PIP/PIO AC Electrical Specifications Table 14 provides the PIP/PIO AC timings as shown in ...

Page 47

DATA-OUT STBO (Output) STBI (Input) Figure 41. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 42. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 43. PIP TX (Pulse Mode) Timing Diagram MPC862/857T/857DSL ...

Page 48

CPM Electrical Characteristics CLKO DATA-IN DATA-OUT Figure 44. Parallel I/O Data-In/Data-Out Timing Diagram 11.2 Port C Interrupt AC Electrical Specifications Table 15 provides the timings for port C interrupts. Num 35 Port C interrupt pulse width low (edge-triggered mode) 36 ...

Page 49

Table 16. IDMA Controller Timing (continued) Num 43 SDACK negation delay from clock low 44 SDACK negation delay from TA low 45 SDACK negation delay from clock high 46 TA assertion to falling edge of the clock setup time (applies ...

Page 50

CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 48. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 49. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC862/857T/857DSL ...

Page 51

Baud Rate Generator AC Electrical Specifications Table 17 provides the baud rate generator timings as shown in Num 50 BRGO rise and fall time 51 BRGO duty cycle 52 BRGO cycle BRGOX Figure 50. Baud Rate Generator Timing Diagram ...

Page 52

CPM Electrical Characteristics CLKO 61 TIN/TGATE (Input) TOUT (Output) Figure 51. CPM General-Purpose Timers Timing Diagram 11.6 Serial Interface AC Electrical Specifications Table 19 provides the serial interface timings as shown in Num 70 L1RCLK, L1TCLK frequency (DSC = 0) ...

Page 53

Num 83a L1RCLK, L1TCLK width high (DSC = 1) 84 L1CLK edge to L1CLKO valid (DSC = 1) 85 L1RQ valid before falling edge of L1TSYNC 2 86 L1GR setup time 87 L1GR hold time 88 L1CLK edge to L1SYNC ...

Page 54

CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 53. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, ...

Page 55

L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 54. SI Transmit Timing Diagram (DSC = 0) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 70 72 TFSD 80a ...

Page 56

CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 55. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC862/857T/857DSL PowerQUICC™ ...

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MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 56. IDL Timing CPM Electrical Characteristics 57 ...

Page 58

CPM Electrical Characteristics 11.7 SCC in NMSI Mode Electrical Specifications Table 20 provides the NMSI external clock timing. Num 100 RCLK1 and TCLK1 width high 101 RCLK1 and TCLK1 width low 102 RCLK1 and TCLK1 rise/fall time 103 TXD1 active ...

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Figure 57 through Figure 59 show the NMSI timings. RCLK1 102 106 RxD1 (Input) CD1 (Input) CD1 (SYNC Input) Figure 57. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 58. SCC ...

Page 60

CPM Electrical Characteristics TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Echo Input) 11.8 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Num 120 CLSN width high 121 RCLK1 rise/fall time 122 RCLK1 width low 1 123 ...

Page 61

Num 134 TENA inactive delay (from TCLK1 rising edge) 135 RSTRT active delay (from TCLK1 falling edge) 136 RSTRT inactive delay (from TCLK1 falling edge) 137 REJECT width low 138 CLKO1 low to SDACK asserted 139 CLKO1 low to SDACK ...

Page 62

CPM Electrical Characteristics TCLK1 128 131 TxD1 (Output) 133 TENA(RTS1) (Input) RENA(CD1) (Input) (NOTE 2) NOTES: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all ...

Page 63

SMC Transparent AC Electrical Specifications Table 23 provides the SMC transparent timings as shown in Num 1 150 SMCLK clock period 151 SMCLK width low 151A SMCLK width high 152 SMCLK rise/fall time 153 SMTXD active delay (from SMCLK ...

Page 64

CPM Electrical Characteristics 11.10 SPI Master AC Electrical Specifications Table 24 provides the SPI master timings as shown in Num 160 MASTER cycle time 161 MASTER clock (SCK) high or low time 162 MASTER data setup time (inputs) 163 Master ...

Page 65

SPICLK (CI=0) (Output) 161 161 SPICLK (CI=1) (Output) 163 162 SPIMISO msb (Input) 167 SPIMOSI (Output) Figure 67. SPI Master ( Timing Diagram 11.11 SPI Slave AC Electrical Specifications Table 25 provides the SPI slave timings as shown ...

Page 66

CPM Electrical Characteristics SPISEL (Input) SPICLK (CI=0) (Input) 173 173 SPICLK (CI=1) (Input) 177 SPIMISO msb (Output) 175 176 SPIMOSI msb (Input) Figure 68. SPI Slave ( Timing Diagram SPISEL (Input) 171 SPICLK (CI=0) (Input) 173 173 SPICLK ...

Page 67

Electrical Specifications 2 Table 26 provides the I C (SCL < 100 KHz) timings. Num 200 SCL clock frequency (slave) 200 SCL clock frequency (master) 202 Bus free time between transmissions 203 Low period of ...

Page 68

UTOPIA AC Electrical Specifications 2 Figure 70 shows the I C bus timing. SDA 202 203 205 SCL 206 12 UTOPIA AC Electrical Specifications Table 28 shows the AC electrical specifications for the UTOPIA interface. Table 28. UTOPIA AC Electrical ...

Page 69

Figure 71 shows signal timings during UTOPIA receive operations. UtpClk U5 PHREQn RxClav HighZ at MPHY RxEnb UTPB SOC Figure 72 shows signal timings during UTOPIA transmit operations. UtpClk U5 5 PHSELn TxClav HighZ at MPHY TxEnb UTPB SOC 13 ...

Page 70

FEC Electrical Characteristics 13.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER, MII_RX_CLK) The receiver functions correctly MII_RX_CLK maximum frequency of 25MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the ...

Page 71

Table 30. MII Transmit Signal Timing (continued) Num M7 MII_TX_CLK pulse width high M8 MII_TX_CLK pulse width low Figure 74 shows the MII transmit signal timing diagram. MII_TX_CLK (input) MII_TXD[3:0] (outputs) MII_TX_EN MII_TX_ER Figure 74. MII Transmit Signal Timing Diagram ...

Page 72

Mechanical Data and Ordering Information Table 32. MII Serial Management Channel Timing Num M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation delay) M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) M12 MII_MDIO (input) to MII_MDC ...

Page 73

... Frequency (MHz) 0°C to 105° 100 -40°C to 115°C 66 Mechanical Data and Ordering Information Cache Size Instruction Data Yes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes Order Number XPC862PZP50B XPC862TZP50B XPC857TZP50B XPC857DSLZP50B XPC862PZP66B XPC862TZP66B XPC857TZP66B XPC857DSLZP66B XPC862PZP80B XPC862TZP80B XPC857TZP80B XPC862PZP100B XPC862TZP100B XPC857TZP100B 1 XPC862PCZP66B XPC857TCZP66B 73 ...

Page 74

Mechanical Data and Ordering Information NOTE: This is the top view of the device. PD10 PD8 PD3 IRQ7 PD14 PD13 PD9 PD6 M_Tx_EN PA0 PB14 PD15 PD4 PD5 PA1 PC5 PC4 PD11 PD7 PC6 PA2 PB15 PD12 PA4 PB17 PA3 ...

Page 75

Table 35 contains a list of the MPC862 input and output signals and shows multiplexing and pin assignments. Name A[0:31] B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15, C14, B14, A14, D12, C13, B13, D9, D11, ...

Page 76

Mechanical Data and Ordering Information Name FRZ G3 IRQ6 IRQ0 V14 IRQ1 U14 M_TX_CLK W15 IRQ7 CS[0:5] C3, A2, D4, E4, A4, B4 CS6 D5 CE1_B CS7 C4 CE2_B WE0 C7 BS_B0 IORD WE1 ...

Page 77

Name GPL_A5 D3 PORESET R2 RSTCONF P3 HRESET N4 SRESET P2 XTAL P1 EXTAL N1 XFC T2 CLKOUT W3 EXTCLK N2 TEXP N3 ALE_A K2 MII-TXD1 CE1_A B3 MII-TXD2 CE2_A A3 MII-TXD3 WAIT_A R3 2 SOC_Split WAIT_B R4 IP_A0 T5 ...

Page 78

Mechanical Data and Ordering Information Name IP_A6 T6 2 UTPB_Split6 MII-TXERR IP_A7 T3 2 UTPB_Split7 MII-RXDV ALE_B J1 DSCK/AT1 IP_B[0:1] H2, J3 IWP[0:1] VFLS[0:1] IP_B2 J2 IOIS16_B AT2 IP_B3 G1 IWP2 VF2 IP_B4 G2 LWP0 VF0 IP_B5 J4 LWP1 VF1 ...

Page 79

Name PA15 C18 RXD1 RXD4 PA14 D17 TXD1 TXD4 PA13 E17 RXD2 PA12 F17 TXD2 PA11 G16 L1TXDB RXD3 PA10 J17 L1RXDB TXD3 PA9 K18 L1TXDA RXD4 PA8 L17 L1RXDA TXD4 PA7 M19 CLK1 L1RCLKA BRGO1 TIN1 PA6 M17 CLK2 ...

Page 80

Mechanical Data and Ordering Information Name PA2 R18 CLK6 TOUT3 L1RCLKB PA1 T19 CLK7 BRGO4 TIN4 PA0 U19 CLK8 TOUT4 L1TCLKB PB31 C17 SPISEL REJECT1 PB30 C19 SPICLK RSTRT2 PB29 E16 SPIMOSI PB28 D19 SPIMISO BRGO4 PB27 E19 I2CSDA BRGO1 ...

Page 81

Name PB21 K16 SMTXD2 L1CLKOB 1 PHSEL1 2 TXADDR1 PB20 L16 SMRXD2 L1CLKOA 1 PHSEL0 2 TXADDR0 PB19 N19 RTS1 L1ST1 PB18 N17 2 RXADDR4 RTS2 L1ST2 PB17 P18 L1RQb L1ST3 RTS3 1 PHREQ1 2 RXADDR1 PB16 N16 L1RQa L1ST4 ...

Page 82

Mechanical Data and Ordering Information Name PC13 E18 L1RQb L1ST3 RTS3 PC12 F18 L1RQa L1ST4 RTS4 PC11 J19 CTS1 PC10 K19 CD1 TGATE1 PC9 L18 CTS2 PC8 M18 CD2 TGATE2 PC7 M16 CTS3 L1TSYNCB SDACK2 PC6 R19 CD3 L1RSYNCB PC5 ...

Page 83

Name PD12 R16 L1RSYNCB MII-MDC UTPB3 PD11 T16 RXD3 MII-TXERR RXENB PD10 W18 TXD3 MII-RXD0 TXENB PD9 V17 RXD4 MII-TXD0 UTPCLK PD8 W17 TXD4 MII-MDC MII-RXCLK PD7 T15 RTS3 MII-RXERR UTPB4 PD6 V16 RTS4 MII-RXDV UTPB5 PD5 U15 REJECT2 MII-TXD3 ...

Page 84

Mechanical Data and Ordering Information Name TRST G19 TDO G17 DSDO M_CRS B7 M_MDIO H18 M_TXEN V15 M_COL H4 KAPWR R1 GND F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10, G11, G12, G13, G14, ...

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TOP VIEW ...

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Document Revision History 15 Document Revision History Table 36 lists significant changes between revisions of this document. Rev. No. Date 0 2001 Initial revision 0.1 9/2001 Change extended temperature from 95 to 105 0.2 11/2001 Revised for new template, changed ...

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THIS PAGE INTENTIONALLY LEFT BLANK MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Document Revision History 87 ...

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