GS1515 Gennum Corporation, GS1515 Datasheet
GS1515
Specifications of GS1515
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GS1515 Summary of contents
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... Serial Digital outputs are muted and the Jitter Demodulator Function (DM) helps to debug systems and locate the source of jitter. The GS1515 is packaged pin MQFP package and requires a single 5V power supply. The GS1515 typically draws 100mA of current. ...
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ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range Input ESD Voltage Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) DC ELECTRICAL CHARACTERISTICS V = +5V 0°C to 70°C unless otherwise specified CC A PARAMETER ...
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AC ELECTRICAL CHARACTERISTICS ° °C unless otherwise specified CC A PARAMETER SYMBOL Serial Input Data Rate Serial Input Jitter Tolerance PLL Lock Time - Asynchronous t ALOCK PLL Lock Time - ...
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... NC 11 LFA 522 - CONDITIONS MIN Loop Bandwidth approximately 1.41MHz at 0.2UI input jitter modulation Loop Bandwidth approximately 129kHz at 0.2UI input jitter modulation 10nF PLCAP GS1515 TOP VIEW TYP MAX UNITS - 0. 0.05 - ...
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PIN DESCRIPTIONS NUMBER SYMBOL 10, NC 24, 25, 27, 29, 31, 33, 34, 36 LFS 5 LFA_V EE 8 LFA_V CC 11 LFA 12 DFT_V EE 13, 14 PLCAP, PLCAP 15, 18, ...
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INPUT / OUTPUT CIRCUITS PD_V CC 5k 20k PD_V EE DDI 50 DDI_V TT Fig. 1 DDI/DDI Input PD_V CC 5k 10k PD_V EE 50 VCO Fig. 2 VCO/VCO Input PD_V 10k 10k DM 85µA DFT_V EE Fig. 3 DM/DM ...
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... H/P E4422B gigaBERT-1400 CLOCK GENERATOR 1.485 GHz SIGNAL SPECIALLY GENERATOR MODIFIED FOR HDTV Fig. 12 Intrinsic Jitter Measurement Set-Up LFA_V CC 100µA LFA_V EE BYPASS EB1515 OUT (GS1515) RECLOCKER BOARD CLOCK SDO SDO + - CD_V R EE SET Fig. 10 SDO/SDO Output PD_V CC 16k + V=2.4V - 100µA ...
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... HD-LINX™ products such as the GS1504 Adaptive Cable Equalizer. PHASE DETECTOR The phase detector portion of the slew PLL used in GS1515 is a bi-level digital phase detector. It indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. When the phase detector is locked, the data transition edges are aligned to the falling edge of the clock ...
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... Typical Application P F Circuit) can reduce the loop bandwidth of the GS1515. The parallel combination of the resistor is directly proportional to the bandwidth factor. For example, the on-chip 500Ω resistor yields 282.9kHzUI 50Ω resistor is connected in parallel, the effective resistance will be (50 || 500) 45.45Ω. ...
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... An accurate jitter peaking measurement of 0.1dB for the GS1515 requires the modulation source to have a constant amount of jitter modulation index (within 0.1dB or 1.2%) over the frequency range beyond the loop bandwidth. It has been determined that for 282.9kHzUI, the minimum ...
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PHASE LOCK The phase lock circuit is used to determine the phase locked condition done by generating a quadrature clock by delaying the in-phase clock (the clock whose falling edge is aligned to the data transition) by 166ps ...
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... Also, in the bypass mode, the internal PLL still locks to a valid HDTV signal and would show PLL_LOCK. CABLE DRIVER The output of the GS1515 is a dual/complimentary current mode cable driver stage. The output swing and impedance can be varied. The following table may be used to select the R resistor for the desired line impedance ...
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... DM/DM signal. Figure 23 shows an example of such a situation. An HDTV SDI signal is modulated with a modulation signal causing about 0.2UI jitter in Figure 23 (Channel 1). The GS1515 receives this signal and locks to it. Figure 23 (Channel 2) shows the DM signal. Notice the wave shape of the DM signal, which is synchronous to the modulating signal. The DM/DM signal could also be used to compare the output jitter of the HDTV signal source ...
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... GO1515 The figure above shows the recommended application circuit for the GS1515. The external VCO is the GO1515 and is specifically designed to be used with the GS1515. Figures 24 through 28 show an example PC board layout of the GS1515 IC and the GO1515 VCO. This application board layout does not reflect every detail of the typical application circuit but is used as a general guide to the location of the critical parts ...
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... Unless the artwork is an exact copy of the recommended layout, every design should be verified for output return loss. Changes in the layout should be tweaked until a return loss of 25dB is attained while the GS1515 is not mounted and L is shorted. Once the device is mounted, different COMP ...
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... The position of ferrite beads for power supply noise filtering. 3. The ground under the transmission line for GS1504 and GS1515 interface. 4. The transmission line decoupling at the GS1515 end to the transmission line ground. 5. The isolation moat around the transmission line reference ground. POSSIBLE REASON Follow jitter measuring procedure as shown in Fig 12 ...
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... Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. REVISION NOTES: Added Pb-free and green information. ...