CS61575-IL1 Cirrus Logic, Inc., CS61575-IL1 Datasheet
CS61575-IL1
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CS61575-IL1 Summary of contents
Page 1
... The CS61574A has a receiver jitter attenuator optimized for minimum delay in switching and transmission applica- tions, while the CS61575 attenuator is optimized for CPE applications subject to AT&T 62411 requirements. The transmitter features internal pulse shaping and a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines ...
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... TV+, RV+ = 5.0V 5%; GND = 0V) Symbol Min (Notes 2.0 IH (Notes (Notes 4.0 OH (Notes (RV+) - 0.2 IH (Note 10 OUT CS61574A CS61575 Min Max Units - 6 (RV+) + 0.3 V (RV+) + 0 -65 150 C Typ Max Units 5.0 5. 290 350 ...
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... ABS((z +z )/( where z = impedance of the transmitter, and load 1:1.26 transformer terminated with a resistor across the secondary of a 1:1.26 transformer CS61574A CS61575 Typ Max 2.37 2.6 3.0 3.3 3.0 3.3 3.0 3.6 - 0.237 - 0 0.005 0.02 - 0.008 0.025 - 0 ...
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... TV+, RV+ = 5.0V 5%; GND = 0V) Min - -13.6 500 (Note 20) 60 (Note 21) 53 (Note 22) 45 160 (Note 23) 0.4 6.0 300 (Note 24) 0. 1.2 V and from CS61574A CS61575 Typ Max Units 50k - - - peak peak peak 175 190 bits - - ...
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... Parameter Jitter Attenuator Jitter Attenuation Curve Corner Frequency CS61574A CS61575 CS61574A T1 Receiver Jitter Transfer Jitter Freq. [Hz] 10 100 500 1k 10k, 40k CS61575 T1 Receiver Jitter Transfer Jitter Freq. [Hz] 10 100 500 1k 10k, 40k CS61574A E1 Receiver Jitter Transfer Jitter Freq. [Hz 100 400 ...
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... CS61574A CS61575 Typ Max Units 6.176000 - MHz 1.544 - MHz - 500 1.544 - MHz ...
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... Figure 2. Recovered Clock and Data Switching Characteristics DS154F2 ( TV+, RV+ = 5%; Symbol (Note 36 90% 10% Figure 1. Signal Rise and Fall Characteristics t pw1 t pwl1 t pwh1 t t su1 h1 CS61574A CS61575 Min Typ Max cdh t 240 - cl t 240 - ...
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... ACLKI Figure 3b. Alternate External Clock Characteristics t cl LSB BYTE DATA Figure 4. Serial Port Write Timing Diagram Figure 5. Serial Port Read Timing Diagram PCS t su4 t pcsl VALID INPUT DATA CS61574A CS61575 t pw3 t pwh3 t cwh t cch t cdh MSB BYTE t cdz HIGH DS154F2 ...
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... Understanding the Difference Between the CS61575 and CS61574A The CS61574A and CS61575 provide receiver jitter attenuation performance optimized for dif- ferent applications. The CS61575 is optimized to attenuate large amplitude, low frequency jitter for T1 Customer Premises Equipment (CPE) applica- tions as required by AT&T 62411. The CS61574A is optimized to minimize data delay in T1 and E1 switching or transmission applications ...
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... AIS JITTER DETECT ATTENUATOR RECEIVER HOST MODE CLKE CONTROL LINE DRIVER CS61575 DRIVER MONITOR CS61574A JITTER LINE RECEIVER ATTENUATOR Figure 7. Overview of Operating Modes CS61574A CS61575 TTIP TRANSMIT TRING TRANSFORMER MRING MTIP DPM RTIP RECEIVE RRING TRANSFORMER LEN0/1/2 TTIP TRANSMIT TRING TRANSFORMER ...
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... SCLK TAOS CLKE 0 Figure 8. Typical Pulse Shape at DSX-1 Cross Connect The CS61575 and CS61574A line drivers are de- signed to drive a 75 For E1 applications, the CS61574A and CS61575 drivers provide return loss during the transmission of both marks and spaces. This im- proves signal quality by minimizing reflections off the transmitter ...
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... LEN2/1/0=0/0/0. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61574A and CS61575 will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 ...
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... PEAK-TO-PEAK JITTER (unit intervals Figure 11. Minimum Input Jitter Tolerance of Receiver CS61574A CS61575 RPOS Jitter RNEG Attenuator RCLK Minimum Performance AT&T 62411 1 10 100 300 700 ...
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... Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 12. The CS61575 fully meets AT&T 62411 jitter attenuation requirements. The CS61574A will have a discontinuity in the jitter transfer function when the incoming jitter ampli- tude exceeds approximately 23 UIs ...
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... The CS61575 has a 192-bit FIFO which allows it to attenuate large amplitude, low frequency jitter as required by AT&T 62411 (e.g., 28 UIpp @ 300 Hz). This makes the CS61575 ideal for use in T1 Customer Premises Equipment which must be compatible with AT&T 62411 re- quirements. In single-line Stratum 4, Type II ...
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... IC monitor performance of a neigh- boring IC, rather than having it monitor its own Source of Clock for performance. Note that a CS61574A or CS61575 TTIP & TRING can not be used to monitor a CS61574 due to out- TCLK put stage differences. TCLK ...
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... However, a reset function is available which will clear all registers. DS154F2 CS61574A CS61575 In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP) ...
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... SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in appli- cations where the host processor has a bi-directional I/O port. LSB, first bit CS61574A CS61575 ...
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... RV+/RGND supply. Wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. DS154F2 CS61574A CS61575 Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering ...
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... LOS MTIP 12 17 TTIP TRING 13 16 TGND TV top 8 view DPM LOS TTIP CS61574A CS61575 TAOS LLOOP RLOOP LEN2 25 LEN1 24 LEN0 23 22 RGND 21 RV RRING RTIP MRING MTIP TRING TV+ DS154F2 ...
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... RCODE 12 17 TTIP TRING 13 16 TGND TV BPV top 8 view AIS LOS TTIP CS61574A CS61575 TAOS LLOOP RLOOP LEN2 25 LEN1 24 LEN0 23 22 RGND 21 RV RRING RTIP PCS RCODE TRING TV+ 21 ...
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... LOS MTIP 12 17 TTIP TRING 13 16 TGND TV top 8 view DPM LOS TTIP CS61574A CS61575 CLKE SCLK CS SDO 25 SDI 24 INT 23 22 RGND 21 RV RRING RTIP MRING MTIP TRING TV+ DS154F2 ...
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... INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. DS154F2 CS61574A CS61575 23 ...
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... Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. 24 CS61574A CS61575 DS154F2 ...
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... Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. DS154F2 CS61574A CS61575 25 ...
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... IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor. Ordering Guide Model Frequency CS61575-IP1 T1 & E1 CS61575-IL1 T1 & E1 CS61574A-IP1 T1 & E1 CS61574A-IL1 T1 & FIFO Depth (Bits) ...
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... DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. B D2/E2 DS154F2 15 28 pin E1 Plastic DIP 28-pin PLCC MILLIMETERS E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 12.32 D1/E1 11.43 D1 D2/ CS61574A CS61575 MILLIMETERS DIM MIN NOM MAX MIN 3.94 4.32 A 5.08 0.155 A1 0.51 0.76 1.02 0.020 B 0.36 0.46 0.56 0.014 B1 1.02 1.27 1.65 0.040 C 0.20 0.25 0.38 0.008 D 36.45 36.83 37.21 1.435 E1 13.72 13.97 14 ...
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... Figures A1-A3 show a 0.47 F capacitor in E1 series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting current through the transformer primary. This current might satu- rate the transformer producing an output offset level shift. CS61574A CS61575 +5V 100 Serial ...
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... EXTENDED 20 4 RRING TCODE HARDWARE MODE 7 RDATA 8 RCLK 3 TDATA 16 TRING 2 TCLK 13 TTIP 9 XTALIN 10 XTALOUT RGND TGND Extended Hardware Mode Configuration CS61574A CS61575 Line Length Setting RECEIVE LINE 2CT:1 PE-65351 0. TRANSMIT 6 5 LINE 1:1.26 PE-65389 Line Length Setting 1 ...
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... In some applications it is desirable to attenuate and 120 jitter from the signal to be transmitted. A CS61575 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. ...
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... If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted be- fore being input to the CS62180B. If the CS61575 or CS61574A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B. ...
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Notes • ...
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... ORDERING INFORMATION: CDB61534, CDB6158, CDB61574A, CDB61575, CDB61304A, CDB61305A +5V 0V Reset Circuit CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A coax E1, or 120 twisted-pair E1 operation. CDB61535. CDB61535A, CDB6158A, CDB61574, CDB61577, TTIP TRING RTIP RRING XTL twisted-pair SEP ’ ...
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... Mode selection is accomplished with slide switch SW1 and jump- ers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes ...
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... E1 75 LOS applications with the CS61534, 12 CS61535, CS6158, CS61574, RV+ OR CS61577) LOS Q2 Q1 2N2222 2N2222 U1: CS61534, CS61535, LED LED CS61535A, CS6158 CS6158A, CS61574 CS61574A, CS61575, 470 470 CS61577, CS61304A, OR CS61305A RV+ T2 RTIP 2:1 RRING TTIP JP5 TRING 35 ...
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Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...
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The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...
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... The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in Table 2. For exam- ple, the Pulse Engineering PE-65388 transformer may be used with the transmitter of the CS61575 device for 100 T1 applications only (as indi- cated by note 3) when installed in transformer socket T1 with pin 1 at position D (upper right) ...
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TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...
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Figure 2. Silk Screen Layer (NOT TO SCALE) LINE INTERFACE EVALUATION BOARD DS40DB3 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 41 ...
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Figure 4. Bottom Trace Layer (NOT TO SCALE) 42 LINE INTERFACE EVALUATION BOARD DS40DB3 ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...