VSC8117 Vitesse Semiconductor Corp., VSC8117 Datasheet
VSC8117
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VSC8117 Summary of contents
Page 1
... Equipment Loopback function which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel data bus and clock outputs. The VSC8117 also provides the option of selecting between either its internal CRU’s recovered clock and data signals or optics containing a G52221-0, Rev ...
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... ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery CRU clock and data signals. (In this mode the VSC8117 operates just like the VSC8111 and VSC8116). The receive section also contains a SONET/SDH frame detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel converter ...
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... The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8117 will con- tinually perform frame detection and recovery as long as this pin is held high even more frames has been detected ...
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... This LOS detection feature can be disabled by applying a high level to the LOSDETEN_ input. The VSC8117 also has a PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually called “ ...
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... Data Sheet VSC8117 RXDATAIN CRU Recovered Clock RXCLKIN TXDATAOUT FACLOOP Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral- lel to serial conversion of the low speed data (TXIN[7:0]) is selected and converted back to parallel data in the receiver section and presented to the low speed parallel outputs (RXOUT[7:0]) ...
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... Clock Synthesis The VSC8117 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622MHz high speed clock used for serialization in the transmitter section. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feed- back system ...
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... Data Sheet VSC8117 Good analog design practices should be applied to the board design for these external components. Tightly controlled analog ground and power planes should be provided for the PLL portion of the circuitry. The dedi- cated PLL power (VDDA) and ground (VSSA) pins should have quiet supply planes to minimize jitter genera- tion within the clock synthesis unit ...
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... The CRU is designed to tolerate this jitter with margin over the specification limits, see Figure 7. The CRU obtains and maintains lock based on the data transition information. When there is no transition on the data stream, the recovered clock frequency can drift. The VSC8117 can maintain lock over 100 bits of no switching on the data stream. ...
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... Data Sheet VSC8117 AC Timing Characteristics Figure 8: Receive High Speed Data Input Timing Diagram RXCLKIN+ RXCLKIN- RXDATAIN+ RXDATAIN- Table 2: Receive High Speed Data Input Timing Table (STS-12 Operation) Parameter T Receive clock period RXCLK T Serial data setup time with respect to RXCLKIN RXSU T Serial data hold time with respect to RXCLKIN ...
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... Pulse width of frame detection pulse FP PW Page 10 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description Description T RXCLKIN T RXLSCK T RXVALID Description VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Min Typ Max Units - 12 Min Typ Max ...
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... T Pulse width of frame detection pulse FP PW Data Latency The VSC8117 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock signal. Table 8: Data Latency Circuit Mode Receive ...
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... Min Typ Max — — V – 0.9V DDP 0.7 — — 1.1 — V – 1.3V DDP 600 — 1300 VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Min Typ Max Units -20 +20 ppm Max Units Conditions 10-90% — ns 10-90% — ns — ps 20-80% 20-80% — ...
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... Data Sheet VSC8117 Table 13: PECL and TTL Inputs and Outputs Parameters Description Differential V Output Voltage OUT50 (PECL) Input HIGH V IH voltage (PECL) Input LOW V IL voltage (PECL) Differential Input V IN Voltage (PECL) I/P Common V Mode Range ICM (PECL) Output HIGH V OH voltage (TTL) ...
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... Commercial Operating Temperature Range ..................................................................... 0 Extended Operating Temperature Range........................................................................ 0 Industrial Operating Temperature Range ...................................................................... -40 Page 14 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION (1) ) Potential to GND..........................................................................-0.5V to +6V ).......................................................................................... +3.3V or +5.0V VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 +0.5V DDP + 0. +125 +150 ...
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... Data Sheet VSC8117 Package Pin Descriptions Table 15: Pin Identification Signal Pin RESET 1 LOOPTIM0 2 CMUFREQSEL 3 VDDP 4 TXDATAOUT+ 5 TXDATAOUT- 6 LOSDETEN_ 7 RXCLKIN+ 8 RXCLKIN- 9 VDDP 10 OOF 11 DSBLCRU 12 RXDATAIN+ 13 RXDATAIN- 14 VDD 15 REFCLKP+ 16 REFCLKP- 17 VDD 18 RXOUT0 19 RXOUT1 20 VSS 21 RXOUT2 22 RXOUT3 23 RXOUT4 24 RXOUT5 25 RXOUT6 26 RXOUT7 27 VSS 28 RXLSCKOUT 29 FP ...
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... Equipment loopback, loops low speed byte wide transmit I TTL input data to receive output bus Facility loopback, loops high speed receive data and clock I TTL directly to transmit outputs. I TTL Loops TXDATAOUT to the CRU replacing RXDATAIN+/- VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 Pin Description G52221-0, Rev 4.1 1/8/00 ...
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... Data Sheet VSC8117 Package Information 64 Pin PQFP Package Drawings TYP G52221-0, Rev. 4.1 1/8/00 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery ...
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... The VSC8117QB1 is designed to operate at a maximum case temperature 115 antee that the maximum case temperature specification is not violated. Given the thermal resistance of the pack- age in still air, the user can operate the VSC8117QB1 in still air if the ambient temperature does not exceed o ...
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... Commercial Temperature ambient case VSC8117QP1 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Extended Temperature ambient to 115 C case VSC8117QP2 622Mb/s Mux/Dmux with CMU and CRU in 64 Pin PQFP Industrial Temperature, -40 C ambient case Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice ...
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... Table 17 contains recommended values for each of the components. TTL Input Structure The TTL inputs of the VSC8117 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol- erances (see Table 13). The input structure, shown in Figure 13, uses a current limiter to avoid overdriving the input FETs. ...
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... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery Figure 12: AC Coupled High Speed I/O VSC8117 +3.3V PECL I/O C1 GND Note: Only one side of a differential signal is shown. Value ...
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... Page 22 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Figure 13: Input Structures INPUT Current Limit INPUT VITESSE SEMICONDUCTOR CORPORATION Data Sheet VSC8117 V DDP +3.3 /+5 V +3.3 V All Resistors 3.3K GND High Speed Differential Input (RXDATAIN+/RXDATAIN-) (RXCLKIN+/RXCLKIN-) (REFCLKP+/REFCLKP-) G52221-0, Rev 4 ...