EPM7256ATC100-7 Altera Corporation, EPM7256ATC100-7 Datasheet

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EPM7256ATC100-7

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EPM7256ATC100-7
Description
Manufacturer
Altera Corporation
Datasheet

Specifications of EPM7256ATC100-7

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QFP

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Features...
Altera Corporation
DS-M7000A-4.5
September 2003, ver. 4.5
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
Data Sheet
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
Extended temperature range
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
Pull-up resistor on I/O pins during in-system programming
or the
®
) architecture (see
®
MAX 7000B Programmable Logic Device Family Data
MAX 7000AE
Includes
MAX 7000 Programmable Logic Device Family
Table
1)
Programmable Logic
MAX 7000A
Data Sheet
Device
Sheet.
1

Related parts for EPM7256ATC100-7

EPM7256ATC100-7 Summary of contents

Page 1

... September 2003, ver. 4.5 Features... f Altera Corporation DS-M7000A-4.5 Includes MAX 7000AE ® High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX ® ) architecture (see 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ...

Page 2

... Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Fast input setup times provided by a dedicated path from I/O pin to macrocell registers Programmable output slew-rate control Programmable ground pins EPM7256AE 5,000 256 8 16 164 5.5 3.9 2.5 3.5 172.4 Altera Corporation EPM7512AE 10,000 512 32 212 7.5 5.6 3.0 4.7 116.3 ...

Page 3

... General Description Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Software design support and automatic place-and-route provided by Altera’s development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF ...

Page 4

... TQFP 208-Pin PQFP 256-Pin BGA 164 164 176 212 TM feature. Therefore, designers can “SameFrame Pin-Outs” on page 15 “SameFrame Pin-Outs” on page 15 Altera Corporation 100-Pin FineLine BGA ( 256-Pin FineLine BGA (3) 100 100 164 164 212 for more ...

Page 5

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices use CMOS EEPROM cells to implement logic functions. The user-configurable MAX 7000A architecture accommodates a variety of independent combinatorial and sequential logic functions. The devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times ...

Page 6

... I/O control blocks The MAX 7000A architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and I/O pin. Figure 1 shows the architecture of MAX 7000A devices. Altera Corporation ...

Page 7

... Control Block I I/O Control Block Note: (1) EPM7032AE, EPM7064AE, EPM7128A, EPM7128AE, EPM7256A, and EPM7256AE devices have six output enables. EPM7512AE devices have 10 output enables. Altera Corporation MAX 7000A Programmable Logic Device Data Sheet LAB Macrocells ...

Page 8

... The Altera development system automatically optimizes product-term allocation according to the logic requirements of the design. Figure 2 shows a MAX 7000A macrocell. Global Clocks 2 Fast Input Programmable Select Register PRN D/T Q Clock/ Enable ENA CLRN Select VCC Clear Select To PIA Altera Corporation From I/O pin Register Bypass To I/O Control Block ...

Page 9

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet For registered functions, each macrocell flipflop can be individually programmed to implement operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera software then selects the most efficient flipflop operation for each registered function to optimize resource utilization ...

Page 10

... Figure 3. MAX 7000A Shareable Expanders Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders ) is incurred when SEXP Figure 3 shows how shareable expanders Product-Term Select Matrix Altera Corporation Macrocell Product-Term Logic Macrocell Product-Term Logic ...

Page 11

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Parallel Expanders Parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. Parallel expanders allow product terms to directly feed the macrocell OR logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the LAB ...

Page 12

... LAB. An EEPROM cell controls one input to a 2-input AND gate, which selects a PIA signal to drive into the LAB. Preset Clock Clear Preset Clock Clear To Next Macrocell Figure 5 shows how the PIA signals are routed Altera Corporation Macrocell Product- Term Logic Macrocell Product- Term Logic ...

Page 13

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 5. MAX 7000A PIA Routing PIA Signals While the routing delays of channel-based routing schemes in masked or FPGAs are cumulative, variable, and path-dependent, the MAX 7000A PIA has a predictable delay. The PIA makes a design’s timing performance easy to predict ...

Page 14

... The MAX 7000A architecture provides dual I/O feedback, in which macrocell and pin feedbacks are independent. When an I/O pin is configured as an input, the associated macrocell can be used for buried logic Global Output Enable Signals (1) OE Select Multiplexer VCC GND Open-Drain Output Slew-Rate Control Altera Corporation , the output is CC ...

Page 15

... SameFrame Pin-Outs Altera Corporation MAX 7000A Programmable Logic Device Data Sheet MAX 7000A devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. ...

Page 16

... EPM7128AE and EPM7256AE devices. The Jam Standard Test and Programming Language (STAPL), JEDEC standard JESD 71, can be used to program MAX 7000A devices with in- circuit testers, PCs, or embedded processors. Altera Corporation ...

Page 17

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet For more information on using the Jam STAPL language, see Note 88 (Using the Jam Language for ISP & ICR via an Embedded Processor) and Application Note 122 (Using Jam STAPL for ISP & ICR via an Embedded Processor) ...

Page 18

... The ISP times for a stand-alone verification of a single MAX 7000A device can be calculated from the following formula: Cycle VTCK -------------------------------- VER VPULSE f TCK where Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK Altera Corporation ...

Page 19

... MHz EPM7032AE 2.01 EPM7064AE 2.01 EPM7128AE 2.02 EPM7256AE 2.05 EPM7512AE 2.09 EPM7128A (1) 5.19 EPM7256A (1) 6.59 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The programming times described in with the worst-case method using the enhanced ISP algorithm. & Cycle Values TCK Programming t (s) Cycle PPULSE 2.00 55,000 2.00 105,000 2.00 205,000 2 ...

Page 20

... JTAG control pins for each device. If the JTAG interface is not required, the JTAG pins are available as user I/O pins. TCK 500 kHz 200 kHz 100 kHz 0.04 0.09 0.18 0.07 0.18 0.35 0.14 0.34 0.68 0.30 0.75 1.49 0.60 1.49 2.97 1.09 2.67 5.31 2.08 5.15 10.27 Altera Programming Hardware Data Sheet. Manufacturers. Altera Corporation Units 50 kHz 0.36 s 0.70 s 1.36 s 2.98 s 5.94 s 10.59 s 20.51 s ...

Page 21

... These instructions are used when programming MAX 7000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or using a Jam STAPL File, JBC File, or SVF File via an embedded processor or test equipment. Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Description ...

Page 22

... Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST. Tables 9 Boundary-Scan Register Length 96 192 288 288 480 480 624 Note (1) IDCODE (32 Bits) Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 Altera Corporation and Bit) ( ...

Page 23

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 8 shows timing information for the JTAG signals. Figure 8. MAX 7000A JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 11 shows the JTAG timing parameters and values for MAX 7000A devices. Table 11. JTAG Timing Parameters & ...

Page 24

... MAX 7000A MultiVolt I/O support. Table 12. MAX 7000A MultiVolt I/O Support V Voltage Input Signal (V) CCIO 2.5 v 2 for the t LPA parameters. levels lower than 3.0 V CCIO instead of t OD2 Output Signal (V) 3.3 5.0 2 Altera Corporation option turned on LAD LAC IC . Inputs can OD1 3.3 5 ...

Page 25

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Open-Drain Output Option MAX 7000A devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. This output can also provide an additional wired-OR plane ...

Page 26

... EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. power planes can be powered in any CCINT Figure 9. Test patterns can be used and then Altera Corporation and V CCINT CCIO ...

Page 27

... STG T Ambient temperature A T Junction temperature J Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 9. MAX 7000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions ...

Page 28

... Input fall time F 28 Conditions (3), (13) (3) (3) (4) Commercial range Industrial range (5) Commercial range Industrial range (5) Extended range (5) Min Max Unit 3.0 3.6 V 3.0 3.6 V 2.3 2.7 V 3.0 3.6 V –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 105 ° C –40 130 ° Altera Corporation ...

Page 29

... Value of I/O pin pull-up resistor ISP during in-system programming or during power-up Table 16. MAX 7000A Device Capacitance Symbol Parameter C Input pin capacitance IN C I/O pin capacitance I/O Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (6) Conditions I = – CCIO I = –0 ...

Page 30

... POR is 3.0 V. The device is fully initialized within the POR time after V CCINT reaches the sufficient POR voltage level. 30 must rise monotonically. CC ° ° to 100 C. For in-system programming support between pin (high-voltage pin during programming) OE1 Table 14 on page 28. parameter refers OH parameter refers to OL CCINT Altera Corporation ...

Page 31

... EPM7128A & EPM7256A Devices 3.3 V 120 I 80 Typical I O Output Current (mA Output Voltage (V) O Timing Model Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Figure 10 shows the typical output drive characteristics of MAX 7000A devices. 2 Typical 3.3 V CCINT Output V = 3.3 V CCI O O ...

Page 32

... Output Register Parallel Delay Delay PEXP PRE t t CLR COMB t t FSU t FH Fast Input Delay Figure 12 shows the timing relationship Altera Corporation OD1 OD2 OD3 I/O Delay for more ...

Page 33

... F driven for a logic high and 0 V for a logic low. All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander (Logic Array Output) Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin PIA Delay ...

Page 34

... Note (1) Conditions Min ( (2) (2) 2.9 (2) 0.0 2.5 0.0 1.0 2.0 2.0 (2) 1.6 (2) 0.3 (2) 1.0 2.0 2.0 (3) 2.0 (2) (2), (4) 227.3 (2) (2), (4) 227.3 Speed Grade -4 -7 Max Min Max Min 4.5 7.5 4.5 7.5 4.7 6.3 0.0 0.0 3.0 3.0 0.0 0.0 3.0 1.0 5.0 1.0 3.0 4.0 3.0 4.0 2.5 3.6 0.5 0.5 4.3 1.0 7.2 1.0 3.0 4.0 3.0 4.0 3.0 4.0 4.4 7.2 138.9 103.1 4.4 7.2 138.9 103.1 Altera Corporation Unit -10 Max 6 9 9.7 ns MHz 9.7 ns MHz ...

Page 35

... Register setup time SU t Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -4 Min Max 0.7 0.7 2.3 1.9 0.5 1.5 0 1.3 ( ...

Page 36

... IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA 36 Conditions -4 Min Max 1.2 0.6 0.8 1.2 1.2 (2) 0.9 (6) 2.5 Note (1) Speed Grade -7 -10 Min Max Min Max 2.0 2.5 1.0 1.2 1.3 1.9 1.9 2.6 1.9 2.6 1.5 2.1 4.0 5.0 Altera Corporation Unit ...

Page 37

... Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -4 Min Max 4.5 ( 4.5 (2) (2) 2.8 (2) 0.0 2 ...

Page 38

... Combinatorial delay COMB t Array clock delay IC 38 Conditions -4 Min Max 0.6 0.6 2.5 1.8 0.4 1.5 0 1 4.5 ( 9.0 4.0 1.3 0.6 1.0 1.5 0.7 0.6 1.2 Note (1) Speed Grade -7 -10 Min Max Min Max 1.1 1.4 1.1 1.4 3.0 3.7 3.0 3.9 0.7 0.9 2.5 3.2 1.0 1.2 0.0 0.0 1.3 1.8 1.8 2.3 6.3 6.8 4.0 5.0 4.5 5.5 9.0 10.0 4.0 5.0 2.0 2.9 1.0 1.3 1.5 1.5 1.5 1.5 1.2 1.6 0.9 1.3 1.9 2.5 Altera Corporation Unit ...

Page 39

... Parameter t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -4 Min Max 0.6 1.0 1.3 1.3 (2) 1.0 (6) 3.5 Note (1) Speed Grade -7 -10 Min ...

Page 40

... Note (1) Conditions -5 Min Max 5.0 ( 5.0 (2) (2) 3.3 (2) 0.0 2.5 0 1.0 3.4 2.0 2.0 (2) 1.8 (2) 0 1.0 4.9 (2) 2.0 2.0 (3) 2.0 (2) 5.2 (2), (4) 192.3 (2) 5.2 (2), (4) 192.3 Speed Grade -7 -10 Min Max Min Max 7.5 7.5 4.9 6.6 0.0 0.0 3.0 3.0 0.0 0.0 1.0 5.0 1.0 3.0 4.0 3.0 4.0 2.8 3.8 0.3 0.4 1.0 7.1 1.0 3.0 4.0 3.0 4.0 3.0 4.0 7.7 10.2 129.9 98.0 7.7 10.2 129.9 98.0 Altera Corporation Unit 6 9 MHz ns MHz ...

Page 41

... Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB t Array clock delay IC Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -5 Min Max 0.7 0.7 2.5 2.0 0.4 1.6 0 1.3 ( ...

Page 42

... Parameter t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA 42 Conditions -5 Min Max 0.7 1.1 1.4 1.4 (2) 1.4 (6) 4.0 Note (1) Speed Grade -7 -10 Min Max Min Max 1.0 1.3 1.6 2.0 2.0 2.7 2.0 2.7 2.0 2.6 4.0 5.0 Altera Corporation Unit ...

Page 43

... Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -5 Min Max 5.5 ( 5.5 (2) (2) 3.9 (2) 0.0 2 ...

Page 44

... Register delay RD t Combinatorial delay COMB 44 Conditions -5 Min Max 0.7 0.7 2.4 2.1 0.3 1.7 0 1 4.5 ( 9.0 4.0 1.5 0.7 1.1 1.4 0.9 0.5 Note (1) Speed Grade -7 -10 Min Max Min Max 0.9 1.2 0.9 1.2 2.9 3.4 2.8 3.7 0.5 0.6 2.2 2.8 1.0 1.3 0.0 0.0 1.2 1.6 1.7 2.1 6.2 6.6 4.0 5.0 4.5 5.5 9.0 10.0 4.0 5.0 2.1 2.9 0.9 1.2 1.6 1.6 1.4 1.4 1.2 1.6 0.8 1.2 Altera Corporation Unit ...

Page 45

... IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -5 Min Max 1.2 0.8 1.0 1.6 1.6 (2) 1.7 (6) 4.0 Note (1) Speed Grade -7 -10 Min ...

Page 46

... Note (1) Conditions -7 Min Max 7.5 ( 7.5 (2) (2) 5.6 (2) 0.0 3.0 0 1.0 4.7 3.0 3.0 (2) 2.5 (2) 0 1.0 7.8 (2) 3.0 3.0 (3) 3.0 (2) 8.6 (2), (4) 116.3 (2) 8.6 (2), (4) 116.3 Speed Grade -10 -12 Min Max Min Max 10.0 12.0 10.0 12.0 7.6 9.1 0.0 0.0 3.0 3.0 0.0 0.0 1.0 6.3 1.0 7.5 4.0 5.0 4.0 5.0 3.5 4.1 0.3 0.4 1.0 10.4 1.0 12.5 4.0 5.0 4.0 5.0 4.0 5.0 11.5 13.9 87.0 71.9 11.5 13.9 87.0 71.9 Altera Corporation Unit MHz ns MHz ...

Page 47

... Register setup time SU t Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD t Combinatorial delay COMB Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -7 Min Max 0.7 0.7 3.1 2.7 0.4 2.2 1 1.5 ( ...

Page 48

... IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA 48 Conditions -7 Min Max 1.8 1.0 1.7 1.0 1.0 (2) 3.0 (6) 4.5 Note (1) Speed Grade -10 -12 Min Max Min Max 2.3 2.9 1.3 1.7 2.2 2.7 1.4 1.7 1.4 1.7 4.0 4.8 5.0 5.0 Altera Corporation Unit ...

Page 49

... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock ACNT period f Maximum internal array ACNT clock frequency Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Note (1) Conditions -6 Min Max Min 6.0 ( 6.0 (2) (2) 4.2 5.3 (2) 0 ...

Page 50

... Register hold time of fast FH input 50 Conditions -6 Min Max Min 0.6 0.6 2.7 2.5 0.7 2.4 2 0 4 4.0 1.9 2.4 1.5 2.2 0.8 1.1 1.7 1.9 Note (1) Speed Grade -7 -10 -12 Max Min Max Min 0.7 0.9 0.7 0.9 3.1 3.6 3.2 4.3 0.8 1.1 3.0 4.1 3.0 4.1 0.0 0.0 0.6 0.7 1.1 1.2 5.6 5.7 4.0 5.0 4.5 5.5 9.0 10.0 4.0 5.0 3.1 3.8 3.3 4.3 1.1 1.1 1.9 1.9 Altera Corporation Unit Max 1.1 ns 1.1 ns 3.9 ns 5.1 ns 1.3 ns 4.9 ns 4.9 ns 0.0 ns 0.9 ns 1.4 ns 5.9 ns 5.0 ns 5.5 ns 10 ...

Page 51

... Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR t PIA delay PIA t Low-power adder LPA Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -6 Min Max Min 1.7 1.7 2.4 2.4 1.0 3.1 3.1 (2) 0.9 (6) 11.0 Note (1) Speed Grade ...

Page 52

... Conditions -6 Min Max Min 6.0 ( 6.0 (2) (2) 3.7 4.6 (2) 0.0 0.0 2.5 3.0 0.0 0 1.0 3.3 1.0 3.0 3.0 3.0 3.0 (2) 0.8 1.0 (2) 1.9 2 1.0 6.2 1.0 (2) 3.0 3.0 3.0 3.0 (3) 3.0 3.0 (2) 6.4 (2), (4) 156.3 125.0 (2) 6.4 (2), (4) 156.3 125.0 Speed Grade -7 -10 -12 Max Min Max Min 7.5 10.0 7.5 10.0 6.2 7.4 0.0 0.0 3.0 3.0 0.0 0.0 4.2 1.0 5.5 1.0 4.0 4.0 4.0 4.0 1.4 1.6 4.0 5.1 7.8 1.0 10.3 1.0 4.0 4.0 4.0 4.0 4.0 4.0 8.0 10.7 93.5 78.1 8.0 10.7 93.5 78.1 Altera Corporation Unit Max 12 12.8 ns MHz 12.8 ns MHz ...

Page 53

... Output buffer disable XZ delay t Register setup time SU t Register hold time H t Register setup time of fast FSU input t Register hold time of fast FH input t Register delay RD Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Conditions -6 Min Max Min 0.3 0.3 2.4 2.8 0.5 2.5 2 0.8 ( ...

Page 54

... Table 14 on page parameter into the signal LAD , and t parameters for macrocells SEXP ACL CPPW , in MHz) for MAX 7000A MAX + × MC – MC TON USED Altera Corporation Unit -12 Min Max 3.2 ns 5.4 ns 5.0 ns 2.2 ns 4.6 ns 4.6 ns 2.6 ns 10.0 ns 28. See parameter LPA × f × tog ...

Page 55

... Altera Corporation MAX 7000A Programmable Logic Device Data Sheet The parameters in this equation are Number of macrocells with the Turbo Bit option turned TON on, as reported in the MAX+PLUS II Report File (.rpt Number of macrocells in the device DEV MC = Total number of macrocells in the design, as reported in ...

Page 56

... MHz Low Power 200 250 192.3 MHz High Speed 108.7 MHz Low Power 200 250 3 Room Temperature 60 High Speed 125.0 MHz 20 Low Power 100 Frequency (MHz) Altera Corporation 222.2 MHz 200 250 ...

Page 57

... I/O/TMS 14 I/O 15 VCC 16 I 44-Pin PLCC Altera Corporation MAX 7000A Programmable Logic Device Data Sheet EPM7512AE 172.4 MHz High Speed Typical I Active (mA) 102.0 MHz 100 200 See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information ...

Page 58

... EPM7064AE I/O 12 VCCIO 13 I/O/TDI 14 I/O 15 I/O 16 I/O 17 I/O 18 GND 19 I/O 20 I EPM7128A I/O 24 EPM7128AE I/O 25 VCCIO 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 GND 32 A1 Ball Pad Corner I/O 73 I/O 72 GND 71 I/O/TDO 70 I/O 69 I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O Altera Corporation ...

Page 59

... Figure 17. 100-Pin TQFP Package Pin-Out Diagram Package outline not drawn to scale. Figure 18. 100-Pin FineLine BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates location of Ball A1 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet Pin 1 EPM7064AE EPM7128A EPM7128AE EPM7256A EPM7256AE ...

Page 60

... Package outline not drawn to scale Indicates location of Ball Indicates location of Pin 1 Pin 1 EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Pin 37 . EPM7064AE EPM7128A EPM7128AE EPM7256AE Pin 109 Pin Altera Corporation A1 Ball Pad Corner ...

Page 61

... Figure 21. 208-Pin PQFP Package Pin-Out Diagram Package outline not drawn to scale Pin 1 Pin 53 Altera Corporation MAX 7000A Programmable Logic Device Data Sheet . EPM7256A EPM7256AE EPM7512AE Pin 157 Pin 105 61 ...

Page 62

... Figure 22. 256-Pin BGA Package Pin-Out Diagram Package outline not drawn to scale. Indicates Location of Ball A1 62 EPM7512AE Altera Corporation A1 Ball Pad Corner ...

Page 63

... EPM7128A EPM7128AE EPM7256A EPM7256AE EPM7512AE Revision History Altera Corporation MAX 7000A Programmable Logic Device Data Sheet . The information contained in the MAX 7000A Programmable Logic Device Data Sheet version 4.5 supersedes information published in previous versions. Version 4.5 The following changes were made in the MAX 7000A Programmable Logic Device Data Sheet version 4 ...

Page 64

... MAX 7000A Programmable Logic Device Data Sheet ® Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as 101 Innovation Drive trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera San Jose, CA 95134 Corporation in the U ...

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