EPF10K250ABC600-2 Altera Corporation, EPF10K250ABC600-2 Datasheet

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... Maximum system gates Logic elements (LEs) Logic array blocks (LABs) Embedded array blocks (EABs) Total RAM bits Maximum user I/O pins Altera Corporation DS-F10K-4.2 Includes FLEX 10KA ® The industry’s first embedded programmable logic device (PLD) family, providing System-on-a-Programmable-Chip (SOPC) integration – ...

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... Table 3. Supply Voltages for FLEX 10K & FLEX 10KA Devices 5.0-V Devices EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50 EPF10K70 EPF10K100 EPF10K130V EPF10K250A 130,000 250,000 211,000 310,000 6,656 12,160 832 1,520 16 20 32,768 40,960 470 470 Table 3 TM options for reduced clock 3.3-V Devices EPF10K10A EPF10K30A EPF10K50V EPF10K100A EPF10K130V EPF10K250A Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Flexible interconnect ® – FastTrack Interconnect continuous routing structure for fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – ...

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... PQFP RQFP 102 134 102 134 102 147 147 102 147 147 Note (1) 484-Pin 600-Pin FineLine BGA BGA 150 (2) 246 369 406 470 470 Altera Corporation 240-Pin PQFP RQFP 189 189 189 189 189 189 189 189 403-Pin PGA 310 ...

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... The speed grade of this application is limited because of clock high and low specifications. (2) This application uses combinatorial inputs and outputs. (3) This application uses registered inputs and outputs. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet shows FLEX 10K performance for some common designs. All -1 Speed -2 Speed ...

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... FLEX 10K devices serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10K device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to reconfigure the device. TM parallel port Altera Corporation ...

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... Functional Description Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet For more information, see the following documents: Configuration Devices for APEX & FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Application Note 116 (Configuring APEX 20K, FLEX 10K & ...

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... FLEX 10K architecture. Each group of LEs is combined into an LAB; LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each row and column of the FastTrack Interconnect. Altera Corporation ...

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... IOE (IOE) IOE IOE Column Interconnect IOE IOE Row Interconnect Logic Array IOE IOE Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Embedded Array Block (EAB) IOE IOE IOE IOE IOE EAB EAB IOE IOE IOE IOE IOE Embedded Array FLEX 10K devices provide six dedicated inputs that drive the flipflops’ ...

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... EAB’s self-timed RAM need only meet the setup and hold time specifications of the global clock. When used as RAM, each EAB can be configured in any of the following sizes: 256 8, 512 4, 1,024 2, or 2,048 Figure 2. EAB Memory Configurations 256 8 512 1. See Figure 2. 4 1,024 2 Altera Corporation 2,048 1 ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Larger blocks of RAM are created by combining multiple EABs. For example, two 256 8 RAM blocks can be combined to form a 256 16 RAM block; two 512 a 512 8 RAM block. See Figure Figure 3. Examples of Combining EABs ...

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... EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 22 EAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 26. 12 Row Interconnect Data Data In Out D Q Address D Q RAM/ROM 256 512 1,024 2,048 Column Interconnect 1 Altera Corporation 24 ...

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... EPF10K10, EPF10K10A, EPF10K20, EPF10K30, EPF10K30A, EPF10K40, EPF10K50, and EPF10K50V devices have 30 LAB local interconnect channels; EPF10K70, EPF10K100, EPF10K100A, EPF10K130V, and EPF10K250A devices have 34 LABs. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Logic Array Block Each LAB consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect ...

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... Each LE drives both the local and the FastTrack Interconnect. See Figure 6. Carry-In Cascade-In Carry Cascade Table Chain Chain (LUT) Clock Carry-Out Cascade-Out Register Bypass Programmable Register PRN D Q ENA CLRN Altera Corporation To FastTrack Interconnect To LAB Local Interconnect ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet The programmable flipflop in the LE can be configured for operation. The clock, clear, and preset control signals on the flipflop can be driven by global signals, general-purpose I/O pins, or any internal logic. For combinatorial functions, the flipflop is bypassed and the output of the LUT drives the output of the LE. The LE has two outputs that drive the interconnect ...

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... The final carry-out signal is routed to an LE, where it can be used as a general-purpose signal. Figure 7. Carry Chain Operation (n-bit Full Adder) Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 s2 Register LE2 sn Register LEn Register Carry-Out LEn + 1 Altera Corporation ...

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... LUT d[7..4] LUT d[(4 n -1)..(4 n -4)] LUT Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Cascade Chain With the cascade chain, the FLEX 10K architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’ ...

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... LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The Altera software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. Figure 9 shows the LE operating modes. Altera Corporation ...

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... Clearable Counter Mode Carry-In data1 (ena) data2 (nclr) data3 (data) data4 (nload) Note: (1) Packed registers cannot be used with the cascade chain. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Cascade-In (1) 4-Input LUT Cascade-Out Cascade-In 3-Input LUT 3-Input ...

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... For example adder, this output is the sum of three signals and carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports simultaneous use of the cascade chain. Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Up/Down Counter Mode The up/down counter mode offers counter enable, clock enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register ...

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... In any of the clear and preset modes, the chip-wide reset overrides all other signals. Registers with asynchronous presets may be preset when the chip-wide reset is asserted. Inversion can be used to implement the asynchronous preset. of how to enter a section of a design for the desired functionality. Figure 10 shows examples Altera Corporation ...

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... Chip-Wide Reset Asynchronous Load with Preset NOT labctrl1 (Asynchronous Load) labctrl2 (Preset) data3 (Data) NOT Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Asynchronous Preset Chip-Wide Reset labctrl1 or labctrl2 VCC PRN D Q CLRN D Chip-Wide Reset Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2 ...

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... DATA3 to account for the inversion of the register’s output. Asynchronous Load without Preset or Clear When implementing an asynchronous load without preset or clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. , asserting Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet FastTrack Interconnect In the FLEX 10K architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, which is a series of continuous horizontal and vertical routing channels that traverse the device. This global routing structure provides predictable performance, even in complex designs ...

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... each intersection, four row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB. To LAB Local Interconnect Column Channels To Other Columns From Adjacent LAB To Adjacent LAB To Other Rows Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet For improved routing, the row interconnect is comprised of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels ...

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... LAB row B, column 3. IOE IOE IOE LAB LAB A2 A3 LAB LAB B2 B3 IOE IOE IOE See Figure 15 for details. IOE IOE To LAB A5 To LAB A4 Cascade & Carry Chains To LAB B5 To LAB B4 IOE IOE Altera Corporation IOE IOE See Figure 14 for details. IOE IOE ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet I/O Element An I/O element (IOE) contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time output register for data that requires fast clock- to-output performance ...

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... Inputs CLK[3..2] 30 VCC VCC OE[7..0] VCC CLK[1..0] VCC ENA[5..0] VCC CLRN[1..0] Chip-Wide VCC OE Register D Q ENA CLRN Chip-Wide Reset Chip-Wide Output Enable Output Register D Q ENA Open-Drain CLRN Output Slew-Rate Control Reset Input Register D Q ENA CLRN Chip-Wide Reset Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Each IOE selects the clock, clear, clock enable, and output enable controls from a network of I/O control signals called the peripheral control bus. The peripheral control bus uses high-speed drivers to minimize signal skew across devices ...

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... Row D Row E Row E Row F Row F Row H EPF10K130V EPF10K250A Row C Row E Row G Row N Row K Row M Row H Row F Row D Row J Row L Row I Altera Corporation EPF10K50 EPF10K50V Row A Row B Row D Row F Row H Row J Row A Row C Row E Row G Row I Row J Row E Row G Row I Row P Row M ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Signals on the peripheral control bus can also drive the four global signals, referred to as GLOBAL0 through GLOBAL3 in internally generated signal can drive the global signal, providing the same low-skew, low-delay characteristics for an internally generated signal as for a signal driven by an input ...

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... Each IOE can be driven by column channels via a multiplexer. The set of column channels that each IOE can access is different for each IOE. See Row Channels per Pin (m) 144 144 216 216 216 312 312 312 456 Figure 15. Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 15. FLEX 10K Column-to-IOE Connections The values for m and n are provided in Table 11. Column n Interconnect n n Each IOE can drive up to two column channels. Table 11 lists the FLEX 10K column-to-IOE interconnect resources. ...

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... Figure 16. SameFrame Pin-Out Example Designed for 484-PinFineLine BGA Package 256-Pin FineLine BGA 256-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) Figure 16). Printed Circuit Board 484-Pin FineLine BGA 484-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements) Altera Corporation ...

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... ClockLock & ClockBoost Features Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet To support high-speed designs, selected FLEX 10K devices offer optional ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL) that is used to increase design speed and reduce resource usage. The ClockLock circuitry uses a synchronizing PLL that reduces the clock delay and skew within a device ...

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... However, a clamping diode can be turned on for a subset of pins, which allows devices to bridge between a 3.3-V PCI bus and a 5.0-V device. CLOCKBOOST=1 INPUT_FREQUENCY= CLOCKBOOST=2 INPUT_FREQUENCY= Its effect can be simulated in the Altera is 3 pin that has the clamping CCIO aout bout to CCIO Altera Corporation ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Slew-Rate Control The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slower slew rate reduces system noise and adds a maximum delay of approximately 2 ...

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... JTAG BST can be performed before or after configuration, but not during configuration. FLEX 10K devices support the JTAG instructions shown in MultiVolt I/O Support Levels (V) Input 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5, 3.3, or 5.0 2.5, 3.3, or 5.0 power supplies can be powered in any CCINT Output 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 3.3 or 5.0 2.5 pins. CCIO Table 13. Altera Corporation ...

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... These instructions are used when configuring a FLEX 10K device via JTAG ports with a BitBlaster, or ByteBlasterMV or MasterBlaster download cable, or using a Jam File (.jam) or Jam Byte-Code File (.jbc) via an embedded processor. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet The instruction register length of FLEX 10K devices is 10 bits. The USERCODE register length in FLEX 10K devices is 32 bits ...

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... BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Jam Programming & Test Language Specification IDCODE (32 Bits) Manufacturer’s Identity (11 Bits) 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 00001101110 Altera Corporation 1 (1 Bit) ( ...

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... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 18 shows the timing requirements for the JTAG signals. Figure 18. JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 16 shows the timing parameters and values for FLEX 10K devices. Table 16. JTAG Timing Parameters & ...

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... Multiple test patterns can be used 464 (703 ) [521 ] Device Output 250 (8. [481 Device input rise and fall times < Note (1) Min (2) –2.0 –2.0 –25 –65 –65 Altera Corporation VCC To Test System C1 (includes JIG capacitance) Max Unit 7 150 ° C 135 ° C 150 ° C 135 ° ...

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... O T Ambient temperature A T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions (3), (4) (3), (4) (3), (4) For commercial use For industrial use For commercial use For industrial use ...

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... Conditions 1.0 MHz 1.0 MHz 1.0 MHz OUT Notes (5), (6) Min Typ 2.0 V CCINT –0.5 2.4 2.4 V – 0.2 CCIO –10 –40 0.5 Note (10) Min Min Altera Corporation Max Unit + 0 0.45 V 0. Max Unit Note (10) ...

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... Typical I O Output Current (mA Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet must rise monotonically 5 Figure 20 shows the typical output drive characteristics of FLEX 10K devices with 5.0-V and 3.3-V V the 5.0-V PCI Local Bus Specification, Revision 2.2 (for 5.0 ...

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... For commercial use For industrial use For commercial use For industrial use Note (1) Min (2) –0.5 –2.0 –25 –65 –65 Min 3.00 (3.00) 3.60 (3.60) 3.00 (3.00) 3.60 (3.60) -0 –40 0 –40 Altera Corporation Max Unit 4 150 ° C 135 ° C 150 ° C 135 ° C Max Unit CCIO 70 ° ...

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... This value is specified for normal device operation. The value may vary during power-up. (11) This parameter applies to -1 speed grade EPF10K50V devices, -2 speed grade EPF10K50V industrial temperature devices, and -2 speed grade EPF10K130V devices. (12) Capacitance is sample-tested only. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions I = – ...

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... Ceramic packages, under bias PQFP, TQFP, RQFP, and BGA packages, under bias 3.3 V Room Temperature Output Voltage (V) O Note (1) Min (2) –0.5 –2.0 –25 –65 –65 Altera Corporation 3 Max Unit 4 150 ° C 135 ° C 150 ° C 135 ° C ...

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... O T Ambient temperature A T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions (3), (4) (3), (4) (3), (4) (5) For commercial use For industrial use For commercial use For industrial use ...

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... 5 –0.3 V (10 ground, no load ground, no load (11) I (6), (7) Min Typ Max 1 CCINT whichever is lower –0.5 0.3 V CCINT 2.4 V – 0.2 CCIO 0.9 V CCIO 2.1 2.0 1.7 0.45 0.2 0.1 V CCIO 0.2 0.4 0.7 –10 10 – Altera Corporation Unit ...

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... This value is specified for normal device operation. The value may vary during power-up. (11) This parameter applies to all -1 speed grade commercial temperature devices and all -2 speed grade industrial-temperature devices. (12) Capacitance is sample-tested only. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Conditions ...

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... Output Voltage (V) Figure 23 shows the typical output drive characteristics of the EPF10K250A device with 3.3-V and 2.5 Moreover, device analysis CCIO Typical Output Current (mA Output Voltage ( CCIO 3.3 V CCINT V = 2.5 V CCIO Room Temperature Altera Corporation ...

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... Figure 23. Output Drive Characteristics for EPF10K250A Device 50 40 Typical Output Current (mA Timing Model Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet 3.3 V CCI NT Typical 3.3 V CCI O Output Room Temperature Current (mA Output Voltage (V) ...

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... Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the FLEX 10K device. Interconnect Logic Element I/O Element Embedded Array Block Altera Corporation ...

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... Figure 25. FLEX 10K Device LE Timing Model Carry-In Data-In Control-In Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figures 25 through 27 show the delays that correspond to various paths and functions within the LE, IOE, and EAB timing models. Cascade-In LUT Delay ...

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... I/O pin timing. Output Delays Delays t IOCO t OD1 t IOCOMB t OD2 t IOSU t OD3 t IOH IOCLR t ZX1 t ZX2 t ZX3 t INREG Output Register EAB Output Delays t t EABCO EABOUT t EABBYPASS t EABSU t EABH t EABCH t EABCL Delay Data-Out Altera Corporation ...

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... LE register control signal delay register clock-to-output delay CO t Combinatorial delay COMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Figure 28. Synchronous Bidirectional Pin External Timing Model Dedicated Clock Tables 32 through 36 describe the FLEX 10K device internal timing parameters ...

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... IOE register feedback delay IOFD t IOE input pad and buffer to FastTrack Interconnect delay INCOMB 60 Note (1) Parameter Note (1) Parameter = V CCIO = low voltage CCIO = V CCIO = low voltage CCIO Conditions Conditions (2) CCINT ( ( (2) CCINT ( (4) Altera Corporation ...

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... Address hold time after falling edge of write pulse WAH t Write enable to data output valid delay WO t Data-in to data-out valid delay DD t Data-out delay EABOUT t Clock high time EABCH t Clock low time EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) Parameter Conditions (5) (5) (5) (5) 61 ...

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... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO 62 Notes (1), (6) Parameter Conditions Altera Corporation ...

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... Clock-to-output delay for bidirectional pins with global clock at IOE register OUTCOBIDIR t Synchronous IOE output buffer disable delay XZBIDIR t Synchronous IOE output buffer enable delay, slow slew rate = off ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) Parameter Notes (8), (10) Parameter ...

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... V for commercial or industrial use in FLEX 10KA devices. = 2 5.0 V. Figures 29 and 30 show the asynchronous and synchronous timing waveforms, respectively, for the EAB macroparameters EABAA d1 t EABWP t EABWDSU din0 t EABWCCOMB a1 din0 Table a2 t EABRCCOMB d2 t EABWDH din1 t EABWAH a2 t EABDD din1 Altera Corporation 34 dout2 ...

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... EAB Synchronous Read WE Address a0 t EABDATASU CLK Data-Out EAB Synchronous Write (EAB Output Registers Used) WE din1 Data- Address t EABWESU CLK Data-Out Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet a1 t EABDATAH t EABDATACO din2 a2 t EABDATAH t EABDATASU t EABWCREG dout0 dout1 a2 t ...

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... COMB PRE t CLR Tables 39 through 47 show EPF10K10 and EPF10K20 device internal and external timing parameters. -3 Speed Grade Min Max 1.4 0.6 1.5 0.6 1.0 0.2 0.9 0.9 0.8 1.3 0.9 0.5 1.3 1.4 1.0 1.0 4.0 4.0 Note (1) -4 Speed Grade Min Max 1.7 0.7 1.9 0.9 1.2 0.3 1.2 1.2 0.9 1.5 1.1 0.6 2.5 1.6 1.2 1.2 4.0 4.0 Altera Corporation Unit ...

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... Table 40. EPF10K10 & EPF10K20 Device IOE Timing Microparameters Symbol t IOD t IOC t IOCO t IOCOMB t IOSU t IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 1.3 0.5 0.2 0.0 2.8 1.0 1.0 2.6 4.9 6.3 4.5 4.5 6.8 8.2 6.0 3.1 3.1 Note (1) -4 Speed Grade Min Max 1.6 0.7 0.2 0.0 3.2 1.2 1.2 3.5 6.4 8.2 5 ...

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... EABWE2 t EABCLK t EABCO t EABBYPASS t EABSU t EABH WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL 68 -3 Speed Grade Min Max 1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 2.0 8.7 5.8 1.6 0.3 0.5 1.0 5.0 5.0 0.5 4.0 5.8 Note (1) -4 Speed Grade Min Max 1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5 10.7 7.2 2.0 0.4 0.6 1.2 6.2 6.2 0.6 4.0 7.2 Altera Corporation Unit ...

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... Table 42. EPF10K10 & EPF10K20 Device EAB Internal Timing Macroparameters Symbol t EABAA t EABRCCOMB t EABRCREG t EABWP t EABWCCOMB t EABWCREG t EABDD t EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 13.7 13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9.5 Note (1) -4 Speed Grade Min Max 17.0 17.0 11.9 7.2 9.0 16.0 12.5 3.4 5.6 0.0 5 ...

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... TWOROWS t LEPERIPH t LABCARRY t LABCASC 70 -3 Speed Grade Min Max 4.8 2.6 4.3 3.4 2.6 0.6 3.6 0.9 4.5 8.1 3.3 0.5 2.7 -3 Speed Grade Min Max 5.2 2.6 4.3 4.3 2.6 0.6 3.7 1.4 5.1 8.8 4.7 0.5 2.7 Note (1) -4 Speed Grade Min Max 6.2 3.8 5.2 4.0 3.8 0.6 3.8 1.1 4.9 8.7 3.9 0.8 3.0 Note (1) -4 Speed Grade Min Max 6.6 3.8 5.2 4.0 3.8 0.6 3.9 1.6 5.5 9.4 5.6 0.8 3.0 Altera Corporation Unit Unit ...

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... XZBIDIR t ZXBIDIR Notes to tables: (1) All timing parameters are described in (2) Using register the signal may provide a lower setup time. (3) This parameter is specified by characterization. Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 16.1 5.5 0.0 2.0 6.7 -3 Speed Grade ...

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... PRE t CLR Tables 48 through 56 show EPF10K30, EPF10K40, and EPF10K50 device internal and external timing parameters. -3 Speed Grade Min Max 1.3 0.6 1.5 0.5 0.9 0.2 0.9 0.9 1.0 1.3 0.9 0.6 1.4 0.9 0.9 0.9 4.0 4.0 Note (1) -4 Speed Grade Min Max 1.8 0.6 2.0 0.8 1.5 0.4 1.4 1.4 1.2 1.6 1.2 0.6 1.4 1.3 1.2 1.2 4.0 4.0 Altera Corporation Unit ...

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... Table 49. EPF10K30, EPF10K40 & EPF10K50 Device IOE Timing Microparameters Symbol t IOD t IOC t IOCO t IOCOMB t IOSU t IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 0.4 0.5 0.4 0.0 3.1 1.0 1.0 3.3 5.6 7.0 5.2 5.2 7.5 8.9 7.7 3.3 3.3 Note (1) -4 Speed Grade Min Max 0.6 0.9 0.5 0.0 3.5 1.9 1.2 3.6 6.5 8.3 5 ...

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... EABWE2 t EABCLK t EABCO t EABBYPASS t EABSU t EABH WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL 74 -3 Speed Grade Min Max 1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 2.0 8.7 5.8 1.6 0.3 0.5 1.0 5.0 5.0 0.5 4.0 5.8 Note (1) -4 Speed Grade Min Max 1.9 6.0 1.2 6.2 2.2 0.6 1.9 1.8 2.5 10.7 7.2 2.0 0.4 0.6 1.2 6.2 6.2 0.6 4.0 7.2 Altera Corporation Unit ...

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... Table 51. EPF10K30, EPF10K40 & EPF10K50 Device EAB Internal Timing Macroparameters Symbol t EABAA t EABRCCOMB t EABRCREG t EABWP t EABWCCOMB t EABWCREG t EABDD t EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 13.7 13.7 9.7 5.8 7.3 13.0 10.0 2.0 5.3 0.0 5.5 0.0 5.5 0.0 2.1 0.0 9.5 Note (1) -4 Speed Grade Min Max 17.0 17.0 11.9 7.2 9.0 16.0 12.5 3.4 5.6 0.0 5 ...

Page 76

... TWOROWS t LEPERIPH t LABCARRY t LABCASC 76 -3 Speed Grade Min Max 6.9 3.6 5.5 4.6 3.6 0.3 3.3 2.5 5.8 9.1 6.2 0.4 2.4 -3 Speed Grade Min Max 7.6 3.6 5.5 4.6 3.6 0.3 3.3 3.1 6.4 9.7 6.4 0.4 2.4 Note (1) -4 Speed Grade Min Max 8.7 4.8 7.2 6.2 4.8 0.3 3.7 2.7 6.4 10.1 7.1 0.6 3.0 Note (1) -4 Speed Grade Min Max 9.4 4.8 7.2 6.2 4.8 0.3 3.7 3.2 6.4 10.6 7.1 0.6 3.0 Altera Corporation Unit Unit ...

Page 77

... INSU t (3) INH t (3) OUTCO Table 56. EPF10K30, EPF10K40 & EPF10K50 Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3 Speed Grade Min Max 8.4 3.6 5.5 4.6 3.6 0.3 3.3 3.9 7.2 10.5 7.5 0.4 2.4 -3 Speed Grade Min Max 17 ...

Page 78

... PRE t CLR Tables 32 through 38 in this data sheet. through 63 show EPF10K70 device internal and external timing Note (1) -3 Speed Grade Max Min Max 1.3 1.5 0.4 0.4 1.5 1.6 0.8 0.9 0.8 0.9 0.2 0.2 1.0 1.1 1.1 1.2 1.0 1.1 0.7 0.8 0.9 1.0 0.4 0.5 2.1 2.3 0.9 1.0 0.9 1.0 4.0 4.0 -4 Speed Grade Unit Min Max 2.0 ns 0.5 ns 2.0 ns 1.3 ns 1.2 ns 0.3 ns 1.4 ns 1.5 ns 1.3 ns 1.0 ns 1.4 ns 0.7 ns 2.6 ns 3.1 ns 1.4 ns 1.4 ns 4.0 ns 4.0 ns Altera Corporation ...

Page 79

... IOC t IOCO t IOCOMB t IOSU t IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 0.0 0.4 0.4 0.0 4.5 5.0 0.4 0.5 0.6 3.6 5.6 6.9 5.5 5.5 7.5 8.8 8.0 7.2 7.2 Note (1) -4 Speed Grade Max Min Max ...

Page 80

... EABSU t EABH WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL 80 -2 Speed Grade -3 Speed Grade Min Max Min 1.3 4.3 0.9 4.5 0.9 0.4 1.3 1.3 1.5 1.8 2.0 7.8 5.2 5.8 1.4 1.6 0.3 0.3 0.4 0.5 0.9 1.0 4.5 4.5 0.4 4.0 4.0 5.2 5.8 Note (1) -4 Speed Grade Max Min Max 1.5 1.9 4.8 6.0 1.0 1.2 5.0 6.2 1.0 2.2 0.5 0.6 1.5 1.9 1.8 2.5 8.7 10.7 7.2 2.0 0.4 0.6 1.2 5.0 6.2 5.0 6.2 0.5 0.6 4.0 7.2 Altera Corporation Unit ...

Page 81

... Table 60. EPF10K70 Device EAB Internal Timing Macroparameters Symbol t EABAA t EABRCCOMB t EABRCREG t EABWP t EABWCCOMB t EABWCREG t EABDD t EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 12.1 12.1 13.7 8.6 9.7 5.2 5.8 6.5 7.3 11.6 13.0 8.8 1.7 4.7 5.3 0.0 0.0 4.9 5.5 0.0 0.0 1.8 2.1 0.0 0.0 4.1 4.7 0.0 0.0 8 ...

Page 82

... Speed Grade Min Max Min 7.4 8.1 0.0 0.0 2.0 9.9 2.0 13.7 13.7 Note (1) -4 Speed Grade Max Min 7.3 4.8 7.1 6.2 4.8 0.4 4.9 3.4 8.3 13.2 5.7 0.9 3.0 Note (1) -4 Speed Grade Max Min 19.1 8.0 0.0 11.1 2.0 Note (1) -4 Speed Grade Max Min 10.4 0.0 11.1 2.0 15.4 15.4 Altera Corporation Unit Max 8.8 ns 6.0 ns 10.8 ns 7.7 ns 6.0 ns 0.5 ns 5.5 ns 3.7 ns 9.2 ns 14.7 ns 6.5 ns 1.1 ns 3.2 ns Unit Max 24 14.3 ns Unit Max ns ns 14.3 ns 18.5 ns 18.5 ns ...

Page 83

... EN t CICO t CGEN t CGENR t CASC COMB PRE t CLR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 64 through 70 show EPF10K100 device internal and external timing parameters. -3 Speed Grade Max Min 1.5 0.4 1.6 0.9 0.9 0.2 1.1 1.2 1.1 0.8 1.0 0.5 2.1 2.1 2 ...

Page 84

... ClockLock or INREG ClockBoost circuitry t with ClockLock or INREG ClockBoost circuitry t IOFD t INCOMB 84 -3DX Speed Grade -3 Speed Grade Min Max Min 0.0 0.5 0.4 0.0 5.5 5.5 0.5 0.5 0.7 4.0 6.3 7.7 6.2 6.2 8.5 9.9 9.0 3.0 8.1 8.1 Note (1) -4 Speed Grade Max Min Max 0.0 0.0 0.5 0.7 0.4 0.9 0.0 0.0 6.7 0.7 0.7 1.6 4.0 5.0 6.3 7.3 7.7 8.7 6.2 6.8 6.2 6.8 8.5 9.1 9.9 10.5 9.0 10.5 – – 8.1 10.3 8.1 10.3 Altera Corporation Unit ...

Page 85

... EABDATA2 t EABWE1 t EABWE2 t EABCLK t EABCO t EABBYPASS t EABSU t EABH WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3DX Speed Grade -3 Speed Grade Min Max Min 1.5 4.8 1.0 5.0 1.0 0.5 1.5 1.5 1.5 2.0 2.0 8.7 5.8 5.8 1.6 1.6 0.3 0.3 0.5 0.5 1.0 1.0 5.0 5.0 0.5 4.0 4.0 5.8 5.8 Note (1) -4 Speed Grade ...

Page 86

... EABRCREG t EABWP t EABWCCOMB t EABWCREG t EABDD t EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO 86 -3DX Speed Grade -3 Speed Grade Min Max Min 13.7 13.7 13.7 9.7 9.7 5.8 5.8 7.3 7.3 13.0 13.0 10.0 2.0 5.3 5.3 0.0 0.0 5.5 5.5 0.0 0.0 5.5 5.5 0.0 0.0 2.1 2.1 0.0 0.0 9.5 Note (1) -4 Speed Grade Max Min Max 13.7 17.0 17.0 11.9 7.2 9.0 16.0 10.0 12.5 2.0 3.4 5.6 0.0 5.8 0.0 5.8 0.0 2.7 0.0 9.5 11.8 Altera Corporation Unit ...

Page 87

... ClockLock or DCLK2LE ClockBoost circuitry t with ClockLock or ClockBoost DCLK2LE circuitry t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -3DX Speed Grade -3 Speed Grade Min Max 10.3 4.8 7.3 6.2 2.3 4.8 2.3 0.4 4.9 5.1 10.0 14.9 6.9 0.9 3.0 Note (1) -4 Speed Grade Min ...

Page 88

... Tables 32 through 38 Note (1) -4 Speed Grade Max Min 19.1 8.5 11.1 2.0 0.0 – – Note (1) -4 Speed Grade Max Min 10.4 0.0 11.1 2.0 15.3 15.3 – – – – – – in this data sheet. Unit Max 24 14 – ns Unit Max ns ns 14.3 ns 18 – ns – ns – ns Altera Corporation ...

Page 89

... PACKED CICO t CGEN t CGENR t CASC COMB PRE t CLR t 2 2.0 CL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 71 through 77 show EPF10K50V device internal and external timing parameters. -2 Speed Grade Max Min Max 0.9 1.0 0.1 0.5 0.5 0.8 0.4 0.4 0.7 0.9 0.2 0.2 0.8 0.7 0.4 0.3 0.7 0.7 0.3 1.0 0.5 0.7 ...

Page 90

... ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB 90 -2 Speed Grade Max Min Max 1.2 1.6 0.3 0.4 0.3 0.3 0.0 0.0 2.8 0.8 0.5 0.6 2.8 3.2 – – 6.5 6.9 2.8 3.1 2.8 3.1 – – 6.5 6.8 5.0 5.7 1.5 1.9 1.5 1.9 Note (1) -3 Speed Grade -4 Speed Grade Min Max Min 1.9 0.5 0.4 0.0 3.4 3.9 1.0 1.4 0.7 3.9 – 7.6 3.8 3.8 – 7.5 7.0 2.3 2.3 Unit Max 2.1 ns 0.5 ns 0 0.7 ns 4.7 ns – ns 8.4 ns 4.6 ns 4.6 ns – ns 8.3 ns 9.0 ns 2.7 ns 2.7 ns Altera Corporation ...

Page 91

... EABWE2 t EABCLK t EABCO t EABBYPASS t 0.8 EABSU t 0.8 EABH 6 0.1 WDSU t 0.1 WDH t 0.1 WASU t 0.1 WAH EABOUT t 2.0 EABCH t 6.0 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.7 2.8 4.9 3.9 0.0 2.5 4.0 4.1 0.4 0.8 0.1 0.2 0.9 1.1 1.5 1.6 5.5 8.2 4.9 0.8 0.2 0.4 0.8 2.8 4.3 2.8 4.3 0.5 0.4 4.0 4.9 Note (1) -3 Speed Grade -4 Speed Grade Min Max Min 3 ...

Page 92

... EABWP t 6.2 EABWCCOMB t 12.0 EABWCREG t EABDD t EABDATACO t 5.3 EABDATASU t 0.0 EABDATAH t 4.4 EABWESU t 0.0 EABWEH t 1.8 EABWDSU t 0.0 EABWDH t 4.5 EABWASU t 0.0 EABWAH t EABWO 92 -2 Speed Grade Max Min Max 9.5 13.6 13.6 8.8 4.9 6.1 11.6 6.8 9.7 1.0 1.4 4.6 0.0 4.8 0.0 1.1 0.0 4.6 0.0 5.1 9.4 Note (1) -3 Speed Grade -4 Speed Grade Min Max Min 16.5 16.5 20.8 10.8 13.4 6.0 7.4 7.5 9.2 14.2 17.4 11.8 1.8 5.6 6.9 0.0 0.0 5.8 7.2 0.0 0.0 1.4 2.1 0.0 0.0 5.6 7.4 0.0 0.0 11.4 Unit Max 20 14 14.0 ns Altera Corporation ...

Page 93

... DRR t (2), (3) 5.5 INSU t (3) 0.0 INH t (3) 2.0 OUTCO Table 77. EPF10K50V Device External Bidirectional Timing Parameters Symbol -1 Speed Grade Min t 2.0 INSUBIDIR t 0.0 INHBIDIR t 2.0 OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 4.7 6.0 2.5 2.6 4.4 5.9 2.5 3.9 2.5 2.6 0.2 0.2 2.8 3.0 3.0 3.2 5.8 6.2 8.6 9.2 4.5 5.5 0.3 0.4 0.0 1.3 -2 Speed Grade ...

Page 94

... CLR Tables 32 through 38 Tables 78 through 84 show EPF10K130V device internal and external timing parameters. -3 Speed Grade Max Min 1.3 0.5 1.2 0.5 0.6 0.2 0.3 0.7 0.9 1.9 0.6 0.5 0.2 0.2 0.0 0.0 2.4 2.4 4.0 4.0 4.0 4.0 in this data sheet. Note (1) -4 Speed Grade Max Min Max 1.8 0.7 1.7 0.6 0.8 0.3 0.4 1.0 1.2 2.4 0.9 0.7 0.3 0.0 3.1 3.1 4.0 4.0 Unit 2.3 ns 0.9 ns 2.2 ns 0.7 ns 1.0 ns 0.4 ns 0.5 ns 1.3 ns 1.5 ns 3.0 ns 1 3 Altera Corporation ...

Page 95

... IOCO t IOCOMB t IOSU t IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 1.3 0.4 0.3 0.0 2.6 3.3 0.0 0.0 1.7 3.5 – 8.2 4.9 4.9 – 9.6 7.9 6.2 6.2 Note (1) -4 Speed Grade Max Min Max 1 ...

Page 96

... EABSU t EABH WDSU t WDH t WASU t WAH EABOUT t EABCH t EABCL 96 -2 Speed Grade -3 Speed Grade Min Max Min 1.9 3.7 1.9 3.7 0.7 0.5 0.6 1.4 1.8 0.0 0.0 5.6 3.7 4.7 4.6 5.9 0.0 0.0 3.9 5.0 0.0 0.0 5.6 5.6 2.4 4.0 4.0 4.0 4.7 Note (1) -4 Speed Grade Max Min Max 2.4 2.4 4.7 4.7 2.4 2.4 4.7 4.7 0.9 0.9 0.6 0.6 0.8 0.8 1.8 0.0 7.1 7.1 4.7 5.9 0.0 5.0 0.0 7.1 7.1 7.1 7.1 3.1 3.1 4.0 4.7 Altera Corporation Unit ...

Page 97

... Table 81. EPF10K130V Device EAB Internal Timing Macroparameters Symbol t EABAA t EABRCCOMB t EABRCREG t EABWP t EABWCCOMB t EABWCREG t EABDD t EABDATACO t EABDATASU t EABDATAH t EABWESU t EABWEH t EABWDSU t EABWDH t EABWASU t EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade -3 Speed Grade Min Max Min 11.2 11.1 14.2 8.5 10.8 3.7 4.7 7.6 9.7 14.0 17.8 11.1 3.6 4.4 5.6 0.0 0.0 4.4 5.6 0.0 0.0 4.6 5.9 0.0 0.0 3.9 5.0 0.0 0.0 11 ...

Page 98

... Speed Grade Min Max Min 6.7 8.5 0.0 0.0 2.0 6.9 2.0 12.9 12.9 Note (1) -4 Speed Grade Max Min Max 9.0 9.5 3.0 3.1 6.3 7.4 4.6 5.1 3.0 3.1 0.6 0.8 5.3 6.5 9.5 9.7 14.8 16.2 20.1 22.7 8.6 9.5 0.8 1.0 1.0 1.2 Note (1) -4 Speed Grade Max Min Max 19.1 24.2 11.0 0.0 9.9 2.0 11.3 Note (1) -4 Speed Grade Max Min Max 10.8 0.0 8.8 2.0 10.2 16.4 19.3 16.4 19.3 Altera Corporation Unit Unit Unit ...

Page 99

... Table 86. EPF10K10A Device IOE Timing Microparameters Symbol -1 Speed Grade Min t IOC t IOCO t IOCOMB t 0.8 IOSU Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 85 through 91 show EPF10K10A device internal and external timing parameters. -2 Speed Grade Max Min ...

Page 100

... Table 86. EPF10K10A Device IOE Timing Microparameters Symbol -1 Speed Grade Min t 0.8 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB 100 Note (1) -2 Speed Grade Max Min Max 1.0 1.2 1.4 1.2 1.4 2.9 3.5 6.6 7.8 1.2 1.4 1.2 1.4 2.9 3.5 6.6 7.8 5.2 6.3 3.1 3.8 3.1 3.8 (Part Speed Grade Unit Min Max 1.3 ns 1.9 ns 1.9 ns 4.7 ns 10.5 ns 1.9 ns 1.9 ns 4.7 ns 10.5 ns 8.4 ns 5.0 ns 5.0 ns Altera Corporation ...

Page 101

... EABDATA2 t EABWE1 t EABWE2 t EABCLK t EABCO t EABBYPASS t 1.4 EABSU t 0.1 EABH 2 0.7 WDSU t 0.5 WDH t 0.6 WASU t 0.9 WAH EABOUT t 3.0 EABCH t 3.03 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 3.3 3.9 1.0 1.3 2.6 3.1 2.7 3.2 0.0 0.0 1.2 1.4 0.1 0.2 1.7 0.1 4.5 5.4 2.4 0.8 0.6 0.7 1.1 3.3 3.9 3.3 3.9 0.1 0.1 3.5 3.5 Note (1) -3 Speed Grade Min Max 5.2 1.7 4.1 4.3 0.0 1 ...

Page 102

... Min t EABAA t 8.1 EABRCCOMB t 5.8 EABRCREG t 2.0 EABWP t 3.5 EABWCCOMB t 9.4 EABWCREG t EABDD t EABDATACO t 2.4 EABDATASU t 0.0 EABDATAH t 4.1 EABWESU t 0.0 EABWEH t 1.4 EABWDSU t 0.0 EABWDH t 2.5 EABWASU t 0.0 EABWAH t EABWO 102 -2 Speed Grade Max Min Max 8.1 9.8 9.8 6.9 2.4 4.2 11.2 6.9 8.3 1.3 1.5 3.0 0.0 4.9 0.0 1.6 0.0 3.0 0.0 6.2 7.5 Note (1) -3 Speed Grade Unit Min Max 13.1 ns 13.1 ns 9.3 ns 3.2 ns 5.6 ns 14.8 ns 11.0 ns 2.0 ns 3.9 ns 0.0 ns 6.5 ns 0.0 ns 2.2 ns 0.0 ns 4.1 ns 0.0 ns 9.9 ns Altera Corporation ...

Page 103

... DRR t (2), (3) 1.6 INSU t (3) 0.0 INH t (3) 2.0 OUTCO Table 91. EPF10K10A Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 4.2 2.2 4.3 4.2 2.2 0.1 2.2 0.8 3.0 5.2 1.8 0.5 0.9 -2 Speed Grade Max Min 10.0 2.1 0.0 5.8 2.0 -2 Speed Grade ...

Page 104

... Speed Grade Max Min 0.8 0.6 1.2 0.6 1.3 0.2 0.8 0.6 0.9 1.1 0.4 0.6 0.9 1.3 0.5 0.5 3.5 3.5 -2 Speed Grade Max Min 2.2 0.3 0.2 0.5 1.7 in this data sheet. Note (1) -3 Speed Grade Max Min Max 1.1 1.5 0.7 1.0 1.5 2.0 0.6 1.0 1.5 2.0 0.3 0.4 1.0 1.3 0.8 1.0 1.1 1.4 1.3 1.7 0.6 0.7 0.7 0.9 1.4 1.7 0.6 0.8 0.6 0.8 4.0 4.0 Note (1) (Part Speed Grade Max Min Max 2.6 3.4 0.3 0.5 0.2 0.3 0.6 0.8 2.2 Unit Unit Altera Corporation ...

Page 105

... Table 93. EPF10K30A Device IOE Timing Microparameters Symbol -1 Speed Grade Min t 0.9 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Note (1) -2 Speed Grade Max Min Max 1.1 0.7 0.8 1.9 2.2 4.8 5.6 7.0 8.2 2.2 2.6 2.2 2.6 5.1 6.0 7.3 8.6 4.4 5.2 3.8 4.5 3.8 4.5 (Part ...

Page 106

... EABCLK t EABCO t EABBYPASS t 1.2 EABSU t 0.1 EABH 3 0.1 WDSU t 0.1 WDH t 0.1 WASU t 0.1 WAH EABOUT t 3.0 EABCH t 3.8 EABCL 106 -2 Speed Grade Max Min Max 5.5 6.5 1.1 1.3 2.4 2.8 2.1 2.5 0.0 0.0 1.7 2.0 0.0 0.0 1.4 0.1 4.2 5.0 4.5 0.1 0.1 0.1 0.1 3.7 4.4 3.7 4.4 0.0 0.1 3.5 4.5 Note (1) -3 Speed Grade Min Max 8.5 1.8 3.7 3.2 0.2 2.6 0.3 1.9 0.3 6.5 5.9 0.2 0.2 0.2 0.2 6.4 6.4 0.6 4.0 5.9 Altera Corporation Unit ...

Page 107

... EABRCCOMB t 5.9 EABRCREG t 3.8 EABWP t 4.0 EABWCCOMB t 9.8 EABWCREG t EABDD t EABDATACO t 2.3 EABDATASU t 0.0 EABDATAH t 3.3 EABWESU t 0.0 EABWEH t 3.2 EABWDSU t 0.0 EABWDH t 3.7 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 9.7 11.6 11.6 7.1 4.5 4.7 11.6 9.2 11.0 1.7 2.1 2.7 0.0 3.9 0.0 3.8 0.0 4.4 0.0 6.1 7.3 Note (1) -3 Speed Grade Unit Min Max 16.2 ns 16.2 ns 9.7 ns 5.9 ns 6 ...

Page 108

... Speed Grade Min Max Min 4.2 4.9 0.0 0.0 2.0 5.4 2.0 6.2 6.2 Note (1) -3 Speed Grade Max Min Max 4.4 5.1 1.5 1.9 3.6 4.5 3.5 4.6 1.5 1.9 0.1 0.2 2.4 2.7 1.4 1.9 3.8 4.6 6.2 7.3 3.8 4.1 0.4 0.5 1.1 1.4 Note (1) -3 Speed Grade Max Min Max 13.0 17.0 3.9 0.0 6.2 2.0 8.3 Note (1) -3 Speed Grade Max Min 6.8 0.0 6.2 2.0 7.5 7.5 Altera Corporation Unit Unit Unit Max ns ns 8.3 ns 9.8 ns 9.8 ns ...

Page 109

... CICO t CGEN t CGENR t CASC COMB PRE t CLR t 2 2.5 CL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 38 Tables 99 through 105 show EPF10K100A device internal and external timing parameters. -2 Speed Grade Max Min 1.0 0.8 1.4 0.4 0.6 0.2 0.4 0.6 0.7 0.9 0.2 0.6 1.0 0.5 0.3 0.3 3 ...

Page 110

... Min t IOD t IOC t IOCO t IOCOMB t 1.3 IOSU t 0.2 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB 110 -2 Speed Grade Max Min Max 2.5 2.9 0.3 0.3 0.2 0.2 0.5 0.6 1.7 0.2 1.0 1.2 2.2 2.6 4.5 5.3 6.8 7.9 2.7 3.1 2.7 3.1 5.0 5.8 7.3 8.4 5.3 6.1 4.7 5.5 4.7 5.5 Note (1) -3 Speed Grade Min Max 3.4 0.4 0.3 0.7 1.8 0.3 1.4 3.0 6.1 9.3 3.7 3.7 6.8 10.0 7.2 6.4 6.4 Altera Corporation Unit ...

Page 111

... EABDATA2 t EABWE1 t EABWE2 t EABCLK t EABCO t EABBYPASS t 1.3 EABSU t 0.4 EABH 3 2.4 WDSU t 0.2 WDH t 0.2 WASU t 0.0 WAH EABOUT t 2.5 EABCH t 3.2 EABCL Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.8 2.1 3.2 3.7 0.8 0.9 2.3 2.7 0.8 0.9 1.0 1.1 0.3 0.3 1.5 0.5 4.1 4.8 3.7 2.8 0.2 0.2 0.0 3.4 3.9 3.4 3.9 0.3 0.3 3.5 3.7 Note (1) -3 Speed Grade Min Max 2.4 4.4 1.1 3.1 1.1 1 ...

Page 112

... Min t EABAA t 6.8 EABRCCOMB t 5.4 EABRCREG t 3.2 EABWP t 3.4 EABWCCOMB t 9.4 EABWCREG t EABDD t EABDATACO t 3.7 EABDATASU t 0.0 EABDATAH t 2.8 EABWESU t 0.0 EABWEH t 3.4 EABWDSU t 0.0 EABWDH t 1.9 EABWASU t 0.0 EABWAH t EABWO 112 -2 Speed Grade Max Min Max 6.8 7.8 7.8 6.2 3.7 3.9 10.8 6.1 6.9 2.1 2.3 4.3 0.0 3.3 0.0 4.0 0.0 2.3 0.0 5.1 5.7 Note (1) -3 Speed Grade Unit Min Max 9.2 ns 9.2 ns 7.4 ns 4.4 ns 4.7 ns 12.8 ns 8.2 ns 2.9 ns 5.1 ns 0.0 ns 3.8 ns 0.0 ns 4.6 ns 0.0 ns 2.6 ns 0.0 ns 6.9 ns Altera Corporation ...

Page 113

... DRR t (2), (3) 3.7 INSU t (3) 0.0 INH t (3) 2.0 OUTCO Table 105. EPF10K100A Device External Bidirectional Timing Parameters Symbol t INSUBIDIR t INHBIDIR t OUTCOBIDIR t XZBIDIR t ZXBIDIR Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 4.8 2.0 2.4 2.6 2.0 0.1 1.5 5.5 7.0 8.5 3.9 0.2 0.4 -2 Speed Grade Max Min 12.5 4.5 0.0 5.3 2.0 -1 Speed Grade ...

Page 114

... Tables 32 through 38 Tables 106 through 112 show EPF10K250A device internal and external timing parameters. -2 Speed Grade Max Min 0.9 1.2 2.0 0.4 1.4 0.2 0.4 0.8 0.7 1.2 0.6 0.5 1.4 1.3 0.7 0.7 3.0 3.0 in this data sheet. Note (1) -3 Speed Grade Max Min Max 1.0 1.4 1.3 1.6 2.3 2.7 0.4 0.5 1.6 1.9 0.3 0.3 0.6 0.6 1.0 1.1 0.8 1.0 1.3 1.6 0.7 0.9 0.6 0.7 1.7 1.6 0.8 0.9 0.8 0.9 3.5 3.5 Unit Altera Corporation ...

Page 115

... Symbol -1 Speed Grade Min t IOD t IOC t IOCO t IOCOMB t 2.7 IOSU t 0.2 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.2 1.3 0.4 0.4 0.8 0.9 0.7 0.7 3.1 0.3 1.2 1.3 3.2 3.6 5.9 6.7 8.7 9.8 3.8 4.3 3.8 4.3 6.5 7.4 9.3 10.5 8.2 9.3 9.0 10.2 9.0 10.2 Note (1) -3 Speed Grade ...

Page 116

... EABCLK t EABCO t EABBYPASS t 3.8 EABSU t 0.7 EABH 5 1.3 WDSU t 0.1 WDH t 0.1 WASU t 0.1 WAH EABOUT t 2.5 EABCH t 5.6 EABCL 116 -2 Speed Grade Max Min Max 1.3 1.5 1.3 1.5 0.9 1.1 5.0 5.7 0.6 0.7 0.0 0.0 0.1 0.1 4.3 0.8 4.5 5.0 6.4 1.4 0.1 0.1 0.1 4.1 4.6 4.1 4.6 0.1 0.1 3.0 6.4 Note (1) -3 Speed Grade Min Max 1.7 1.7 1.3 6.7 0.8 0.0 0.2 5.0 0.9 5.9 7.5 1.7 0.2 0.2 0.2 5.5 5.5 0.2 3.5 7.5 Altera Corporation Unit ...

Page 117

... EABRCCOMB t 4.6 EABRCREG t 5.6 EABWP t 5.8 EABWCCOMB t 15.8 EABWCREG t EABDD t EABDATACO t 4.5 EABDATASU t 0.0 EABDATAH t 8.2 EABWESU t 0.0 EABWEH t 1.7 EABWDSU t 0.0 EABWDH t 0.9 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 6.1 6.8 6.8 5.1 6.4 6.6 17.8 5.7 6.4 0.7 0.8 5.1 0.0 9.3 0.0 1.8 0.0 0.9 0.0 5.3 6.0 Note (1) -3 Speed Grade Unit Min Max 8.2 ns 8.2 ns 6.1 ns 7.5 ns 7 ...

Page 118

... Speed Grade Min Max Min 9.3 10.6 0.0 0.0 2.0 8.0 2.0 10.8 10.8 Note (1) -3 Speed Grade Max Min Max 8.5 9.4 3.1 3.5 1.6 1.7 4.0 4.6 3.1 3.5 0.3 0.3 7.3 8.2 2.7 3.0 10.0 11.2 17.3 19.4 8.1 8.9 0.4 0.5 0.4 0.5 Note (1) -3 Speed Grade Max Min Max 17.0 20.0 9.4 0.0 8.9 2.0 10.4 Note (1) -3 Speed Grade Max Min 12.7 0.0 8.9 2.0 12.2 12.2 Altera Corporation Unit Unit Unit Max ns ns 10.4 ns 14.2 ns 14.2 ns ...

Page 119

... Input clock frequency (ClockBoost clock multiplication factor equals 2) CLK2 t Input clock period (ClockBoost clock multiplication factor equals 2) CLK2 Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet Tables 32 through 37 For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device ...

Page 120

... tog CCACTIVE MAX The parameters in this equation are shown below: Min Typ ( CCACTIVE ) the FLEX 10K device DC CC0 value, which depends on the device output A -------------------------- - LC MHz LE Max Unit 1 MHz 0.5 MHz 100 Altera Corporation ...

Page 121

... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet = Maximum operating frequency in MHz f MAX N = Total number of logic cells used in the device tog = Average percent of logic cells toggling at each clock LC (typically 12.5 Constant, shown in Table 114. FLEX 10K K Constant Values Device ...

Page 122

... EPF10K70 I Supply CC Current (mA 1,000 900 800 700 600 500 400 300 200 100 Frequency (MHz) 2,500 2,000 1,500 1,000 500 Frequency (MHz) 3,500 3,000 2,500 2,000 1,500 1,000 500 Frequency (MHz) Altera Corporation ...

Page 123

... I Supply CC Current (mA) 1,000 500 Frequency (MHz) EPF10K30A 400 300 I Supply CC Current (mA) 200 100 0 25 Frequency (MHz) Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet EPF10K50V I Supply CC Current (mA EPF10K10A I Supply CC Current (mA 100 EPF10K100A I Supply CC Current (mA) ...

Page 124

... I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode; normal device operation is called user mode 100 Frequency (MHz) Altera Corporation ...

Page 125

... Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet SRAM configuration elements allow FLEX 10K devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation ...

Page 126

... Embedded Programmable Logic Device Family Data Sheet. Updated General Description section Updated I/O Element section Updated SameFrame Pin-Outs section Updated Figure 16 Updated Tables 13 and 116 Added Note 9 to Table 19 Added Note 10 to Table 24 Added Note 10 to Table 28 Data Source Figure 13. Altera Corporation ...

Page 127

... Notes: Altera Corporation FLEX 10K Embedded Programmable Logic Device Family Data Sheet 127 ...

Page 128

... Innovation Drive San Jose, CA 95134 Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as (408) 544-7000 trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera http://www ...