AT89C51 ATMEL Corporation, AT89C51 Datasheet

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AT89C51

Manufacturer Part Number
AT89C51
Description
Manufacturer
ATMEL Corporation
Datasheet

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Pin Configurations
Features
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash programmable and erasable read only memory (PEROM). The device
is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set and pinout. The on-chip
Flash allows the program memory to be reprogrammed in-system or by a conven-
tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash
on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides
a highly-flexible and cost-effective solution to many embedded control applications.
(RXD) P3.0
(INT0) P3.2
(INT1) P3.3
(TXD) P3.1
Compatible with MCS-51
4K Bytes of In-System Reprogrammable Flash Memory
Fully Static Operation: 0 Hz to 24 MHz
Three-level Program Memory Lock
128 x 8-bit Internal RAM
32 Programmable I/O Lines
Two 16-bit Timer/Counters
Six Interrupt Sources
Programmable Serial Channel
Low-power Idle and Power-down Modes
(T0) P3.4
(T1) P3.5
– Endurance: 1,000 Write/Erase Cycles
P1.5
P1.6
P1.7
RST
NC
1
2
3
4
5
6
7
8
9
10
11
PQFP/TQFP
Products
33
32
31
30
29
28
27
26
25
24
23
PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
(INT0) P3.2
(INT1) P3.3
(RXD) P3.0
(TXD) P3.1
(T0) P3.4
(T1) P3.5
P1.5
P1.6
P1.7
RST
NC
(INT0) P3.2
(INT1) P3.3
(RXD) P3.0
(TXD) P3.1
(WR) P3.6
7
8
9
10
11
12
13
14
15
16
17
(RD) P3.7
(T0) P3.4
(T1) P3.5
XTAL2
XTAL1
GND
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PDIP
PLCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
39
38
37
36
35
34
33
32
31
30
29
PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
8-bit
Microcontroller
with 4K Bytes
Flash
AT89C51
Not Recommended
for New Designs.
Use AT89S51.
Rev. 0265G–02/00
1

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AT89C51 Summary of contents

Page 1

... Flash allows the program memory to be reprogrammed in-system conven- tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications. Pin Configurations PQFP/TQFP P1 ...

Page 2

... Block Diagram V CC GND RAM ADDR. REGISTER B REGISTER PSEN TIMING ALE/PROG INSTRUCTION AND REGISTER CONTROL PP RST OSC AT89C51 2 P0.0 - P0.7 PORT 0 DRIVERS PORT 0 PORT 2 RAM LATCH LATCH ACC TMP2 TMP1 ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PSW PORT 1 LATCH PORT 1 DRIVERS P1 ...

Page 3

... Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock cir- cuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning ...

Page 4

... PSEN Program Store Enable is the read strobe to external pro- gram memory. When the AT89C51 is executing code from external pro- gram memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. ...

Page 5

Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Regis- Lock Bit Protection Modes Program Lock ...

Page 6

... Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps. 1. Input the desired memory location on the address lines. ...

Page 7

... PROGRAMMING MODES ABLE 3-24 MHz RST V IH PSEN EA/V P2.6 P2.7 PP H/12V H/12V H H H/12V H H H/12V H L H/12V AT89C51 ADDR. P1 OOOOH/0FFFH P2 A11 P2.6 P2.7 P3.6 T P3.7 XTAL2 XTAL1 GND PSEN P3 PGM DATA P0 ...

Page 8

... Flash Programming and Verification Waveforms - High-voltage Mode (V P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.4 (RDY/BSY) Flash Programming and Verification Waveforms - Low-voltage Mode (V P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE/PROG EA/V PP P2.7 (ENABLE) P3.4 (RDY/BSY) AT89C51 8 PROGRAMMING ADDRESS DATA DVGL GHDX t AVGL t SHGL t GLGH EHSH t GHBL PROGRAMMING ADDRESS DATA DVGL GHDX ...

Page 9

Flash Programming and Verification Characteristics T = 0°C to 70° 5.0 10 Symbol Parameter (1) V Programming Enable Voltage PP (1) I Programming Enable Current PP 1/t Oscillator Frequency CLCL t Address Setup to PROG Low ...

Page 10

... Port Ports Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89C51 10 *NOTICE: Condition (Except EA) (Except XTAL1, RST) (XTAL1, RST 1 3 -60 µ ...

Page 11

AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics Symbol Parameter 1/t Oscillator Frequency CLCL t ALE Pulse ...

Page 12

... External Program Memory Read Cycle t LHLL ALE t AVLL PSEN PORT 0 PORT 2 External Data Memory Read Cycle t LHLL ALE PSEN RD t AVLL FROM RI OR DPL PORT 0 PORT 2 P2 A15 FROM DPH AT89C51 12 t LLIV t LLPL t PLIV t PLAZ t PXIZ t LLAX t PXIX INSTR IN t AVIV A8 - A15 ...

Page 13

External Data Memory Write Cycle t LHLL ALE PSEN WR t AVLL PORT FROM RI OR DPL PORT 2 P2 A15 FROM DPH External Clock Drive Waveforms t CHCX V - ...

Page 14

... V - 0. TEST POINTS 0 0.45V Note Inputs during testing are driven at V logic 1 and 0.45V for a logic 0. Timing measurements are made at V min. for a logic 1 and V IH logic 0. AT89C51 14 12 MHz Osc Min 1.0 700 XLXL t XHQX 0 ...

Page 15

... AT89C51-12PC AT89C51-12QC AT89C51-12AI AT89C51-12JI AT89C51-12PI AT89C51-12QI AT89C51-16AC AT89C51-16JC AT89C51-16PC AT89C51-16QC AT89C51-16AI AT89C51-16JI AT89C51-16PI AT89C51-16QI AT89C51-20AC AT89C51-20JC AT89C51-20PC AT89C51-20QC AT89C51-20AI AT89C51-20JI AT89C51-20PI AT89C51-20QI AT89C51-24AC AT89C51-24JC AT89C51-24PC AT89C51-24QC AT89C51-24AI AT89C51-24JI AT89C51-24PI AT89C51-24QI Package Type Package Operation Range 44A Commercial 44J ( 40P6 ...

Page 16

... PLANE .161(4.09) .125(3.18) .065(1.65) .110(2.79) .041(1.04) .090(2.29) .630(16.0) .590(15.0) .012(.305) .008(.203) .690(17.5) .610(15.5) AT89C51 16 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC 12.21(0.478) SQ 11.75(0.458) 0.45(0.018) 0.30(0.012) .032(.813) .026(.660) .050(1.27) TYP 10.10(0.394 ...

Page 17

... Atmel Corporation 2000. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war- ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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