CS4299 Cirrus Logic, Inc., CS4299 Datasheet
CS4299
Available stocks
Related parts for CS4299
CS4299 Summary of contents
Page 1
... S/PDIF Digital Audio Output l CrystalClear l Industrial Temperature Range Description The CS4299- ’97 2.1 compatible stereo au- dio codec designed for PC multimedia systems. Using the industry leading CrystalClear mixed signal technology, the CS4299-BQ enables the design of PC 99-compliant desktop, portable, and enter- tainment PCs. ...
Page 2
... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com CS4299-BQ CS4299-BQ DS319-BQPP2 ...
Page 3
... Phone Input ......................................................................................................... 38 6.2 Analog Outputs ................................................................................................................ 38 6.2.1 Stereo Outputs .................................................................................................... 38 6.2.2 Mono Output ....................................................................................................... 38 6.3 Miscellaneous Analog Signals ......................................................................................... 39 6.4 Power Supplies ................................................................................................................ 39 6.5 Reference Design ............................................................................................................ 39 7. SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) ................................................................... 40 8. GROUNDING AND LAYOUT ................................................................................................. 40 9. PIN DESCRIPTIONS 10. PARAMETER AND TERM DEFINITIONS ............................................................................ 47 11. REFERENCE DESIGN ....................................................................................................... 49 12. REFERENCES ...................................................................................................................... 50 13. PACKAGE DIMENSIONS .................................................................................................... 51 DS319-BQPP2 ........................................................................................................... 42 CS4299-BQ CS4299- ...
Page 4
... Figure 17. Alternate Line Output as Headphone Output ............................................................... 38 Figure 18. Stereo Output............................................................................................................... 38 Figure 19. Voltage Regulator ........................................................................................................ 39 Figure 20. S/PDIF Output.............................................................................................................. 40 Figure 21. Conceptual Layout for the CS4299-BQ........................................................................ 41 Figure 22. Pin Locations for the CS4299-BQ ................................................................................ 42 Figure 23. CS4299 Reference Design .......................................................................................... 49 LIST OF TABLES Table 1. Mixer Registers ...................................................................................................................... 19 Table 2. Analog Mixer Output Attenuation........................................................................................... 21 Table 3 ...
Page 5
... ± 0. ± 0. ± 0.25 dB A-D DR A-A A-A D-A A-D SNR D-A THD+N A-A D-A A-D (phone/mic) A-D (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) refers to the digital output pin loading. DL CS4299-BQ CS4299-BQ = 25° C, ambient =100 kΩ/ AL CS4299-BQZ Min Typ Max Unit - 1. RMS - 1. RMS - 0. RMS 0.85 1.0 1.15 V RMS 20 - 20,000 20,000 Hz 20 ...
Page 6
... AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 (AVss = DVss = 0 V) Symbol Min 0.65 x DVdd ih V 0.90 x DVdd 0.99 x DVdd -10 -10 - (Note 4) - CS4299-BQ CS4299-BQ Min Typ Max Unit -0.3 - 5.5 -0.3 - 5.5 - 0.95 1. -0.3 - AVdd + 0.3 -0.3 - DVdd + ...
Page 7
... T 10 isetup T 0 ihold T 2 irise T 2 ifall (Note orise (Note ofall T - s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk 15 setup2rst (Note off CS4299-BQ CS4299-BQ = 25° C, ambient Typ Max Unit µ µs 40.0 - µs 62.5 - µ 12.288 - MHz 81 750 kHz µs 20 ...
Page 8
... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Startup or Fault Condition BIT_CLK T orise SYNC T irise rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T T ifall T sync_high sync_low T sync_period Figure 3. Clocks CS4299-BQ CS4299-BQ T rst2clk T ifall DS319-BQPP2 ...
Page 9
... SDATA_OUT Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK DS319-BQPP2 isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don't Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode CS4299-BQ CS4299-BQ T ihold T T sync_pr4 sync2clk Hi ...
Page 10
... V. See Section 3, AC Link Frame Definition, for detailed AC-link information. 2.2 Control registers The CS4299-BQ contains a set of AC ’97 compli- ant control registers and a set of Cirrus Logic de- fined control registers. These registers control the basic functions and features of the CS4299-BQ. Read accesses of the control registers by the AC ’ ...
Page 11
... In addition, the Intel (ICHx) specification requires support for five more audio rates (8, 11.025, 16, 22.05, and 32). The CS4299 supports all these rate, as shown in Table 7 on page 29. 2.4 Output Mixer The CS4299-BQ has two output mixers, illustrated in Figure 8 ...
Page 12
... ANALOG STEREO 3D OUTPUT OUTPUT MIXER MIXER STEREO TO MONO MIXER Σ Σ 1/2 Σ Σ STEREO TO MONO MIXER 1/2 Figure 8. Mixer Diagram CS4299-BQ CS4299-BQ BYPASS BUFFER DAC DIRECT MASTER MODE VOLUME OUTPUT MUTE BUFFER ALT LINE VOLUME OUTPUT MUTE BUFFER MONO OUT ...
Page 13
... On the next rising edge of BIT_CLK, the first bit of Slot 0 is driven by the controller on the SDATA_OUT pin. On the next falling edge of BIT_CLK, the CS4299-BQ latches this data in, as the first bit of the frame. 20.8 µs (48 kHz) ...
Page 14
... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4299-BQ from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4299-BQ is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
Page 15
... See Figure 9 for bit frame positions. RI[6:0] Register Index. The RI[6:0] bits contain the 7-bit register index to the AC ’97 registers in the CS4299-BQ. All registers are defined at word addressable boundaries. The RI0 bit must be ‘clear’ to access CS4299-BQ registers. 3.1.3 Command Data Port (Slot 2) ...
Page 16
... The data format for the input frame is very similar to the output frame. Figure 9 on page 13 il- lustrates the serial port timing. The PCM capture data from the CS4299-BQ is shifted out MSB first in the most significant 18 bits of each slot. The least significant 2 bits in each slot will be ‘cleared’. If the host requests PCM data from the AC ’ ...
Page 17
... Audio ID Register (Index 28h) and the SM[1:0] and AMAP bits in the AC Mode Control Reg- ister (Index 5Eh). The definition of each slot can be found in Table 8 on page 30. DS319-BQPP2 CS4299-BQ CS4299- Reserved ...
Page 18
... SYNC assertion Upon loss of synchronization with the controller, the CS4299-BQ will ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the CS4299-BQ will ignore all register reads and writes and will discontinue the transmission of PCM capture data ...
Page 19
... Fs L CC6 CC5 CC4 CC3 CC2 CC1 CC0 Table 1. Mixer Registers CS4299-BQ CS4299- Default 0 0 ID4 MR5 MR4 MR3 MR2 MR1 MR0 0 MR5 MR4 MR3 MR2 MR1 MR0 0 MM5 MM4 MM3 MM2 MM1 MM0 ...
Page 20
... This value corresponds attenuation and Mute ‘set’ D10 SE0 0 ID8 ID7 0 D10 ML2 ML1 ML0 0 0 CS4299-BQ CS4299- ID4 MR5 MR4 MR3 MR2 MR1 DS319-BQPP2 ...
Page 21
... Table 2. Analog Mixer Output Attenuation D10 CS4299-BQ CS4299- MR5 MR4 MR3 MR2 MR1 MM5 MM4 MM3 MM2 MM1 D0 MR0 D0 MM0 21 21 ...
Page 22
... Default 8008h. This value corresponds gain and Mute ‘set’ D10 D10 CS4299-BQ CS4299- PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 DS319-BQPP2 GN0 ...
Page 23
... 20dB Gain Level GN[4:0] 20dB = 0 20dB = 1 00000 +12.0 dB +32.0 dB 00001 +10.5 dB +30.5 dB … … ... 00111 +1.5 dB +21.5 dB 01000 0.0 dB +20.0 dB 01001 -1.5 dB +18.5 dB … … ... 11111 -34.5 dB -14.5 dB Table 3. Microphone Input Gain Values CS4299-BQ CS4299- GN4 GN3 GN2 GN1 D0 GN0 23 23 ...
Page 24
... Table 4. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 5. Stereo Volume Register Index CS4299-BQ CS4299- GR4 GR3 GR2 GR1 DS319-BQPP2 D0 GR0 ...
Page 25
... Aux Input 100 Line Input 101 Stereo Mix 110 Mono Mix 111 Phone Input Table 6. Input Mux Selection D10 GL2 GL1 GL0 0 0 CS4299-BQ CS4299- SR2 SR1 GR3 GR2 GR1 D0 SR0 ...
Page 26
... General Purpose Register (Index 20h). Default 0000h. This value corresponds to minimum spatial enhancement added to the output signal. 26 D10 MIX MS LPBK 0 D10 CS4299- stereo enhancement. This ...
Page 27
... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular section of the CS4299-BQ is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the powerdown functions ...
Page 28
... ID[1:0] Codec Configuration ID. When ID[1:0] = 00, the CS4299-BQ is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4299- secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins. AMAP Audio Slot Mapping. The AMAP bit indicates whether the optional AC ’97 2.1 compliant AC-link slot to audio DAC mapping is supported ...
Page 29
... AC44 48,000 BB80 Bh, Ch, Dh, Eh Table 7. Standard Sample Rates D10 SR9 SR8 SR7 SR6 CS4299-BQ CS4299- SR5 SR4 SR3 SR2 SR1 ...
Page 30
... Loss of SYNC Mute Enable. The LOSM bit controls the loss of SYNC mute function. If this bit is ‘set’, the CS4299-BQ will mute all analog outputs for the duration of loss of SYNC. If this bit is ‘cleared’, the mixer will continue to function normally during loss of SYNC. The CS4299-BQ expects to sample SYNC ‘ ...
Page 31
... When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4299-BQ. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘ ...
Page 32
... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character. DID[2:0] Device ID. With a value of DID[2:0] = 011, these bits specify the audio codec is a CS4299. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
Page 33
... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 7. Once deasserted, all of the CS4299-BQ registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. DS319-BQPP2 5.1.2 Warm AC ’ ...
Page 34
... SDATA_OUT in their normal capacities. Either a Cold Reset or a Warm Reset is required to restore Register operation to the CS4299-BQ. A Cold Reset will re- store all mixer registers to their power-on default values. A Warm Reset will not alter the values of any mixer register, except clearing the PR4 bit in Powerdown Control/Status Register (Index 26h) ...
Page 35
... Table 12. Powerdown PR Function Matrix I (mA) I DVdd DVdd [DVdd=3.3 V] [DVdd=5 V] 29.1 50.2 1 30.1 49.4 24.5 43.4 21.0 38.1 22.1 39.6 22.1 39.9 18.9 34.8 19.3 35.5 11 µA 27 µA 24.5 43.4 11 µA 27 µ DVdd/Rload/2 DVdd CS4299-BQ CS4299-BQ AC Internal Link Clock Off • • • • • (mA) I (mA) AVdd 37.9 37.9 37.9 29.0 31.3 10.7 45 µA 37.9 45 µA 36.2 450 µ ...
Page 36
... AN165: CS4297A/CS4299 EMI Reduction Techniques [5]. 6.1 Analog Inputs All analog inputs to the CS4299-BQ, including CD_GND, should be capacitively coupled to the input pins. Unused analog inputs should be tied to- gether and connected through a capacitor to analog ground or tied to the Vrefout pin directly. The max- ...
Page 37
... The design also sup- ports the recommended advanced frequency re- sponse for voice recognition as specified in PC 99. Note the microphone input to the CS4299-BQ has an integrated pre-amplifier. Using the 20dB bit in the Microphone Volume Register (Index 0Eh) the pre-amplifier gain can be set dB. ...
Page 38
... Figure 16 shows a design for a modem connection where the output is fed from the CS4299-BQ MONO_OUT pin through a divider. The divider ratio shown does not attenuate the sig- nal, providing an output voltage lower output voltage is desired, the resistors can be replaced with appropriate values, as long as the to- tal load on the output is kept greater than 10 kΩ ...
Page 39
... The analog power pins, AVdd1 and AVdd2, supply power to all the analog circuitry on the CS4299-BQ. The +5 V analog supply should be generated from a linear voltage regulator (7805 type) connected to a +12 V supply. This helps iso- late the analog circuitry from noise typically found digital supplies ...
Page 40
... the CS4299-BQ and any other external analog circuitry. All analog components and traces should be located over the analog ground plane and all dig- ital components and traces should be located over the digital ground plane. The common connection point between the two ...
Page 41
... Via to +5VA 0.1 µF Y5V AVss2 DVdd1 Via to +5VD or +3.3VD Figure 21. Conceptual Layout for the CS4299-BQ DS319-BQPP2 Vrefout to via 1000 pF NPO AFLT1 AFLT2 REFFLT AVdd2 Analog Via to Analog Ground Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF DVss1 Y5V 0.1 µF DVss2 Y5V Via to +5VD or +3 ...
Page 42
... SDATA_IN DVdd2 SYNC RESET# PC_BEEP Figure 22. Pin Locations for the CS4299-BQ CS4299-BQ CS4299-BQ LINE_OUT_R 36 LINE_OUT_L 35 FLTO 34 FLTI 33 FLT3D 32 BPCFG 31 AFLT2 30 AFLT1 29 Vrefout 28 ...
Page 43
... AC-coupled, with separate AC-coupling caps, to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4299-BQ intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry ...
Page 44
... VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4299-BQ intended to be used for the audio signal output of a video device. The maximum allowable input internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or both AC-coupled, with separate AC-coupling caps, to analog ground ...
Page 45
... Analog Reference, Filters, and Configuration REFFLT - Internal Reference Voltage, Input, Pin 27 This signal is the voltage reference used internal to the CS4299-BQ. A 0.1 µF and a 1.0 µF (must not be larger than 1 µF) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin. ...
Page 46
... Power Supplies DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4299-BQ. These pins can be tied digital or to +3.3 V digital. The CS4299-BQ and controller AC-link should share a common digital supply DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4299-BQ ...
Page 47
... AC ’97 Registers or Codec Registers Refers to the 64-field register map defined in the AC ’97 Specification. ADC Refers to a single Analog-to-Digital converter in the CS4299-BQ. “ADCs” refers to the stereo pair of Analog-to-Digital converters. The CS4299-BQ ADCs have 18-bit resolution. Codec Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4299-BQ ...
Page 48
... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4299-BQ operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
Page 49
... REFERENCE DESIGN GND 2 DS319-BQPP2 + + AVdd2 AVdd1 AVss2 AVss1 XTL_OUT XTL_IN DVdd2 FLTO DVdd1 FLTI CS4299-BQ CS4299- ...
Page 50
... Version 6.0, February 1998 3) Cirrus Logic, AN22: Overview of Digital Audio Interface Data Structures, Version 2.0, February 1998 4) Cirrus Logic, AN134: AES and S/PDIF Recommended Transformers, Version 2, April 1999 5) Cirrus Logic, AN165: CS4297A/CS4299 EMI Reduction Techniques, Version 1.0, September 1999 ® 6) Intel , Audio Codec ’97 Component Specification, Revision 2.1, May 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm ® ...
Page 51
... Controlling dimension is mm. JEDEC Designation: MS022 DS319-BQPP2 ∝ L INCHES NOM MAX 0.055 0.063 0.004 0.006 0.009 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° CS4299-BQ CS4299- MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 8.70 9.0 BSC 9.30 6.90 7.0 BSC 7.10 0.40 0.50 BSC 0.60 0.45 0.60 0.75 0.00° ...
Page 52
...