CS4201 Cirrus Logic, Inc., CS4201 Datasheet
CS4201
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CS4201 Summary of contents
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... I S Serial Digital Outputs Enable Cost Effective Six Channel Applications Description The CS4201 ’97 2.1 compliant stereo audio co- dec designed for PC multimedia systems. It uses industry leading CrystalClear signal technology. This advanced technology and these features are designed to help enable the design and PC 2001 compliant high-quality audio systems for desktop, portable, and entertainment PCs ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 ......................................................19 .............................................................................................22 CS4201 DS483PP3 ...
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... MHz Crystal Operation ..................................................................................48 9.3 Secondary Codec Operation ..................................................................................... 48 10. ANALOG HARDWARE DESCRIPTION ......................................................................... 50 10.1Analog Inputs ............................................................................................................50 10.1.1 Line Inputs ................................................................................................. 50 10.1.2 CD Input ..................................................................................................... 50 10.1.3 Microphone Inputs ..................................................................................... 51 10.1.4 PC Beep Input ............................................................................................ 51 10.1.5 Phone Input ................................................................................................ 51 10.2Analog Outputs ......................................................................................................... 52 10.2.1 Stereo Outputs ........................................................................................... 52 10.2.2 Mono Output .............................................................................................. 52 10.3Miscellaneous Analog Signals ..................................................................................52 10.4Power Supplies ......................................................................................................... 53 10.5Reference Design ..................................................................................................... 53 11. GROUNDING AND LAYOUT ........................................................................................ 54 DS483PP3 CS4201 3 ...
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... PIN DESCRIPTIONS Audio I/O Pins .................................................................................................................57 Analog Reference, Filter, and Configuration Pins ...........................................................58 AC-Link Pins ...................................................................................................................59 Clock and Configuration Pins ..........................................................................................60 Misc. Digital Interface Pins ..............................................................................................60 Power Supply Pins ..........................................................................................................61 13. PARAMETER AND TERM DEFINITIONS ......................................................................62 14. REFERENCE DESIGN 15. REFERENCES ................................................................................................................65 16. PACKAGE DIMENSIONS ...............................................................................................66 4 ..................................................................................................56 .................................................................................................64 CS4201 DS483PP3 ...
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... Figure 23. Modem Connection .........................................................................................51 Figure 24. Line Out and Headphone Out Setup ...............................................................52 Figure 25. Line Out/Headphone Out Setup ...................................................................... 52 Figure 26. +5V Analog Voltage Regulator ........................................................................ 53 Figure 27. Conceptual Layout for the CS4201 when in XTAL or OSC Clocking Modes .. 55 Figure 28. Pin Locations for the CS4201.......................................................................... 56 Figure 29. CS4201 Reference Design.............................................................................. 64 DS483PP3 ...
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... Table 10. Slot Mapping for the CS4201...........................................................................35 Table 11. Serial Data Format Selection ............................................................................38 Table 12. Device ID with Corresponding Part Number .....................................................39 Table 13. Serial Data Formats and Compatible DACs for the CS4201 ...........................41 Table 14. Powerdown PR Bit Functions ...........................................................................46 Table 15. Powerdown PR Function Matrix for the CS4201 ..............................................47 Table 16. Power Consumption by Powerdown Mode for the CS4201..............................47 Table 17 ...
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... A-D A-D A-D A-D A-D D-A D-A (Note ± 0 ± 0 ± 0.5 dB A-D DR A-A A-A D-A A-D SNR D-A THD+N A-A A-A D-A (all inputs) A-D (Note 4) (Note 4) (Note 4) refers to the digital output pin loading. DL CS4201 = 25° C, ambient =100 kΩ/ AL CS4201-JQ Min Typ Max 0.91 1.00 - 0.91 1.00 - 0.283 0.315 - 0.091 0.10 - 0.0283 0.0315 - 0.91 1.0 1. 20,000 20 - 20,000 20 - 20,000 ...
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... AVss2 = DVss1 = DVss2 = 0 V) +3.3 V Digital +5 V Digital Analog (Supplies, Inputs, Outputs) (Except Supply Pins) (Except Supply Pins) (Power Applied) (AVss1 = AVss2 = DVss1 = DVss2 = 0 V) Symbol +3.3 V Digital DVdd1, DVdd2 +5 V Digital DVdd1, DVdd2 Analog AVdd1, AVdd2 CS4201 CS4201-JQ Min Typ Max 730 - - 0 ...
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... Output buffer drive current BIT_CLK, SPDO/SDO2 SDATA_IN, EAPD/SCLK GPIO0/LRCLK, GPIO1/SDOUT DS483PP3 (AVss = DVss = 0 V) Symbol Min 2. 3. -10 - (Note 3. 4. -10 - (Note 4) - CS4201 Typ Max Unit - 0. 3. 0.03 0. µ µ 0. 4. 0.03 0. µ ...
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... T clk_high T clk_low F sync T sync_period T sync_high T sync_low isetup T ihold T irise T ifall (Note 4) T orise (Note 4) T ofall T s2_pdown T 1.0 sync_pr4 T 162.8 sync2clk setup2rst (Note 4) T off CS4201 = 25° C, ambient Typ Max Unit - - µs - 4.0 - µs - 4.0 - µ 62.5 - µ µs - 12.288 - MHz - 81 750 ...
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... BIT_CLK RESET# Vdd BIT_CLK SYNC CODEC_READY Figure 2. Codec Ready from Start-up or Fault Condition BIT_CLK T orise SYNC T irise DS483PP3 T rst_low T vdd2rst# Figure 1. Power Up Timing T sync2crd clk_high clk_low clk_period T ifall T T sync_high sync_low T sync_period Figure 3. Clocks CS4201 T rst2clk T ifall 11 ...
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... Write to 0x20 SDATA_IN SYNC RESET# SDATA_OUT, SYNC SDATA_IN, BIT_CLK isetup Figure 4. Data Setup and Hold Slot 2 Data PR4 Don’t Care T s2_pdown Figure 5. PR4 Powerdown and Warm Reset T setup2rst T off Figure 6. Test Mode T ihold T T sync_pr4 sync2clk Hi-Z CS4201 DS483PP3 ...
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... During each au- dio frame, data is passed bi-directionally between the CS4201 and the controller. The input frame is driven from the CS4201 on the SDATA_IN line. The output frame is driven from the controller on the SDATA_OUT line ...
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... Sample Rate Converters The sample rate converters (SRC) provide high ac- curacy digital filters supporting sample frequencies other than 48 kHz to be captured from the CS4201 or played from the controller. AC ’97 requires sup- port for two audio rates (44.1 and 48 kHz). In addi- ® tion, the Intel ...
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... PATH 3D Σ Σ Σ ANALOG STEREO 3D OUTPUT OUTPUT MIXER MIXER STEREO TO MONO MIXER Σ 1/2 Σ STEREO TO MONO MIXER 1/2 Figure 8. CS4201 Mixer Diagram CS4201 DAC DIRECT MASTER MODE VOLUME OUTPUT MUTE BUFFER HEADPHONE VOLUME HEADPHONE OUT HEADPHONE MUTE AMPLIFIER MONO OUT MONO ...
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... The first bit position in a new se- rial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4201 (on the falling edge of BIT_CLK), both devices are syn- chronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame’ ...
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... AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin to the CS4201 from the AC ’97 controller. Figure 9 illustrates the serial port timing. The PCM playback data being passed to the CS4201 is shifted out MSB first in the most significant bits of each slot. Any PCM data from the AC ’ ...
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... Not Implemented GPIO[1:0] GPIO Pin Control. The GPIO[1:0] bits control the CS4201 GPIO pins configured as outputs. Write accesses using GPIO pin control bits configured at outputs will be reflected on the GPIO pin output on the next AC-link frame. Write accesses using GPIO pin control bits configured as inputs will have no effect and are ignored. If the GPOC bit in the Misc. Crystal Control Reg- ister (Index 60h) is ‘ ...
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... AC-Link Serial Data Input Frame In the serial data input frame, data is passed on the SDATA_IN pin from the CS4201 to the AC ’97 con- troller. The data format for the input frame is very similar to the output frame. Figure 9 on page 16 illus- trates the serial port timing. ...
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... GPIO[1:0] GPIO Pin Status. The GPIO[1:0] bits reflect the status of the CS4201 GPIO pins configured as inputs. The pin status of GPIO pins configured as outputs will be reflected back on the GPIO[1:0] bits of input Slot 12 in the next frame. The output GPIO pins are controlled by the GPIO[1:0] pin control bits in output Slot 12 ...
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... BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the controller, the CS4201 will mute all analog outputs and ‘clear’ the Codec Ready bit in the serial data input frame until two valid frames are detected. During this de- ...
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... Fs L CC6 CC5 CC4 CC3 Table 1. Register Overview for the CS4201 CS4201 ID4 MR5 MR4 MR3 MR2 MR1 0 MR5 MR4 MR3 MR2 MR1 0 MM5 ...
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... The data in this register is read-only data. Any write to this register causes a Register Reset of the audio control (Index 00h - 3Ah) and Cirrus Logic defined (Index 5Ah - 7Ah) registers. A read from this register returns configuration information about the CS4201. 4.2 Analog Mixer Output Volume Registers (Index 02h - 04h) ...
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... This value corresponds attenuation and Mute ‘set’. 24 D10 D10 D10 CS4201 MM5 MM4 MM3 MM2 MM1 PV3 PV2 PV1 PV0 GN4 GN3 GN2 GN1 DS483PP3 ...
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... Gain Level 10dB = 0, 10dB = 1, 10dB = 0, 20dB = 0 20dB = 0 20dB = 1 +12.0 dB +22.0 dB +32.0 dB +10.5 dB +20.5 dB +30.5 dB … ... ... +1.5 dB +11.5 dB +21.5 dB 0.0 dB +10.0 dB +20.0 dB -1.5 dB +8.5 dB +18.5 dB … ... ... -34.5 dB -24.5 dB -14.5 dB Table 3. Microphone Input Gain Values CS4201 GN4 GN3 GN2 GN1 10dB = 1, 20dB = 1 +42.0 dB +40.5 dB ... +31.5 dB +30.0 dB +28.5 dB ... -4 GN0 25 ...
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... Table 4. Analog Mixer Input Gain Values Register Index Function 10h Line In Volume 12h CD Volume 14h Video Volume 16h Aux Volume 18h PCM Out Volume Table 5. Analog Mixer Input Gain Register Index GR4 GR3 GR2 CS4201 D1 D0 GR1 GR0 DS483PP3 ...
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... Phone Input Table 6. Input Mux Selection D10 GL2 GL1 GL0 0 0 Gx4 - Gx0 Gain Level 1111 +22.5 dB … … 0001 +1.5 dB 0000 0 dB Table 7. Record Gain Values CS4201 SR2 SR1 GR3 GR2 GR1 D0 SR0 ...
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... When S[3:0] = 1111, maximum spatial enhancement is added. Default 0000h. This value corresponds to minimum spatial enhancement. 28 D10 MIX MS LPBK 0 D10 CS4201 ® 3D stereo enhancement. This DS483PP3 ...
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... The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec- tion of the CS4201 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must be checked before writing to any mixer registers. See Section 8, Power Management , for more information on the powerdown functions ...
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... ID[1:0] Codec Configuration ID. These bits indicate the current codec configuration. When ID[1:0] = 00, the CS4201 is the primary audio codec. When ID[1:0] = 01, 10, or 11, the CS4201 is a secondary audio codec. The state of the ID[1:0] bits is determined at power-up from the ID[1:0]# pins and the current clocking scheme, see Table 17 on page 49. ...
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... If VRA = 0, writes to the register are ignored and the register will always read BB80h. Sample Rate (Hz) 8,000 11,025 16,000 22,050 32,000 44,100 48,000 Table 8. Directly Supported SRC Sample Rates for the CS4201 DS483PP3 D10 SR9 SR8 SR7 ...
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... Default x000h. This value indicates no supported modem functions. The Extended Modem ID Register (Index 3Ch read/write register that identifies the CS4201 modem capabilities. Writing any value to this location issues a reset to modem registers (Index 3Ch-54h) , including GPIO registers (Index 4Ch - 54h) . Audio registers are not reset by a write to this location. ...
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... CMOS Drive 0 1 Output Open Drain 1 0 Input Active Low 1 1 Input Active High (default) Table 9. GPIO Input/Output Configurations D10 CS4201 GP1 :0] bits define the GPIO GS1 D0 GP0 ...
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... AC-link wakeup if and only if the AC-link was powered down. Once the controller has re-established communication with the CS4201 following a Warm Reset, it will continue to signal the wakeup event through the GPIO_INT bit of input Slot 12 until the AC ’97 controller clears the inter- rupt-causing bit in the GPIO Pin Status Register (Index 54h) ...
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... DACs. If this bit is ‘set’, alternate (independent) slots will be routed to the S/PDIF transmitter. The alternate slots are the same as the SDO2 slots in Table 10. SM[1:0] Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4201 when the AMAP bit is ‘cleared’. Refer to Table 10 for the slot mapping configurations. Default ...
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... Force Cold Reset. The CRST bit is used as an override to the New Warm Reset behavior defined during PR4 powerdown. If this bit is ‘set’, an active RESET# signal will force a Cold Reset to the CS4201 during a PR4 powerdown. GPOC General Purpose Output Control. The GPOC bit specifies the mechanism by which the status of a General Purpose Output pin can be controlled. If this bit is ‘ ...
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... When ‘set’, the sampling frequency is 44.1 kHz. The actual rate at which S/PDIF data are being transmitted solely depends on the master clock frequency of the CS4201. The Fs bit is merely an indicator to the S/PDIF receiver. L Generation Status. The L bit is mapped to bit 15 of the channel status block. For category codes 001xxxx, 0111xxx and 100xxxx, a value of ‘ ...
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... Default 0000h 38 D10 SDF1 SDF0 Serial Data Format Left Justified 1 0 Right Justified, 20-bit data 1 1 Right Justified, 16-bit data Table 11. Serial Data Format Selection CS4201 SDO2 SDSC SDF1 SDF0 DS483PP3 D0 ...
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... Third Character of Vendor ID. With a value of T[7:0] = 59h, these bits define the ASCII ‘Y’ character. DID[2:0] Device ID. With a value of DID[2:0] = 100, these bits specify the audio codec is a CS4201. REV[2:0] Revision. With a value of REV[2:0] = 001, these bits specify the audio codec revision is ‘A’. ...
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... SCLK is internally derived from MCLK and LRCLK. In this case, SCLK generation in the CS4201 is optional. A feature has been designed into the CS4201 that allows the phase of the internal DACs to be re- versed. This DAC phase reversal is controlled by the DPC bit in the Misc. Crystal Control Register ...
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... Table 13. Serial Data Formats and Compatible DACs for the CS4201 DS483PP3 will (BIT_CLK/4). Serial data is transi- tioned by the CS4201 on the falling edge of SCLK and latched by the DACs on the next rising edge. Serial data is shifted out MSB first in all supported formats, but LRCLK polarity as well as data justi- fication, alignment, and resolution vary ...
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... Figure 11. Serial Data Format LSB M SB Figure 12. Serial Data Format 1 (Left Justified CS4201 Right Channel + LSB 2 S) Right Channel + LSB Right Channel ...
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... SONY/PHILIPS DIGITAL INTERFACE (S/PDIF) The S/PDIF digital output is used to interface the CS4201 to consumer audio equipment external to the PC. This output provides an interface for stor- ing digital audio data or playing digital audio data to digital speakers. Figure 15 illustrates the circuits R 1 S/PDIF_OUT SPDO/SDO2 DVdd 3 ...
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... EXCLUSIVE FUNCTIONS Some of the digital pins on the CS4201 have mul- tiplexed functionality. These functions are mutual- ly exclusive and cannot be requested at the same time. The following pairs of functions are mutually exclusive: • GPIO and Serial Data Port (GPIO0 pin is shared with LRCLK pin and GPIO1 pin is shared with SDOUT pin) • ...
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... This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 10. Once de-assert- ed, all of the CS4201 registers will be reset to their default power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. 8.1.2 ...
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... The PR[6:0] bits in this register control the internal powerdown states of the CS4201. Power- down control is available for individual subsections of the CS4201 by asserting any PRx bit or any com- bination of PRx bits. All powerdown states except PR4 and PR5 can be resumed by clearing the cor- responding PRx bit ...
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... AC-Link off (PR4) Internal Clocks off (PR5) Digital off (PR4+PR5) PR3+PR4+PR5 RESET Table 16. Power Consumption by Powerdown Mode for the CS4201 1 Assuming standard resistive load for transformer coupled coaxial S/PDIF output (Rload = 292 Ohm, DVdd = 3.3 V) (Rload = 415 Ohm, DVdd = 5 V). General HP_OUT_L, HP_OUT_R driving 4 Vpp into 32 Ohm resistive load. ...
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... MHz BIT_CLK output; see Table 17 on page 49 for additional de- tails. In PLL mode, the CS4201 is configured as a primary codec independent of the state of the ID[1:0]# pins. If 24.576 MHz is chosen as the ex- ternal clock input (ID[1:0]# inputs both pulled high or left floating), the PLL is disabled and the clock is used directly ...
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... External 48.000 0 XTAL 24.576 1 BIT_CLK 12.288 2 BIT_CLK 12.288 3 BIT_CLK 12.288 Table 17. Clocking Configurations for the CS4201 CS4201 PLL Application Notes Active No clock generator driving XTL_IN Yes external clock source driving XTL_IN Yes loop filter connected to XTL_OUT Yes No crystal connected to XTL_IN, XTL_OUT ...
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... Replicate this circuit for the Line, Video and Aux inputs. This design attenuates the input by 6 dB, bringing the signal from the PC 99 specified the CS4201 maximum allowed 1 V RMS 10.1.2 CD Input The CD line-level input has an extra pin, CD_GND, providing a pseudo-differential input 50 for both CD_L and CD_R ...
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... PC Beep Input The PC_BEEP input is useful for mixing the output of the “beeper” (timer chip), provided in most PCs, with the other audio signals. When the CS4201 is held in reset, PC_BEEP is passed directly to the line output. This allows the system sounds or “beeps” available before the AC ’97 interface has been activated ...
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... Electrolytic capacitors should not be used. No other connection should be made, as any coupling onto this pin will degrade the analog performance of the CS4201. Likewise, digital signals should be kept away from REFFLT for similar reasons. Line Out ...
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... One analog power pin, AVdd2, supplies power to the headphone amplifier on the CS4201. The other analog power pin, AVdd1, supplies pow the rest of the CS4201 analog circuitry. The +5 V analog supply should be generated from a voltage regulator (7805 type) connected to a +12 V supply ...
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... GROUNDING AND LAYOUT Figure 27 shows the conceptual layout for the CS4201 in XTAL or OSC clocking modes. The de- coupling capacitors should be located physically as close to the pins as possible. Also, note the connec- tion of the REFFLT decoupling capacitors to the ground return trace connected directly to the ground return pin, AVss1 ...
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... Via to +5VA 0.1 µF Y5V AV ss2 DVdd1 Via to +5VD or +3.3VD Figure 27. Conceptual Layout for the CS4201 when in XTAL or OSC Clocking Modes DS483PP3 Vrefout toVia 1000 pF NPO AFLT1 AFLT2 REFFLT AVdd2 Via to Analog Ground Digital Ground Via to Digital Ground Pin 1 0.1 µF DVss1 Y5V 0.1 µ ...
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... DVss2 7 8 SDATA_IN DVdd2 9 10 SYNC RESET# 11 PC_BEEP CS4201 Figure 28. Pin Locations for the CS4201 CS4201 LINE_OUT_R 35 LINE_OUT_L 34 FLTO 33 FLTI 32 FLT3D 31 HPCFG 30 AFLT2 29 AFLT1 28 Vrefout 27 REFFLT 26 AVss1 25 AVdd1 DS483PP3 ...
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... AC-coupled to analog ground. CD_L, CD_R - Analog CD Source, Inputs, Pins 18 and 20 These inputs form a stereo input pair to the CS4201 intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input inputs are internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. ...
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... This analog input is used to remove common mode noise from Red Book CD audio signals. The impedance on the input signal path should be one half the impedance on the CD_L and CD_R input paths. This pin requires AC-coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC-coupled to analog ground. 58 CS4201 DS483PP3 ...
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... VIDEO_L, VIDEO_R - Analog Video Audio Source, Inputs, Pins 16 and 17 These inputs form a stereo input pair to the CS4201 intended to be used for the audio signal output of a video device. The maximum allowable input internally biased at the Vrefout voltage reference and require AC-coupling to external circuitry. If these inputs are not used, they should both be connected to the Vrefout pin or AC-coupled to analog ground ...
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... SDATA_IN - AC-Link Serial Data Output Stream from AC ’97, Output, Pin 8 This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4201 on the rising edge of BIT_CLK. A series terminating resistor of 47 Ω should be connected on this signal close to the CS4201. ...
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... Section 9, Clocking , for additional details. ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46 These pins select the Codec ID for the CS4201, as well as determine the rate of the incoming clock in PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up to the digital supply voltage and should be left floating for logic ‘ ...
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... Power Supply Pins DVdd1, DVdd2 - Digital Supply Voltage, Pins 1 and 9 Digital supply voltage for the AC-link section of the CS4201. These pins can be tied digital or to +3.3 V digital. The CS4201 and controller’s AC-link should share a common digital supply. DVss1, DVss2 - Digital Ground, Pins 4 and 7 Digital ground connection for the AC-link section of the CS4201 ...
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... Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the codec is the CS4201. DAC Refers to a single Digital-to-Analog converter in the CS4201. “DACs” refers to the stereo pair of Digital-to-Analog converters. The CS4201 DACs have 20-bit resolution defined as dB relative to full-scale. The “ ...
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... SRC Sample Rate Converter. Converts data derived at one sample rate to a differing sample rate. The CS4201 operates at a fixed sample frequency of 48 kHz. The internal sample rate converters are used to convert digital audio streams playing back at other frequencies to 48 kHz. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level ...
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... REFERENCE DESIGN 2 GND + DS483PP3 + + + 38 AVdd2 25 AVdd1 42 AVss2 26 AVss1 1 DVdd1 9 DVdd2 + + + + + CS4201 3 XTL_OUT 2 XTL_IN 34 FLTO 33 FLTI + 65 ...
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... Audio Codec ’97 Component Specification, Revision 2.1, May 1998 http://developer.intel.com/ial/scalableplatforms/audio/index.htm ® 7) Microsoft , PC 99 System Design Guide, Version 1.0, July 1999 http://www.microsoft.com/hwdev/desguid/ ® 8) Microsoft , PC 2001 System Design Guide, Version 0.9, August 2000 http://www.pcdesguide.org/pc2001/default.htm ® 9) Intel 82801AA (ICH) and 82801AB (ICH0) I/O Controller Hub, June 1999 http://developer.intel.com/design/chipsets/datashts/290655.htm4 66 CS4201 DS483PP3 ...
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... JEDEC Designation: MS022 DS483PP3 ∝ L INCHES NOM MAX 0.055 0.063 0.004 0.006 0.009 0.011 0.354 0.366 0.28 0.280 0.354 0.366 0.28 0.280 0.020 0.024 0.24 0.030 4° 7.000° CS4201 A A1 MILLIMETERS MIN NOM MAX --- 1.40 0.05 0.10 0.17 0.22 8.70 9.0 BSC 6.90 7.0 BSC 8.70 9.0 BSC 6.90 7.0 BSC 0.40 0.50 BSC 0.45 0.60 0.00° 4° 7.00° 1.60 0.15 0.27 9.30 7 ...
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