CS62180B-IL Cirrus Logic, Inc., CS62180B-IL Datasheet
CS62180B-IL
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CS62180B-IL Summary of contents
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... CS61574A, and CS61575 Line Interface Units. Applications T1 Line Cards ISDN Primary Rate Line Cards Ordering Information: CS62180A-IP 40 Pin Plastic DIP CS62180A-IL 44 Pin PLCC CS62180B-IP 40 Pin Plastic DIP CS62180B-IL 44 Pin PLCC TFSYNC TSER TABCD Transmit Timing Data F-Bit Data Selector ...
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... ° 5.0 V 10%; GND = Symbol (Note (Note OUT = 1.6 mA) V (Note 6) I (Note 7) I (Note 5.25 to 5.5 V and T > 70 ° CS62180A CS62180B Min Typ Max - - 6 -10 - + -65 - 150 - - - 260 Min ...
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... CDH2 CDH1 CL LSB LSB Control Byte Data Byte Serial Port Write Timing is not a requirement for the CS62180B. In the CS62180B data is latched on the t CDZ t CDV High-Z Serial Port Read Timing CS62180A CS62180B Min Typ Max ...
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... Maximum input rise & fall times Symbol t TTR SRD t HRD t RST t PRS t PRD t PRA (Notes 15 and 16 CS62180A CS62180B Min Typ Max Units 250 648 - ns 125 324 - -125 - 125 ns 100 - - ...
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... Note: TMO, TLCLK, TSIGSEL and TSIGFR are generally coincident with the rising edge of TCLK. DS225PP1 RLOS t RS Old Alignment New Alignment Reframe Timing Logic 1 Logic 0 Transition Times for All Receiver Outputs STD HTD t TSP t STS t PTS Transmitter Timing. CS62180A CS62180B t TTR VDD - 1 TLCLK t PTCH 5 ...
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... RCLK RSER, RABCD RLINK RFSYNC, RMSYNC, RSIGSEL, RSIGFR RLCLK, RCHCLK RYEL, RCL, RBV, RFER, RLOS RST RPOS, RNEG PRD t PRS (RFSYNC PRA t RST t t SRD HRD Receiver Timing. CS62180A CS62180B DS225PP1 ...
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... The receiver line code decoder is now universal. The decoder will automatically decode either AMI or B8ZS. The CS62180B B8ZS con- trol option controls only the transmitter’s encoder. The universal decoder simplifies the provisioning of B8ZS in the network. Lastly, the serial control interface was simplified ...
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... Serial Interface For applications in which the device is to interface with a host processor, the CS62180A and CS62180B can be configured to run in host mode by tying the Serial Port Select pin (SPS) to the +5 V supply (VDD). This allows access to the serial port, providing a large number of configuration op- tions via the 16 on-chip control and status registers ...
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... DS225PP1 D7 (MSB) specifies burst mode if set to 1. When using burst mode, the address field of the com- mand word must be "0000", any other value will invalidate the command, and the CS62180A and CS62180B will simply ignore it. This effectively MODE CLKE TPOS SCLK ...
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... B8ZS codes will be intercepted by the receiver and replaced with 8 zeros before being proc- essed by the rest of the receive side. CS62180B Only: If B8ZS (CCR.2) is set to a "1", B8ZS zero substitution will be enabled in the transmitter. Independent of the setting of CCR.2, any incoming B8ZS codes will be inter- ...
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... DS225PP1 193E Yellow Alarm Format CCR.5: EYELMD The CS62180A and CS62180B supports two dif- ferent yellow alarm formats for 193E framing. Whichever format is selected, it will be used by both the transmit side, for yellow alarm genera- tion, and the receive side, for alarm detection. ...
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... The frame and multiframe counters can be reset independently via TMSYNC and TFSYNC. If left to run with- out a sync pulse, the CS62180A and CS62180B will arbitrarily choose a framing alignment. A low to high transition of TMSYNC, occurring near the rising edge of TCLK, resets the CS62180A’ ...
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... Logical combination of TMO and TSIGSEL pro- vides a way to distinguish the 6th, 12th, 18th, and 24th frames for external multiplexing of sig- naling channels. TMO is high for channels A and B, and TSIGSEL is high for channels A and C. See Figure 7 for timing diagram and 12 CS62180A CS62180B ...
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... DC-bit positions correspond to the spoiler bits. The CS62180B internally generates the spoiler bits. The data input on TLINK in the DC posi- tion is ignored by the CS62180B. TLCLK kHz clock for the TLINK input. TLCLK goes high during odd frames. TMO transitions high at the beginning of every 12th frame ...
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... Multiframe Transmit Timing Figure 9. T1DM Multiframe Transmit Timing TSIGSEL and TSIGFR serve no purpose in the T1DM mode and can be ignored. However, TSIGSEL and TSIGFR operate as in 193S mode. CS62180A CS62180B ...
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... CCR.5. See Common Control Register, above, for description of the available yellow alarm for- mats for 193S and 193E modes. In SLC-96 mode, the CS62180B does not generate the yel- low alarm code. rather, the user transmits the 16 4 ...
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... Note: When using internal S-bit generation (TCR conjunction with external F insertion (TCR.6 = 1), the CS62180A and CS62180B will logically ’OR’ the value at TSER with the internally generated value. This means that the data on TSER during S-bit periods should always be "0" to avoid corrupting the generated F pattern ...
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... It shows the various control options as inputs into decision branches of the flow chart, and the order in which the various optional signals are muxed into the final data stream. CS62180A CS62180B 2 1 CH4 CH3 CH2 CH11 ...
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... Internal 0 = Internal DL bits TLINK F S Idle Code Insertion Robbed Bit Signaling & B7 Zero Suppression Yellow Alarm Insertion B8ZS Zero Suppression Blue Alarm or Loopback TPOS/TNEG CS62180A CS62180B 193E TCR External FPS Passthrough TSER FPS TCR External CRC Passthrough TSER CRC TLINK FDL ...
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... Figure 13b. Transmit Insertion Hierarchy: Idle Codes, Signaling, and Idle 0 Transparent Channels Signaling TABCD Zero Suppression Yellow Alarm Insertion B8ZS Zero Suppression Blue Alarm or Loopback CS62180A CS62180B TSER F-bit Insertion TIR Idle Channels Normal 1 = Transparent TTR 0 = Normal TCR.4 Robbed Bit Signaling Disabled CCR Disabled TPOS/TNEG ...
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... Robbed Bit Signaling & B7 Zero Suppresion TCR.0 Yellow Alarm Yes ® T1DM SLC-96 TLINK Yes CCR.2 B8ZS Zero Suppression Yes TCR.1 Blue Alarm Yes CCR.0 Loopback TPOS/TNEG CS62180A CS62180B 193E CCR.5 Alarm Format 1 193E 0 FDL ...
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... RECEIVER The receive sides of the CS62180A and CS62180B have only three inputs: the clock (RCLK), the in- coming signal (RPOS/RNEG), and a reset pin (RST). The receiver determines the framing syn- chronization of the incoming data, and outputs the timing information on the six timing clocks: RLCLK, RCHCLK, RFSYNC, RMSYNC, RSIGFR, and RSIGSEL ...
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... Figure 15. 193S Multiframe Receive Timing Figure 16. 193E Multiframe Receive Timing CS62180A CS62180B Channel 1 LSB ...
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... Figure 18. T1DM Multiframe Receive Timing SLC-96 The CS62180B will output 36 bits of the DL on RLINK using RLCLK. RSIGSEL can be used to locate the DL bits. RSIGSEL will be held high in those frames where Fs bits and the last spoiler bit are present (frames 58 to 11). RSIGSEL is held low in all other frames (frames 12 to 57) ...
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... RLOS (pin 39) will go high until a new framing alignment is declared CH6 CH5 CH14 CH13 CH22 CH21 CS62180A CS62180B 2 1 SYNCT SYNCE RESYNC 10 bits 0 Autoresync 1 24 bits 1 Disabled 2 1 CH4 ...
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... When RCR.2 is clear, 10 consecutive F framing bits preceding an RMSYNC rising edge must be qualified. Setting RCR "1" re- quires the CS62180A and CS62180B to qualify 24 consecutive F or FPS bits preceding an T CS62180A ...
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... mum resync time (RCR.2=0). This causes the CS62180B to sync on the 10 valid F seprated by valid Fs bits in frames 65 through 11, and prevents false synchronization to data link and/or spoiler bits. signaling, setting Note: The CS62180B does not check SLC-96 multiframe alignment once synchronization is declared ...
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... Detected Detected Figure 21. Receive Status Register (RSR) Receive Status Register (RSR) The CS62180A and CS62180B monitors the in- coming T1 data for a number of error conditions. These alarms are recorded in the Receive Status Register (RSR), and output in real time on the status pins: RYEL, RCL, RBV, RFER, and RLOS ...
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... CS62180A only response to an RCL, nd RLOS goes high with the 32 bit. CS62180B only response to an RCL, RLOS goes high with the 128th 1 consecutive zero bit. The RLOS pin will return low one bit period prior to the F-bit of the second frame after the new alignment has been declared (timing signals will reset at the start of the new superframe) ...
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... RSER. The RCL pin will return low as soon as the next "1" is received at RPOS/RNEG. CS62180B only: Carrier loss is declared when 128 1 consecutive zero’s are detected at RPOS/RNEG. RCL (RSR.2) and the RCL pin (pin 36) transition high with the output of the ...
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... F-bit of frame 12. In T1DM mode , a yellow alarm is detected by checking the channel 24 sync word. In SLC-96 mode, the CS62180B does not recognize yellow alarms, rather, they are recognized by the user via the DL. Error Count Saturation RSR.6: ECS ECS (RSR ...
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... RSR.7. Bipolar Violations in valid B8ZS codes are never counted by the CS62180B, but will be counted by the CS62180A if B8ZS format is disabled via CCR.2. Note also that the Bipolar Violation monitoring circuit is disabled entirely when us- ing NRZ input at RPOS/RNEG (selected by tying RPOS/RNEG together) ...
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... HARDWARE MODE For stand alone applications or prototyping in which the device is to operate without a host processor, the CS62180A and CS62180B can be configured to run in hardware mode by tying the Serial Port Select pin (SPS) to ground (VSS). This disables the serial port and redefines pins 14-18 (16-20, PLCC) as mode control pins ...
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... B8ZS pin high enables B8ZS. Transparent mode may be selected by holding both pins low. CS62180B only: B7 selects the B7 zero suppres- sion format for the transmitter. Pulling the B7 pin high enables bit 7 stuffing. Pulling the B8ZS pin high enables B8ZS encoding on the transmit- ter ...
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... SPS 20 21 VSS TCLK NC TSER TMO CS62180A-IL 11 TLINK 12 and 13 CS62180B-IL TLCLK 14 TPOS 15 16 TNEG SPS VSS CS62180A CS62180B VDD POSITIVE POWER SUPPLY RLOS RECEIVE LOSS OF SYNC RFER RECEIVE FRAME ERROR RBV RECEIVE BIPOLAR VIOLATION ...
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... Pulled low to flag host controller when an alarm interrupt condition occurs. The user may select which alarm conditions will trigger an interrupt by appropriately setting the Receive Interrupt Mask Register (RIMR). INT is an open drain output, and should be tied to the positive supply (VDD) through a resistor. 36 CS62180A CS62180B DS225PP1 ...
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... CS62180A, pulling the B8ZS pin high enables B8ZS zero suppression in both the transmitter and receiver. On the CS62180B, pulling the B8ZS pin high enables B8ZS zero suppression in just the transmitter, since the CS62180B receiver is always capable of receiving either B8ZS or AMI-encoded data. Pulling the B7 and B8ZS pins high simultaneously puts the CS62180A and CS62180B into loopback operation ...
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... TSER) concurrent with the next falling edge of TCLK as the F-bit of a new frame. If tied low, TMSYNC may be used to set both frame and multiframe alignment. Without any sync input, the CS62180A and CS62180B will arbitrarily choose both frame and multiframe alignment. Internal channel, frame, and multiframe counters are output on TCHCLK, TMO, TSIGSEL, TSIGFR, and TLCLK ...
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... TPOS, TNEG - Transmit Bipolar Data Outputs, Pins 12 and 13 (PLCC, Pins 14 and 15 ). Coded data for transmission, updated on rising edge of TCLK. If TCR.7 is clear, or the CS62180A and CS62180B is in hardware mode, data is output in dual-unipolar format. If TCR.7 is set to a "1", data is output on TPOS in NRZ format, and TNEG is held low. Delay from input to TPOS/TNEG is 10 TCLK periods ...
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... On the CS62180A, RCL transitions high if 32 consecutive "0’s" are detected on RPOS and RNEG and returns low on next "1". On the CS62180B, RCL transitions high if 128 1 consecu- tive "0’s" are detected on RPOS and RNEG and returns low on the next "1". ...
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... Goes high for one RCLK period concurrent with the F-bit of each new frame output on RSER, low otherwise. In the T1DM mode, the falling edge of RFSYNC can be used to sample the "A" link channel on RLINK. DS225PP1 ® modes, and FPS bits are tested in 193E. In T1DM CS62180A CS62180B and T 41 ...
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... Fs bits (frames 59 to 11) and the last spolier bit (frame 58) are present; goes low in all other frames (frames 12 to 57). Miscellaneous TEST - Test Mode, Pin 32 (PLCC, Pin 36). Tie to VSS for normal operation. Factory use only. 42 ® mode, RSIGSEL goes high in those frames CS62180A CS62180B DS225PP1 ...
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... Plastic DIP 28/44 pin PLCC 28 MILLIMETERS E E1 DIM MIN NOM MAX MIN A 4.20 4.45 4.57 0.165 A1 2.29 2.79 3.04 0.090 B 0.33 0.41 0.53 0.013 D/E 12.32 12.45 12.57 0.485 D1/E1 11.43 11.51 11.58 0.450 D2/E2 9.91 10.41 10.92 0.390 e 1.19 1.27 1.35 0.047 A CS62180A CS62180B MILLIMETERS MIN DIM MIN NOM MAX 0.155 A 3.94 4.32 5.08 A1 0.51 0.76 1.02 0.020 B 0.36 0.46 0.014 0.56 B1 1.02 1.27 0.040 1.65 C 0.20 0.25 0.008 0.38 2.035 D 51.69 52.20 52.71 E1 14.22 0.540 13.72 13.97 e1 0.095 2.41 2.54 2.67 eA 15.24 - 15.87 0.600 L 3 ...
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... TLCLK RFER ® 11 TLINK RLOS 10 sync Data Link Supervision Figure A1. Typical System Connection several T1 lines into higher and higher data rates. Figure A2 gives an overview of the T-car- rier hierarchy. Level T-1 T-1C T-2 T-3 T-4 CS62180A CS62180B +5V VDD TV+ TTIP 40 SPS RV+ TRING 19 MODE TCLK 3 TPOS 12 TNEG 13 RCLK 24 RPOS 34 ...
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... F-bits Channel bits Frame 1 Frame 12 (F12 F10 F11 F12 Frame 24 (F24 F21 F22 F23 F24 CS62180A CS62180B ® ) and Digital Data ® ) T1DM. S Signaling Options F F Data Signaling 1 1-7 Bit 1-8 1 ...
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... shown in Figure A9. DDS that every DS0 channel contains at least one "1". Therefore, neither B8ZS nor bit-7 zero substitu- tion should be selcted in the CS62180B. CS62180A CS62180B ® T1 format is used between the Lo- ® ® ® ...
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... Bit 1-7 Bit 8 (B) 72 ® Figure A7. SLC-96 Framing Format Channel Bits Bit CS62180A CS62180B ® F-bits Channel bits Data Signaling S=0 1 1-7 Bit 1-7 Bit 8 (B) 1 PLS1 1-8 0 ...
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... Furthermore, no more than 15 consecu- tive "0’s" are allowable. Various zero substitution schemes have been developed to meet these re- quirements. The CS62180A and CS62180B supports B7 and B8ZS zero suppression formats. B7 Zero Substitution B7 zero substitution guarantees at least one "1" ...
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... CS62180A and CS62180B if B8ZS is enabled. The received B8ZS code is replaced with eight zeros before any other processing is done on the incoming data. Note also that even if B8ZS is not enabled, the CS62180A and CS62180B monitors the incoming signal for B8ZS codes, and reports them on RSR.2 (if CCR ...
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Notes • ...
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Notes • ...
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