AM27C2048-150DC Advanced Micro Devices, AM27C2048-150DC Datasheet

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AM27C2048-150DC

Manufacturer Part Number
AM27C2048-150DC
Description
2 megabit CMOS EPROM
Manufacturer
Advanced Micro Devices
Datasheet

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Am27C2048
2 Megabit (128 K x 16-Bit) CMOS EPROM
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am27C2048 is a 2 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 128 K
words, operates from a single +5 V supply, has a static
standby mode, and features fast single address loca-
tion programming. The Am27C2048 is ideal for use in
16-bit microprocessor systems. The device is available
in windowed ceramic DIP packages, and plastic one
time programmable (OTP) PDIP and PLCC packages.
Data can be typically accessed in less than 55 ns, al-
lowing high-performance microprocessors to operate
without any WAIT states. The device offers separate
Output Enable (OE#) and Chip Enable (CE#) controls,
BLOCK DIAGRAM
Fast access time
— Speed options as fast as 55 ns
Low power consumption
— 100 µA maximum CMOS standby current
JEDEC-approved pinout
— Plug-in upgrade of 1 Mbit EPROM
— 40-pin DIP/PDIP
— 44-pin PLCC
Single +5 V power supply
FINAL
Address
A0–A16
Inputs
PGM#
OE#
CE#
Output Enable
Chip Enable
V
V
V
Prog Logic
Decoder
Decoder
CC
SS
PP
and
Y
X
thus eliminating bus contention in a multiple bus micro-
processor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in
blocks, or at random. The device supports AMD’s
Flashrite programming algorithm (100 µs pulses), re-
sulting in a typical programming time of 16 seconds.
100% Flashrite programming
— Typical programming time of 16 seconds
Latch-up protected to 100 mA from –1 V to
V
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
High noise immunity
10% power supply tolerance standard
CC
+ 1 V
Data Outputs
DQ0–DQ15
2,097,152
Buffers
Bit Cell
Output
Gating
Matrix
Y
Publication# 11407
Issue Date: May 1998
Rev: G Amendment/0
11407G-1

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AM27C2048-150DC Summary of contents

Page 1

... It is organized as 128 K words, operates from a single +5 V supply, has a static standby mode, and features fast single address loca- tion programming. The Am27C2048 is ideal for use in 16-bit microprocessor systems. The device is available in windowed ceramic DIP packages, and plastic one time programmable (OTP) PDIP and PLCC packages ...

Page 2

... DQ11 A12 DQ10 A11 DQ9 A10 DQ8 DQ7 A7 DQ6 A6 DQ5 A5 DQ4 11407G-2 LOGIC SYMBOL 17 Am27C2048 Am27C2048 -90 -120 -150 -200 90 120 150 200 90 120 150 200 PLCC ...

Page 3

... Megabit (128 K x 16-Bit) CMOS UV EPROM Valid Combinations AM27C2048-55 DC5, DC5B, DI5, DI5B AM27C2048- 5.0 V 10% CC DC, DCB, DI, DIB AM27C2048-70 AM27C2048-90 AM27C2048-120 AM27C2048-150 DC, DCB, DE, DEB, DI, DIB AM27C2048-200 AM27C2048-255 DC, DCB, DI, DIB OPTIONAL PROCESSING Blank = Standard Processing B VOLTAGE TOLERANCE ...

Page 4

... Valid Combinations AM27C2048-55 PC5, PI5, JC5, JI5 AM27C2048- 5.0 V 10% CC AM27C2048-70 AM27C2048-90 AM27C2048-120 PC, PI, JC, JI AM27C2048-150 AM27C2048-200 AM27C2048-255 OPTIONAL PROCESSING Blank = Standard Processing VOLTAGE TOLERANCE See Product Selector Guide and Valid Combinations TEMPERATURE RANGE C = Commercial ( + Industrial (– ...

Page 5

... CE# should be decoded and used as the primary de- vice-selecting function, while OE# be made a common connection to all devices in the array and connected to Am27C2048 , and V between 12.5 V and 13 address line A9. Two identifier bytes ...

Page 6

... voltage during programming. PP Am27C2048 for each eight devices. The loca Outputs OUT High High High ...

Page 7

... V to +5. for ± 10% devices . . . . . . . . . +4. +5. Operating ranges define those limits between which the func- tionality of the device is guaranteed. to –2 2.0 V for periods up to –2.0 V for SS must not exceed+13.5 Am27C2048 ) . . . . . . . . . . . + .– + .– +125 ...

Page 8

... V CC CE and removed simultaneously or after 0.5 V, which may overshoot –75 –50 – 11407G-5 Figure 2. Typical Supply Current vs. Temperature Am27C2048 Min Max 2.4 0.45 2 0.5 CC –0.5 +0.8 C/I Devices 1.0 E Devices 5.0 5 1.0 100 100 applied ...

Page 9

... Input timing measurement reference levels Output timing measurement reference levels 11407G-7 2.4 V 1.5 V 0.45 V Output Note: For C L INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Am27C2048 All -55 others 1 TTL gate L 30 100 20 0.0–3.0 0.45–2.4 1.5 0.8, 2.0 1.5 0.8, 2.0 2.0 V 2.0 V Test Points 0 ...

Page 10

... Addresses Valid 0 ACC (Note 1) after the falling edge of the addresses without impact CDV040 Test Conditions Typ OUT Am27C2048 Am27C2048 -55 -70 -90 -120 -150 -200 -255 120 150 200 120 150 200 ...

Page 11

... BSC SIDE VIEW 21 .530 .580 20 SEATING PLANE .015 .014 .060 .022 Am27C2048 DATUM D .700 CENTER PLANE MAX 94 105 .300 BSC .600 BSC END VIEW 16-000038H-3 CDV040 DF11 3-30-95 ae .600 .625 .008 .015 .630 ...

Page 12

... REF .032 TOP VIEW REVISION SUMMARY FOR AM27C2048 Revision G Global Changed formatting to match current data sheets. Connection Diagrams Corrected designation for pin 38 on PDIP connection diagram to A16. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. ...

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