LXT971ALE Intel Corporation, LXT971ALE Datasheet

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LXT971ALE

Manufacturer Part Number
LXT971ALE
Description
Manufacturer
Intel Corporation
Datasheet

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Intel
3.3V Dual-Speed Fast Ethernet PHY Transceiver
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
Product Features
Combination 10BASE-T/100BASE-TX or
100BASE-FX Network Interface Cards
(NICs)
3.3V Operation.
Low power consumption (300 mW
typical).
Low-power “Sleep” mode.
10BASE-T and 100BASE-TX using a
single RJ-45 connection.
Supports auto-negotiation and parallel
detection.
MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber-optic capable.
Standard CSMA/CD or full-duplex
operation.
Supports JTAG boundary scan.
®
LXT971A
10/100 PCMCIA Cards
Cable Modems and Set-Top Boxes
Configurable via MDIO serial port or
hardware control pins.
Integrated, programmable LED drivers.
64-ball Plastic Ball Grid Array (PBGA).
64-pin Low-profile Quad Flat Package
(LQFP).
— LXT971ABC - Commercial (0
— LXT971ABE - Extended (-40
— LXT971ALC - Commercial (0
— LXT971ALE - Extended (-40
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Order Number: 249414-002
Datasheet
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Related parts for LXT971ALE

LXT971ALE Summary of contents

Page 1

... Plastic Ball Grid Array (PBGA). q — LXT971ABC - Commercial ( ambient — LXT971ABE - Extended (- ambient). 64-pin Low-profile Quad Flat Package (LQFP). q — LXT971ALC - Commercial ( ambient). q — LXT971ALE - Extended (- ambient). Order Number: 249414-002 August 2002 ...

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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 *Third-party brands and names are the property of their respective owners. 2 ...

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Contents 1.0 Pin Assignments ..............................................................................................................................12 2.0 Signal Descriptions ..........................................................................................................................16 3.0 Functional Description.....................................................................................................................21 3.1 Introduction .......................................................................................................................21 3.1.1 Comprehensive Functionality .............................................................................21 3.1.2 OSP™ Architecture ............................................................................................21 3.2 Network Media / Protocol Support....................................................................................22 3.2.1 10/100 Network Interface ...................................................................................22 3.2.1.1 Twisted-Pair Interface ..........................................................................22 3.2.1.2 Fiber ...

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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 3.6.7.2 Test Loopback...................................................................................... 35 3.7 100 Mbps Operation ......................................................................................................... 36 3.7.1 100BASE-X Network Operations...................................................................... 36 3.7.2 Collision Indication ............................................................................................ 38 3.7.3 100BASE-X Protocol Sublayer Operations ....................................................... 38 3.7.3.1 PCS Sublayer ....................................................................................... 38 3.7.3.2 ...

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Figures 1 LXT971A Block Diagram...................................................................................................9 2 64-Pin PBGA Pin Assignments.........................................................................................10 3 64-Pin LQFP Pin Assignments..........................................................................................11 4 Management Interface Read Frame Structure...................................................................21 5 Management Interface Write Frame Structure ..................................................................21 6 Interrupt Logic...................................................................................................................22 7 Initialization Sequence ......................................................................................................24 8 Hardware Configuration Settings ......................................................................................26 ...

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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Tables 1 LQFP Numeric Pin List .................................................................................................... 12 2 LXT971A MII Signal Descriptions .................................................................................. 14 3 LXT971A Network Interface Signal Descriptions ........................................................... 15 4 LXT971A Miscellaneous Signal Descriptions ................................................................. 16 5 LXT971A Power ...

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Status Register #2 (Address 17) ........................................................................................74 51 Interrupt Enable Register (Address 18).............................................................................75 52 Interrupt Status Register (Address 19, Hex 13).................................................................76 53 LED Configuration Register (Address 20, Hex 14) ..........................................................77 54 Transmit Control Register (Address 30) ...........................................................................78 Datasheet Document #: ...

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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver Revision History Page Globally replaced “pseudo-PECL” with Low-Voltage PECL”, except when identified with 5 V. Front Page: Changed “pseudo-ECL (PECL)” to “Low Voltage PECL (LVPECL). 1 Added “JTAG Boundary Scan” to Product Features ...

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Page Clock Requirements: Modified language under Clock Requirements heading. N/A Table 21 I/O Characteristics REFCLK: Changed values for Input Clock Duty Cycle under Min from and under Max from 60 to 65. Datasheet Document #: 249414 Revision ...

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LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver 10 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...

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Figure 1. LXT971A Block Diagram RESET Management / ADDR<4:0> MDIO MDC MDINT MDDIS TX_EN TXD<3:0> TX_ER TX_CLK LED/CFG<3:1> Collision COL Detect RX_CLK RXD<3:0> RXDV CRS RX_ER Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 1.0 Pin Assignments Figure 2. LXT971A 64-Ball PBGA Assignments 1 A MDINT REF B CLK/ SLEW0 E ADDR0 F ADDR3 G ADDR4 H RBIAS ...

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Figure 3. LXT971A 64-Pin LQFP Assignments REFCLK/XI XO MDDIS RESET TXSLEW0 TXSLEW1 GND VCCIO N/C N/C GND ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 1. LQFP Numeric Pin List Pin Symbol 1 REFCLK/ MDDIS 4 RESET 5 TxSLEW0 6 TxSLEW1 7 GND 8 VCCIO 9 N/C 10 N/C 11 GND 12 ADDR0 13 ADDR1 ...

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Table 1. LQFP Numeric Pin List (Continued) Pin Symbol 37 LED/CFG2 38 LED/CFG1 39 PWRDWN 40 VCCIO 41 GND 42 MDIO 43 MDC 44 N/C 45 RXD3 46 RXD2 47 RXD1 48 RXD0 49 RX_DV 50 GND 51 VCCD 52 ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 2.0 Signal Descriptions Note: Intel recommends that all inputs and multi-function pins be tied to the inactive states and all outputs be left floating, if unused. Table 2. LXT971A MII Signal Descriptions PBGA LQFP ...

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Table 2. LXT971A MII Signal Descriptions (Continued) PBGA LQFP Symbol Pin# Pin MDDIS E7 43 MDC D8 42 MDIO A1 64 MDINT 1. Type Column Coding Input Output Analog Open ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 4. LXT971A Miscellaneous Signal Descriptions PBGA LQFP Pin# Pin ...

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Table 5. LXT971A Power Supply Signal Descriptions PBGA LQFP Pin# Pin D4 11, 18, E4, F3 25, 34, F4, C6, 35, 41, C3, G7 G3, G4 21, 22 Table ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 8. LXT971A Pin Types and Modes Modes RXD 0-3 HWReset DL SFTPWRDN DL HWPWRDN High ISOLATE IPLD SLEEP High Z (High impedance) or three-state determines when the ...

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Functional Description 3.1 Introduction The LXT971A is a single-port Fast Ethernet 10/100 transceiver that supports 10 Mbps and 100 Mbps networks and complies with all applicable requirements of IEEE 802.3. The LXT971A directly drives either a 100BASE-TX line (up ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.2 Network Media / Protocol Support The LXT971A supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100 Mbps Ethernet over fiber media (100BASE-FX). 3.2.1 10/100 Network Interface The network interface port consists of ...

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Fault Detection and Reporting The LXT971A supports two fault detection and reporting mechanisms. “Remote Fault” refers to a MAC-to-MAC communication function that is essentially transparent to PHY layer devices used only during auto-negotiation, and is applicable only ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver bit 26.11 through software control. Setting Register bit 26. through the MDC/MDIO interface sets the MII pins (RXD[0:3], RX_DV, RX_CLK, RX_ER, COL, CRS, and TX_CLK higher drive strength. 3.2.3 Configuration ...

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Figure 5. Management Interface Write Frame Structure MDC MDIO 32 "1"s 0 (Write) Idle Preamble ST 3.2.3.1.3 MII Interrupts The LXT971A provides a single interrupt pin (MDINT). Interrupt logic is shown in LXT971A also provides two dedicated interrupt registers. Register ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.3 Operating Requirements 3.3.1 Power Requirements The LXT971A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from ...

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Hardware Control Mode In the Hardware Control Mode, LXT971A disables direct write operations to the MDIO registers via the MDIO Interface. On power-up or hardware reset the LXT971A reads the Hardware Control Interface pins and sets the MDIO registers ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 7. Initialization Sequence MDIO Control MDIO Controlled Operation (MDIO Writes Enabled) Reset MDIO Registers to values read at H/W Control Interface at last 3.4.3 Reduced Power Modes The LXT971A offers two power-down modes ...

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Software Power Down Software power-down control is provided by Register bit 0.11 in the Control Register (refer to Table 43 on page 74). During soft power-down, the following conditions are true: • The network port is shut down. • ...

Page 30

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.4.5 Hardware Configuration Settings The LXT971A provides a hardware option to set the initial device configuration. The hardware option uses the three LED driver pins. This provides three control bits, as listed in LED ...

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Establishing Link See Figure 9 for an overview of link establishment. 3.5.1 Auto-Negotiation If not configured for forced operation, the LXT971A attempts to auto-negotiate with its link partner by sending Fast Link Pulse (FLP) bursts. Each burst consists of ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 9. Link Establishment Overview Disable Auto-Negotiation Go To Forced Settings Done 3.6 MII Operation The LXT971A device implements the Media Independent Interface (MII) as defined in the IEEE 802.3 standard. Separate channels are ...

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Transmit Enable The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN after the last bit of the packet. 3.6.3 Receive Data Valid The LXT971A asserts RX_DV when it receives a valid ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 10. 10BASE-T Clocking TX_CLK (Sourced by LXT971A) RX_CLK (Sourced by LXT971A) XI Figure 11. 100BASE-X Clocking TX_CLK (Sourced by LXT971A) RX_CLK (Sourced by LXT971A) XI Figure 12. Link Down Clock Transition RX_CLK TX_CLK ...

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Operational Loopback Operational loopback is provided for 10 Mbps half-duplex links when Register bit 16 Data transmitted by the MAC (TXData) is looped back on the receive side of the MII (RXData). Operational loopback is not provided ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 10. Carrier Sense, Loopback, and Collision Conditions Speed Duplex Condition Full-Duplex 100 Mbps Half-Duplex Full-Duplex Half-Duplex, 10 Mbps Register bit 16 Half-Duplex, Register bit 16 Test Loopback is ...

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Figure 15. 100BASE-TX Data Path Standard Data Flow D0 Parallel to Serial D1 D2 Serial to D3 Parallel Scrambler Bypass Data Flow S0 Parallel to S1 Serial S2 Serial S3 to Parallel S4 As shown in Figure 14 on page ...

Page 38

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.7.2 Collision Indication Figure 18 shows normal transmission. Upon detection of a collision, the COL output is asserted and remains asserted for the duration of the collision as shown in Figure 18. 100BASE-TX Transmission ...

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In the receive direction, the PCS layer performs the opposite function, substituting two preamble nibbles for the SSD. 3.7.3.1.2 Dribble Bits The LXT971A handles dribbles bits in all modes. If one to four dribble bits are received, the nibble is ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 11. 4B/5B Coding 4B Code Code Type ...

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Table 11. 4B/5B Coding (Continued) 4B Code Code Type undefined undefined undefined undefined undefined INVALID undefined undefined undefined undefined undefined undefined 1. The /I/ (Idle) code group is sent continuously between frames. 2. The /J/ and ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver • De-assertion time for CRS is slightly longer than assertion time. This causes IFG intervals to appear somewhat shorter to the MAC than it actually is on the wire. • CRS de-assertion is not ...

Page 43

Programmable Slew Rate Control The LXT971A device supports a slew rate mechanism whereby one of four pre-selected slew rates can be used. This allows the designer to optimize the output waveform to match the characteristics of the magnetics. The ...

Page 44

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 3.8.4 10BASE-T Link Integrity Test In 10BASE-T mode, the LXT971A always transmits link pulses. When the Link Integrity Test function is enabled (the normal configuration), it monitors the connection for link pulses. Once link ...

Page 45

Register bits 17.14 and 17.9 can be used to determine the link operating conditions (speed and duplex). 3.9.1.1 Monitoring Next Page Exchange The LXT971A offers an Alternate Next Page mode to simplify the next page exchange process. Normally, Register ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver When a long event (such as duplex status) occurs it is edge detected and it starts the stretch timer. When the stretch timer expires the edge detector is reset so that a long event ...

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Table 12. BSR Mode of Operation Mode Description System Function Table 13. Supported JTAG Instructions Name EXTEST 1111 1111 1110 1000 IDCODE 1111 1111 1111 1110 SAMPLE 1111 1111 1111 1000 HIGHZ 1111 1111 1100 1111 ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 4.0 Application Information 4.1 Magnetics Information The LXT971A requires a 1:1 ratio for both the receive and transmit transformers. The transformer isolation voltage should be rated protect the circuitry from ...

Page 49

Figure 22. Typical Twisted-Pair Interface - Switch TPFOP LXT971A TPFON 1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center-tap from a 2.5 V current source. A separate ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 23. Typical Twisted-Pair Interface - NIC LXT971A 1. Center-tap current may be supplied from 3.3 V VCCA as shown. Additional power savings may be realized by supplying the center-tap from a 2.5 V ...

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Figure 24. Typical MII Interface MAC Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver TX_EN TX_ER TXD<3:0> TX_CLK RX_CLK RX_DV LXT971A RX_ER RXD<3:0> CRS COL X F RJ- ...

Page 52

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 4.3 The Fiber Interface The fiber interface consists of an LVPECL transmit and receive pair to an external fiber-optic transceiver. Both 3.3 V fiber-optic transceivers and 5 V fiber-optic transceivers can be used with ...

Page 53

Figure 25. Typical LXT971A-to-3.3 V Fiber Transceiver Interface Circuitry TPFON TPFOP LXT971A SD/TP TPFIN TPFIP 1. Refer to the transceiver manufacturer’s recommendations for termination circuitry. Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 26. Typical LXT971A-to-5 V Fiber Transceiver Interface Circuitry TPFON TPFOP LXT971A SD/TP TPFIN TPFIP 1. Refer to the transceiver manufacturer’s recommendations for termination circuitry. 2. See Figure 27 54 +3.3V +3.3V PF : ...

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Figure 27. ON Semiconductor Triple PECL-to-LVPECL Translator 0. 82: PECL Input Signal 130: (5V Fiber Txcvr) Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 5V ON Semiconductor Vcc ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 5.0 Test Specifications Note: Table 17 through Table 40 specifications of the LXT971A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in recommended operating conditions specified ...

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Table 19. Digital I/O Characteristics Parameter Input Low voltage Input High voltage Input current Output Low voltage Output High voltage 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 22. I/O Characteristics - LED/CFG Pins Parameter Input Low Voltage Input High Voltage Input Current Output Low Voltage Output High Voltage Table 23. I/O Characteristics – SD/TP Pin Parameter Fiber Mode (Register bit ...

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Table 25. 100BASE-FX Transceiver Characteristics Parameter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Peak differential input voltage Common mode input range 1. Typical values are at 25 °C and are for design aid only; not ...

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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 28. LXT971A Thermal Characteristics Parameter Package Theta-JA Theta-JC Psi - JT 60 LXT971ALC LXT971ALE x1 LQFP 1.4 64 LQFP 58 C/W 56 C/W 27 C/W 25 C/W 3.4 C/W 3.0 C/W LXT971ABE .96 64 BGA-CSP 42 C/W 20 C/W – Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...

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Timing Diagrams Figure 28. 100BASE-TX Receive Timing - 4B Mode TPFI CRS RX_DV RXD<3:0> RX_CLK COL Table 29. 100BASE-TX Receive Timing Parameters - 4B Mode Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK ...

Page 62

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 29. 100BASE-TX Transmit Timing - 4B Mode TXCLK TX_EN TXD<3:0> TPFO CRS Table 30. 100BASE-TX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High ...

Page 63

Figure 30. 100BASE-FX Receive Timing TPFI CRS RX_DV RXD<3:0> RX_CLK COL Table 31. 100BASE-FX Receive Timing Parameters Parameter RXD<3:0>, RX_DV, RX_ER setup to RX_CLK High RXD<3:0>, RX_DV, RX_ER hold from RX_CLK High CRS asserted to RXD<3:0>, RX_DV Receive start of ...

Page 64

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 31. 100BASE-FX Transmit Timing TXCLK TX_EN TXD<3:0> TPFO CRS Table 32. 100BASE-FX Transmit Timing Parameters Parameter TXD<3:0>, TX_EN, TX_ER setup to TX_CLK High TXD<3:0>, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled to ...

Page 65

Figure 32. 10BASE-T Receive Timing RX_CLK RXD, RX_DV, RX_ER CRS TPFI COL Table 33. 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High TPFIP RXD out (Rx latency) ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 33. 10BASE-T Transmit Timing TX_CLK TXD, TX_EN, TX_ER CRS TPFO Table 34. 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER setup to TX_CLK High TXD, TX_EN, TX_ER hold from TX_CLK High TX_EN sampled ...

Page 67

Figure 34. 10BASE-T Jabber and Unjabber Timing TX_EN TXD COL Table 35. 10BASE-T Jabber and Unjabber Timing Parameters Parameter Maximum transmit time Unjab time 1. Typical values are at 25 °C and are for design aid only; not guaranteed and ...

Page 68

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 36. Auto-Negotiation and Fast Link Pulse Timing TPFOP Figure 37. Fast Link Pulse Timing TPFOP Table 37. Auto-Negotiation and Fast Link Pulse Timing Parameters Parameter Clock/Data pulse width Clock pulse to Data pulse ...

Page 69

Figure 38. MDIO Input Timing MDC MDIO Figure 39. MDIO Output Timing MDC MDIO Table 38. MDIO Timing Parameters Parameter MDIO setup before MDC, sourced by STA MDIO hold after MDC, sourced by STA MDC to MDIO output delay, source ...

Page 70

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Figure 40. Power-Up Timing VCC MDIO,etc Table 39. Power-Up Timing Parameters Parameter Voltage threshold 2 Power Up delay 1. Typical values are at 25° C and are for design aid only; not guaranteed and ...

Page 71

Register Definitions The LXT971A register set includes multiple 16-bit registers. listing. Table complete memory map of all registers and individual register definitions. Base registers (0 through 8) are defined in accordance with the “Reconciliation Sublayer and ...

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LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 72 Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 ...

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Datasheet Document #: 249414 Revision #: 002 Rev. Date: August 7, 2002 LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 73 ...

Page 74

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 43. Control Register (Address 0) Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection Auto-Negotiation 0.12 Enable 0.11 Power-Down 0.10 Isolate Restart 0.9 Auto-Negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6 Speed Selection ...

Page 75

Table 44. MII Status Register #1 (Address 1) Bit Name 100BASE-T4 1.15 Not Supported 1.14 100BASE-X Full-Duplex 1.13 100BASE-X Half-Duplex 1.12 10 Mbps Full-Duplex 1.11 10 Mbps Half-Duplex 100BASE-T2 Full- Duplex 1.10 Not Supported 100BASE-T2 Half- Duplex 1.9 Not Supported ...

Page 76

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 45. PHY Identification Register 1 (Address 2) Bit Name 2.15:0 PHY ID Number Read Only Table 46. PHY Identification Register 2 (Address 3) Bit Name 3.15:10 PHY ID number Manufacturer’s ...

Page 77

Table 47. Auto-Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved Asymmetric 4.11 Pause 4.10 Pause 4.9 100BASE-T4 100BASE-TX 4.8 full-duplex 4.7 100BASE-TX 10BASE-T 4.6 full-duplex 4.5 10BASE-T Selector Field, 4.4:0 S<4:0> ...

Page 78

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 48. Auto-Negotiation Link Partner Base Page Ability Register (Address 5) Bit Name 5.15 Next Page 5.14 Acknowledge 5.13 Remote Fault 5.12 Reserved Asymmetric 5.11 Pause 5.10 Pause 5.9 100BASE-T4 100BASE-TX 5.8 full-duplex 5.7 ...

Page 79

Table 49. Auto-Negotiation Expansion (Address 6) Bit Name 6.15:6 Reserved 6.5 Base Page Parallel 6.4 Detection Fault Link Partner 6.3 Next Page Able 6.2 Next Page Able 6.1 Page Received Link Partner A/N 6.0 Able Read Only ...

Page 80

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 51. Auto-Negotiation Link Partner Next Page Receive Register (Address 8) Bit Name Next Page 8.15 (NP) Acknowledge 8.14 (ACK) Message Page 8.13 (MP) Acknowledge 2 8.12 (ACK2) Toggle 8.11 (T) Message/Unformatted 8.10:0 Code ...

Page 81

Table 52. Configuration Register (Address 16, Hex 10) Bit Name 16.15 Reserved Force Link Pass 16.14 16.13 Transmit Disable Bypass Scrambler 16.12 (100BASE-TX) 16.11 Reserved Jabber 16.10 (10BASE-T) SQE 16.9 (10BASE-T) TP Loopback 16.8 (10BASE-T) CRS Select 16.7 (10BASE-T) 16.6 ...

Page 82

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 53. Status Register #2 (Address 17) Bit Name 17.15 Reserved 17.14 10/100 Mode 17.13 Transmit Status 17.12 Receive Status 17.11 Collision Status 17.10 Link 17.9 Duplex Mode 17.8 Auto-Negotiation Auto-Negotiation 17.7 Complete 17.6 ...

Page 83

Table 54. Interrupt Enable Register (Address 18) Bit Name 18.15:9 Reserved 18.8 Reserved 18.7 ANMSK 18.6 SPEEDMSK 18.5 DUPLEXMSK 18.4 LINKMSK 18.3 Reserved 18.2 Reserved 18.1 INTEN 18.0 TINT 1. R/W = Read /Write Datasheet Document #: 249414 Revision #: ...

Page 84

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 55. Interrupt Status Register (Address 19, Hex 13) Bit Name 19.15:9 Reserved 19.8 Reserved 19.7 ANDONE 19.6 SPEEDCHG 19.5 DUPLEXCHG 19.4 LINKCHG 19.3 Reserved 19.2 MDINT 19.1 Reserved 19.0 Reserved 1. R/W = ...

Page 85

Table 56. LED Configuration Register (Address 20, Hex 14) Bit Name LED1 20.15:12 Programming bits LED2 20.11:8 Programming bits 1. R/W = Read /Write RO = Read Only LH = Latching High 2. Link status is the primary LED driver. ...

Page 86

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver Table 56. LED Configuration Register (Address 20, Hex 14) (Continued) Bit Name LED3 20.7:4 Programming bits 5 20.3:2 LEDFREQ PULSE- 20.1 STRETCH 20.0 Reserved 1. R/W = Read /Write RO = Read Only LH ...

Page 87

Table 58. Transmit Control Register (Address 30) Bit Name 30.15:11 Reserved 30.12 Transmit Low Power 30.11:10 Port Rise Time Control 30.9:0 Reserved 1. Values are relative approximations. Not guaranteed or production tested. 2. R/W = Read/Write Datasheet Document #: 249414 ...

Page 88

LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 7.0 Package Specifications Figure 43. PBGA Package Specification 64-Ball Plastic Ball Grid Array Package • Part Number - LXT971ABC Commercial Temperature Range (0ºC to +70ºC) • Part Number - LXT971ABE Extended Temperature Range (-40ºC ...

Page 89

... Figure 44. LXT971A LQFP Package Specifications 64-Pin Low Profile Quad Flat Pack • Part Number - LXT971ALC Commercial Temperature Range (0ºC to +70ºC) • Part Number - LXT971ALE Extended Temperature Range (-40ºC to +85ºC) Millimeters Dim Min Max A – 1.60 A 0.05 0. 1.35 1. 0.17 0.27 D 11.85 12.15 D 9.9 10 11.85 12.15 E 9.9 10.1 1 ...

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... LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver 8.0 Product Ordering Information Table 59. Product Information Number DJLXT971ALC.A4 DJLXT971ALE.A4 FLLXT971ABC.A4 FLLXT971ABE.A4 Figure 45. Ordering Information - Sample DJ LXT 971A 90 Revision Qualification E001 Build Format E000 E001 Qualification Q S Product Revision xn Temperature Range ...

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