PLUS405-55N Philips Semiconductors, PLUS405-55N Datasheet

no-image

PLUS405-55N

Manufacturer Part Number
PLUS405-55N
Description
Programmable logic sequencer 16 ? 64 ? 8
Manufacturer
Philips Semiconductors
Datasheet
Philips Semiconductors Programmable Logic Devices
DESCRIPTION
The PLUS405-55 device is a bipolar,
programmable state machine of the Mealy
type. Both the AND and the OR array are
user-programmable. All 64 AND gates are
connected to the 16 external dedicated inputs
(I0 - I15) and to the feedback paths of the
8 on-chip State Registers (Q
complement arrays support complex
IF-THEN-ELSE state transitions with a single
product term (input variables C
All state transition terms can include True,
False and Don’t Care states of the controlling
state variables. All AND gates are merged
into the programmable OR array to issue the
next-state and next-output commands to their
respective registers. Because the OR array is
programmable, any one or all of the 64
transition terms can be connected to any or
all of the State and Output Registers.
All state (Q
registers are edge-triggered, clocked J-K
flip-flops, with Asynchronous Preset and
Reset options. The PLUS405 architecture
provides the added flexibility of the J-K toggle
function which is indeterminate on S-R
flip-flops. Each register may be individually
programmed such that a specific
Preset-Reset pattern is initialized when the
initialization pin is raised to a logic level “1”.
This feature allows the state machine to be
asynchronously initialized to known internal
state and output conditions prior to
proceeding through a sequence of state
transitions. Upon power-up, all registers are
unconditionally preset to “1”. If desired, the
initialization input pin (INIT) can be converted
to an Output Enable (OE) function as an
additional user-programmable feature.
Availability of two user-programmable clocks
allows the user to design two independently
clocked state machine functions consisting of
four state and four output bits each.
Order codes are listed in the Ordering
Information Table below.
ORDERING INFORMATION
October 22, 1993
Programmable logic sequencer
(16
28-Pin Plastic Dual In-Line (600mil-wide)
28-Pin Plastic Leaded Chip Carrier
P0
64
- Q
P7
DESCRIPTION
) and output (Q
8)
P0
0
- Q
, C
P7
1).
F0
). Two
- Q
F7
)
FEATURES
APPLICATIONS
66.7MHz minimum guaranteed clock rate
55MHz minimum guaranteed operating
frequency (1/(t
Functional superset of PLS105/105A
Field-programmable (Ti-W fusible link)
16 input variables
8 output functions
64 transition terms
8-bit State Register
8-bit Output Register
2 transition Complement Arrays
Multiple clocks
Programmable Asynchronous Initialization
or Output Enable
Power-on preset of all registers to “1”
“On-chip” diagnostic test mode features for
access to state and output registers
950mW power dissipation (typ.)
TTL compatible
J-K or S-R flip-flop functions
Automatic “Hold” states
3-State outputs
Interface protocols
Sequence detectors
Peripheral controllers
Timing generators
Sequential circuits
Elevator contollers
Security locking systems
Counters
Shift registers
55MHz (t
55MHz (t
FREQUENCY
OPERATING
IS1
IS
IS
+ t
180
+ t
+ t
CKO1
CKO
CKO
)
)
)
ORDER CODE
PLUS405–55N
PLUS405–55A
PIN CONFIGURATIONS
F7
F6
N = Plastic DIP (600mil-wide)
A = Plastic Leaded Chip Carrier
I4
I3
I2
I1
I0
10
11
5
6
7
8
9
I5/CLK
I5/CLK
F5 F4 GND F3 F2 F1 F0
12
4
GND
CLK
F7
F6
F5
F4
I7
I6
I4
I3
I2
I1
I0
13
I6
3
10
11
12
13
14
1
2
3
4
5
6
7
8
9
14
I7
2
N Package
A Package
CLK
PLUS405-55
15 16
DRAWING NUMBER
1
Product specification
V
28
CC
27
17 18
I8
0413B
0401F
853–1546 11164
28
27
26
25
24
23
22
21
20
19
18
17
16
15
26
I9
V
I8
I9
I10
I11
I12
I13
I14
I15
INIT/OE
F0
F1
F2
F3
CC
25
24
23
22
21
20
19
I10
I11
I12
I13
I14
I15
INIT/OE

Related parts for PLUS405-55N

PLUS405-55N Summary of contents

Page 1

... Philips Semiconductors Programmable Logic Devices Programmable logic sequencer ( DESCRIPTION The PLUS405-55 device is a bipolar, programmable state machine of the Mealy type. Both the AND and the OR array are user-programmable. All 64 AND gates are connected to the 16 external dedicated inputs (I0 - I15) and to the feedback paths of the ...

Page 2

... High-to-Low clock transition, after INIT goes Low. See timing definition for t and t NVCK VCK Output Enable: Provides an output enable function to buffers F0–F7 from the Output Registers. October 22, 1993 NAME AND FUNCTION . 181 Product specification PLUS405-55 POLARITY Active-High (H) Active-High/Low (H/L) Active-High/Low (H/L) Active-High (H) Active-High/Low (H/L) Active-High/Low (H/L) ...

Page 3

... HOLD RESET 182 Product specification PLUS405- H/L H ...

Page 4

... Philips Semiconductors Programmable Logic Devices Programmable logic sequencer ( FUNCTIONAL DIAGRAM P63 October 22, 1993 P0 I/CLK ( ( ( ( INIT/OE 183 Product specification PLUS405-55 ...

Page 5

... I4 4 I5/CLK I10 I11 24 I12 23 I13 22 I14 21 20 I15 NOTE: Denotes a programmable fuse location. October 22, 1993 DETAIL D 184 Product specification PLUS405-55 DETAIL A 19 INIT/OE DETAIL B DETAIL CLK ...

Page 6

... With very complex state machines, this approach can be prohibitive, both in terms of time and wasted resources. Note that the PLUS405 sequencers have 2 Complement Arrays which allow the user to design 2 independent Complement functions. This is particularly useful if 2 independent state machines have been implemented on one device ...

Page 7

... MAX 2.7V CC OUT V = MAX 0.45V CC OUT –15 OUT V = MAX 5.0V 2. 5.0V 2.0V CC OUT 186 Product specification PLUS405-55 TEMPERATURE Maximum junction 150 C Maximum ambient 75 C Allowable thermal rise 75 C ambient to junction LIMITS 1 TYP MAX UNIT V 0.8 V –0.8 –1 0.35 0.45 V < –20 – ...

Page 8

... Input CK+ Input CK CK– CC INIT– CK– CK– INIT– CK+ Input CK1+ Output CK2+ Output OE– Output – OE+ Output + INIT+ Output + V + Output + CC 187 Product specification PLUS405-55 LIMITS 1 MIN TYP MAX UNIT ...

Page 9

... Array 30pF to the 1.5V level, and 5pF. High-to-High impedance tests are made to an output L + DUT F7 OUTPUTS INIT/OE GND 188 Product specification PLUS405-55 LIMITS 1 MIN TYP MAX UNIT 55.6 64.5 MHz 55.6 62.5 MHz 38.5 46.5 MHz 38.5 45.5 MHz 66.7 83.3 MHz 55.6 66.7 MHz 66 ...

Page 10

... INITH Asynchronous Initialization 1.5V 1. CKO 1.5V 1.5V 1.5V t CKH MAX 1. Power-On Preset 189 Product specification PLUS405-55 +3V 0V +3V 1. +3V 0V +3V 0V +3V 1. CKL CKO +3V 1.5V 0V +5V ...

Page 11

... RJS É É É É É É É É É É 1.5V (FORCED CKH t CKO Diagnostic Mode – Output Register Input Jam 190 Product specification PLUS405-55 +3V 0V +10V + 1.5V n +10V 8 ...

Page 12

... Required delay between the NVCK negative transition of the clock and the negative transition of the Asynchronous Initialization to guarantee that the clock edge is not detected as a valid negative transition. 191 Product specification PLUS405-55 SYMBOL PARAMETER t Width of initialization input INITH pulse. t Required delay between ...

Page 13

... H PROGRAMMING THE PLUS405: The PLUS405 has a power-up preset feature. This feature insures that the device will power- known state with all register elements (State and Output Register) at logic High (H). When programming the device it is important to realize this is the initial state of the device. You must provide a next state jump if you do not wish to use all Highs (H) as the present state ...

Page 14

... ACTION A PROPAGATE PROGRAMMING/SOFTWARE SUPPORT Refer to Section 9 (Development Software) CLK2 and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. CLK1 OPTION CODE 193 Product specification PLUS405- CODE ACTION CODE L NO CHANGE – ...

Page 15

... Philips Semiconductors Programmable Logic Devices Programmable logic sequencer ( PLUS405 PROGRAM TABLE INACTIVE Im DON’T CARE – COMP. ARRAY C1 C0 I15 I14 I13 I12 I11 I10 ...

Page 16

... SNAP RESOURCE SUMMARY DESIGNATIONS P 63 DIN405 I 15 NIN405 October 22, 1993 P 0 DIN405 NIN405 AND NOR X2 JKFF405 195 Product specification PLUS405-55 I/CLK CK405 CK405 4 F OUT405 OUT405 INIT/OE ...

Related keywords