EP20K200CF484C7 Altera Corporation, EP20K200CF484C7 Datasheet

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EP20K200CF484C7

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EP20K200CF484C7
Description
Manufacturer
Altera Corporation
Datasheet

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Features...
Notes to
(1)
(2)
(3)
Altera Corporation
DS-APEX20KC-2.2
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
PLLs
Speed grades
Maximum macrocells
Maximum user I/O pins
February 2004 ver. 2.2
Table 1. APEX 20KC Device Features
The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
PLL: phase-locked loop.
The -7 speed grade provides the fastest performance.
(2)
Table
Feature
(3)
1:
EP20K200C
Programmable logic device (PLD) manufactured using a 0.15-µm all-
layer copper-metal fabrication process
High-density architecture
-7, -8, -9
526,000
200,000
106,496
8,320
832
376
52
25 to 35% faster design performance than APEX
Pin-compatible with APEX 20KE devices
High-performance, low-power copper interconnect
MultiCore
and embedded memory
LUT logic used for register-intensive functions
Embedded system blocks (ESBs) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
200,000 to 1 million typical gates (see
Up to 38,400 logic elements (LEs)
Up to 327,680 RAM bits that can be used without reducing
available logic
2
Note (1)
®
TM
architecture integrating look-up table (LUT) logic
EP20K400C
1,052,000
-7, -8, -9
400,000
212,992
16,640
1,664
104
488
4
EP20K600C
1,537,000
-7, -8, -9
600,000
311,296
24,320
Programmable Logic
2,432
152
588
4
Table
APEX 20KC
1)
TM
EP20K1000C
1,772,000
1,000,000
20KE devices
-7, -8, -9
327,680
38,400
2,560
Data Sheet
160
708
Device
4
1

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EP20K200CF484C7 Summary of contents

Page 1

... The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to 57,000 additional gates. (2) PLL: phase-locked loop. (3) The -7 speed grade provides the fastest performance. Altera Corporation DS-APEX20KC-2.2 ® ■ Programmable logic device (PLD) manufactured using a 0.15-µm all- layer copper-metal fabrication process – ...

Page 2

... Supports hot-socketing operation – Pull-up on I/O pins before and during configuration Table 2. APEX 20KC Supply Voltages Feature Internal supply voltage (V CCINT MultiVolt I/O interface voltage levels (V Note to Table 2: (1) APEX 20KC devices can be 5.0-V tolerant by using an external resistor. Table 2) CCIO Voltage ) 1 1.8 V, 2.5 V, 3.3 V, 5.0 V CCIO (1) Altera Corporation ...

Page 3

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet ■ Advanced interconnect structure – Copper interconnect for high performance – Four-level hierarchical FastTrack providing fast, predictable interconnect delays – Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) – ...

Page 4

... APEX 20KC device. 672 Pin 488 (3) (3) 508 (3) 508 TM 356-Pin BGA 1.27 1,225 35.0 × 35.0 484 Pin 672 Pin 1.00 1.00 529 729 23 × × 27 Altera Corporation Notes (1), (2) 1,020 Pin 588 708 packages. for detailed 652-Pin BGA 1.27 2,025 45.0 × 45.0 1,020 Pin 1.00 1,089 33 × 33 ...

Page 5

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry. Table 7 APEX 20KC devices. Table 7. APEX 20KC Device Features (Part Feature MultiCore system integration ...

Page 6

... LVPECL data pins (in EP20K400C and larger devices) LVDS and LVPECL clock pins (in all devices) LVDS and LVPECL data pins up to 156 Mbps (in EP20K200C devices) HSTL Class I PCI-X SSTL-2 Class I and II SSTL-3 Class I and II CAM Dual-port RAM FIFO RAM ROM Altera Corporation ...

Page 7

... Functional Description Altera Corporation APEX 20KC Programmable Logic Device Data Sheet After an APEX 20KC device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications. APEX 20KC devices are supported by the Altera Quartus II development ...

Page 8

... LUT LUT LUT IOE Product Term Memory LUT LUT Product Term IOE Memory IOE IOE Figure 1 shows an IOEs support PCI, GTL+, SSTL-3, LVDS, and other standards. Flexible integration of embedded memory, including CAM, RAM, ROM, FIFO, and other memory functions. Altera Corporation ...

Page 9

... Figure 2. MegaLAB Structure To Adjacent LAB or IOEs Local Interconnect Altera Corporation APEX 20KC Programmable Logic Device Data Sheet MegaLAB Structure APEX 20KC devices are constructed from a series of MegaLAB structures. Each MegaLAB structure contains 16 logic array blocks (LABs), one ESB, and a MegaLAB interconnect, which routes signals within the MegaLAB structure ...

Page 10

... LAB or are placed into separate LABs. If both the rising and falling edges of a clock are used in a LAB, both LAB- wide clock signals are used. To/From Adjacent LAB, ESB, or IOEs Column Interconnect Altera Corporation ...

Page 11

... The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the LAB. (2) The SYNCCLR signal can be generated by the local interconnect or global signals. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The LAB-wide control signals can be generated from the LAB local interconnect, global signals, and dedicated clock pins. The inherent low skew of the FastTrack interconnect enables used for clock distribution ...

Page 12

... LUT can be used for unrelated functions. The LE can also drive out registered and unregistered versions of the LUT output. Register Bypass Packed Register Select Programmable Register To F astTrack Interconnect, PRN MegaLAB Interconnect Local Interconnect ENA CLRN To F astTrack Interconnect, MegaLAB Interconnect, or Local Interconnect Altera Corporation ...

Page 13

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The APEX 20KC architecture provides two types of dedicated high-speed data paths that connect adjacent LEs without using local interconnect paths: carry chains and cascade chains. A carry chain supports high-speed arithmetic functions such as counters and adders, while a cascade chain implements wide-input functions such as equality comparators with minimum delay ...

Page 14

... APEX 20KC Programmable Logic Device Data Sheet 14 Figure 6. APEX 20KC Carry Chain Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 Register s2 LE2 sn Register LEn Register Carry-Out LEn + 1 Altera Corporation ...

Page 15

... LUT d[7..4] LUT d[(4 n – 1)..(4 n – 4)] LUT Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Cascade Chain With the cascade chain, the APEX 20KC architecture can implement functions with a very wide fan-in. Adjacent LUTs can compute portions of a function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’ ...

Page 16

... LPM and DesignWare functions, automatically chooses the appropriate mode for common functions such as counters, adders, and multipliers. If required, the designer can also create special-purpose functions that specify which LE operating mode to use for optimal performance. Figure 8 shows the LE operating modes. Altera Corporation ...

Page 17

... The DATA1 and DATA2 input signals can supply counter enable down control, or register feedback signals for LEs other than the second LAB. (6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet LAB-Wide Cascade-In ...

Page 18

... LAB. Consequently, if any of the LEs in an LAB use the counter mode, other LEs in that LAB must be used as part of the same counter or be used for a combinatorial function. The Quartus II software automatically places any registers that are not used by the counter into other LABs. Altera Corporation ...

Page 19

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The counter mode uses two 3-input LUTs: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading, and another AND gate provides synchronous clearing. If the cascade function is used counter mode, the synchronous clear or load overrides any signal carried on the cascade chain ...

Page 20

... IOEs. The column line is used to route signals from one row to another. A column line can drive a row line; it can also drive the MegaLAB interconnect directly, allowing faster connections between rows. Figure 10 shows how the FastTrack interconnect uses the local interconnect to drive LEs within MegaLAB structures. I/O I/O MegaLAB MegaLAB MegaLAB I/O I/O Altera Corporation I/O I/O I/O ...

Page 21

... Figure 10. FastTrack Connection to Local Interconnect I MegaLAB Structure Column Altera Corporation APEX 20KC Programmable Logic Device Data Sheet I/O Row MegaLAB Structure MegaLAB Interconnect MegaLAB Interconnect Drives Local Interconnect Row & Column ...

Page 22

... MegaLAB structures except the end local interconnect on the side of the MegaLAB opposite the ESB. Pins using the FastRow interconnect achieve a faster set-up time, as the signal does not need to use a MegaLAB interconnect line to reach the destination LE. Figure 12 shows the FastRow interconnect. Column Interconnect Altera Corporation ...

Page 23

... Figure 12. APEX 20KC FastRow Interconnect IOE FastRow Interconnect Altera Corporation APEX 20KC Programmable Logic Device Data Sheet FastRow Interconnect IOE Drives Local Interconnect in Two MegaLAB Structures MegaLAB Table 8 summarizes how various elements of the APEX 20KC architecture drive each other. Select Vertical I/O Pins ...

Page 24

... ESB control signals. In product-term mode, each ESB contains 16 macrocells. Each macrocell consists of two product terms and a programmable register. shows the ESB in product-term mode. MegaLAB Row Column Interconnect FastTrack FastTrack Interconnect Interconnect FastRow Interconnect Figure 13 Altera Corporation ...

Page 25

... Global Signals 65 From Adjacent LAB Local Interconnect Altera Corporation APEX 20KC Programmable Logic Device Data Sheet 4 4 Macrocells APEX 20KC macrocells can be configured individually for either sequential or combinatorial logic operation. The macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register ...

Page 26

... If both the rising and falling edges of a clock are used in an ESB, both ESB-wide clock signals are used. ESB-Wide Clocks 2 2 Programmable Register D Q ENA Clock/ CLRN Enable Select Clear Select Altera Corporation ESB Output ...

Page 27

... Local Interconnect Local Interconnect Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The programmable register also supports an asynchronous clear function. Within the ESB, two asynchronous clears are generated from global signals and the local interconnect. Each macrocell can either choose between the two asynchronous clear signals or choose to not be cleared ...

Page 28

... ESB offers a dual-port mode, which supports simultaneous reads and writes at two different clock frequencies. diagram. Figure 17. ESB Block Diagram wraddress[] data[] wren inclock inclocken inaclr Macrocell Product- Term Logic Macrocell Product- Term Logic To Next Macrocell Figure 17 shows the ESB block rdaddress[] q[] rden outclock outclocken outaclr Altera Corporation ...

Page 29

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet ESBs can implement synchronous RAM, which is easier to use than asynchronous RAM. A circuit using asynchronous RAM must generate the RAM write enable (WE) signal, while ensuring that its data and address signals meet setup and hold time specifications relative to the WE signal. ...

Page 30

... The ESB can also use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in Figure 19. APEX 20KC ESB Implementing Dual-Port RAM address_a[] data_a[] we_a clkena_a Clock A to System Logic Port A Port B address_b[] data_b[] we_b clkena_b Figure 19. Clock B Altera Corporation ...

Page 31

... Figure 20: (1) All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Read/Write Clock Mode The read/write clock mode contains two clocks. One clock controls all registers associated with writing: data input, WE, and write address. The other clock controls all registers associated with reading: read enable (RE), read address, and data output ...

Page 32

... ENA D Q ENA D Q Write ENA Pulse Generator Figure 21 RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D Q ENA Read Address Write Address Read Enable Write Enable Altera Corporation shows To MegaLAB, FastTrack & Local Interconnect ...

Page 33

... All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Single-Port Mode The APEX 20KC ESB also supports a single-port mode, which is used when simultaneous reads and writes are not required. See ...

Page 34

... RAM block, the search is performed serially. Thus, finding a particular data word can take many cycles. CAM searches all addresses in parallel and outputs the address storing a particular word. When a match is found, a match flag is set high. diagram. Figure 23 shows the CAM block Altera Corporation ...

Page 35

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 23. APEX 20KC CAM Block Diagram wraddress[] data[] wren inclock inclocken inaclr CAM can be used in any application requiring high-speed searches, such as networking, communications, data compression, and cache management. The APEX 20KC on-chip CAM provides faster system performance than traditional discrete CAM ...

Page 36

... An ESB is fed by the local interconnect, which is driven by adjacent LEs (for high-speed connection to the ESB) or the MegaLAB interconnect. The ESB can drive the local, MegaLAB, or FastTrack interconnect routing structure to drive LEs and IOEs in the same MegaLAB structure or anywhere in the device. INCLKENA OUTCLKENA INCLOCK OUTCLOCK Altera Corporation Figure 24 OUTCLR INCLR ...

Page 37

... I/O Structure Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Implementing Logic in ROM In addition to implementing logic with product terms, the ESB can implement logic functions when it is programmed with a read-only pattern during configuration, creating a large LUT. With LUTs, combinatorial functions are implemented by looking up the results, rather than by computing them ...

Page 38

... The Quartus II Compiler can program these delays automatically to minimize setup time while providing a zero hold time. Quartus II Logic Option Decrease input delay to internal cells Decrease input delay to input registers Decrease input delay to output register Increase delay to output pin Increase clock enable delay Altera Corporation ...

Page 39

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The register in the APEX 20KC IOE can be programmed to power-up high or low after configuration is complete programmed to power-up low, an asynchronous clear can control the register programmed to power-up high, an asynchronous preset can control the register. This feature is useful for cases where the APEX 20KC device controls an active- low input or another device ...

Page 40

... Clock Enable Delay (1 ) VCC CLRn[1..0] Chip-Wide Reset Input Register VCC VCC Chip-Wide Reset (1), (2) OE Register D Q ENA CLRN Output Register t Delay Open-Drain Output ENA CLRN/ Slew-Rate PRN Control Input Pin to Core Delay ( ENA CLRN VCCIO Optional PCI Clamp Altera Corporation ...

Page 41

... This programmable delay has four settings: off and three levels of delay. (2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Each IOE drives a row, column, MegaLAB, or local interconnect when used as an input or bidirectional pin. A row IOE can drive a local, MegaLAB, row, and column interconnect ...

Page 42

... These pins can be used for fast clock, clear, or high fan-out logic signal distribution. They also can drive out. The dedicated fast I/O pin data output and tri-state control are driven by local interconnect from the adjacent MegaLAB for high speed. IOE Column Interconnect Altera Corporation ...

Page 43

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Advanced I/O Standard Support APEX 20KC IOEs support the following I/O standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, PCI-X, 3.3-V AGP, LVDS, LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2 Class I and II. For more information on I/O standards supported by APEX 20KC devices, see Application Note 117 (Using Selectable I/O Standards in Altera Devices) ...

Page 44

... Because APEX 20KC devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the V CCIO powered in any order. I/O Bank 2 Individual Power Bus I/O Bank 5 and V power supplies may be CCINT Altera Corporation I/O Bank 3 (1) LVDS Input Block (2) I/O Bank 4 ...

Page 45

... When APEX 20KC device can drive a 2.5-V device with 3.3-V tolerant inputs. CCIO Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Signals can be driven into APEX 20KC devices before and during power- up without damaging the device. In addition, APEX 20KC devices do not drive out during power-up ...

Page 46

... The ClockLock circuit’s output can be driven off-chip to clock other devices in the system; further, the feedback loop of the PLL can be routed off-chip. This feature allows the designer to exercise fine control over the I/O interface between the APEX 20KC device and another high-speed device, such as SDRAM. current specification OL Altera Corporation ...

Page 47

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Clock Multiplication The APEX 20KC ClockBoost circuit can multiply or divide clocks by a programmable number. The clock can be multiplied by m/(n × k), where m and k range from 2 to 160 and n ranges from 1 to 16. Clock multiplication and division can be used for time-domain multiplexing and other functions, which can reduce design LE requirements. Clock Phase & ...

Page 48

... Clock t t (1) ( OUTDUTY ClockLock Generated Clock Note to Figure 29: (1) Rise and fall times are measured from 10% to 90%. shows the incoming and generated parameter refers to the O INDUTY INCLKSTB JITTER O JITTER CLKDEV Altera Corporation ...

Page 49

... Clock1 PLL output frequency CLOCK1 for internal use f Output clock frequency for CLOCK0_EXT external clock0 output Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Tables 11 and 12 summarize the ClockLock and ClockBoost parameters for APEX 20KC devices. Condition I/O Standard 3 ...

Page 50

... Altera Corporation Units Max (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz (5) MHz ...

Page 51

... SignalTap Monitors internal device operation with the SignalTap embedded logic analyzer. Instructions Altera Corporation APEX 20KC Programmable Logic Device Data Sheet All APEX 20KC devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration ...

Page 52

... Figure 30 shows the timing requirements for the JTAG signals. Tables 14 Boundary-Scan Register Length 1,164 1,506 1,806 2,190 (1) Manufacturer 1 (1 Bit) Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 Altera Corporation and 15 ( ...

Page 53

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 30. APEX 20KC JTAG Waveforms TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal to Be Captured t JSZX Signal to Be Driven Table 16 shows the JTAG timing parameters and values for APEX 20KC devices. Table 16. APEX 20KC JTAG Timing Parameters & ...

Page 54

... With respect to ground No bias Under bias PQFP, RQFP, TQFP, and BGA packages, under bias Ceramic PGA packages, under bias “Timing Model” section on page Note (1) Min (2) –0.5 –0.5 –0.5 –25 –65 –65 Altera Corporation 65. Max Unit 2.5 V 4 150 ° C 135 ° C 135 ° ...

Page 55

... OZ current ( supply current (standby) CC0 CC (All ESBs in power-down mode) R Value of I/O pin pull-up CONF resistor before and during configuration Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Conditions (4) (3), (3), (4) (3), (4) (3), (4) (2), (5) For commercial use For industrial use Conditions ...

Page 56

... Conditions 3 –12 mA 3.0 V (1) CCIO mA 3.0 V (2) CCIO Min CCINT = 1 3.3 V. CCIO Minimum Maximum 3.0 3.6 2 0.3 CCIO –0.3 0.8 –10 10 2.4 0.4 Altera Corporation Max Unit and V are CCIO Table Units µ ...

Page 57

... CCIO voltage V High-level input IH voltage V Low-level input IL voltage I Input pin leakage I current V High-level output OH voltage V Low-level output OL voltage Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Conditions Minimum – CCIO CCIO I = –0 3.0 V CCIO I = 0.1 mA ...

Page 58

... Conditions Minimum 3.0 0.5 × V –0.5 0 < V < V –10 IN CCIO = –500 µA 0.9 × OUT = 1,500 µA I OUT Maximum 1.7 1 0.3 CCIO CCIO 0.35 × V CCIO –10 10 – 0.45 0.45 Typical Maximum 3.3 3 0.5 CCIO CCIO 0.3 × V CCIO 10 CCIO 0.1 × V CCIO Altera Corporation Units µ Units µ ...

Page 59

... V Differential input TH threshold V Receiver input IN voltage range R Receiver differential L input resistor (external to APEX devices) Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Conditions Minimum 3.0 0.5 × V –0.5 0.7 × < V < V –10.0 IN CCIO 0.9 × –500 µA ...

Page 60

... Conditions Minimum 1.35 0. 0.1 REF (2) OL Conditions Minimum 2.375 V – 0.04 REF 1. 0.18 REF –0 –7 7.6 mA (2) OL Typical Maximum Units 1.5 1.65 V 1.0 1. – 0.1 V REF 0.65 V Typical Maximum Units 2.5 2.625 0.04 V REF REF 1.25 1. 0.3 V CCIO V – 0.18 V REF V V – 0. Altera Corporation ...

Page 61

... I/O supply voltage CCIO V Termination voltage TT V Reference voltage REF V High-level input IH voltage V Low-level input IL voltage V High-level output OH voltage V Low-level output OL voltage Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Conditions Minimum 2.375 V – 0.04 REF 1. 0.18 REF –0 –15 15.2 mA (2) OL ...

Page 62

... OL Conditions Minimum 1.71 V – 0.05 REF 0. 0.1 REF –0 –8 mA (1) V – 0.4 OH CCIO (2) OL Typical Maximum Units 3.3 3 0.05 V REF REF 1.5 1 0.3 V CCIO V – 0.2 V REF V V – 0 Typical Maximum Units 1.8 1. 0.05 V REF REF 0.75 0. 0.3 V CCIO V – 0.1 V REF V 0.4 V Altera Corporation ...

Page 63

... OH (2) The I parameter refers to low-level output current. This parameter applies to open-drain pins as well as output OL pins. (3) V specifies center point of switching range. REF Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Conditions = –500 µA I OUT = 1,500 µA I OUT 0 < V < V ...

Page 64

... Room Temperature Output Current (mA 1 Output Voltage (V) Note ( CCINT = 1 CCIO = 2.5V 35 Room Temperature 0 Output Voltage ( CCINT = 1.8V V CCIO = 1.8V Room Temperature I OH 1.5 2.0 Altera Corporation 2.5 3 ...

Page 65

... Timing Model Altera Corporation APEX 20KC Programmable Logic Device Data Sheet The high-performance FastTrack and MegaLAB interconnect routing resources ensure predictable performance, accurate simulation, and accurate timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and therefore have unpredictable performance ...

Page 66

... APEX 20KC Programmable Logic Device Data Sheet Figure 33. ESB Asynchronous Timing Waveforms ESB Asynchronous Read RE Rdaddress a0 Data-Out d0 ESB Asynchronous Write WE Data-In t ESBWASU a0 Wraddress Data-Out ESBWP t ESBWDSU din0 t ESBWCCOMB a1 din0 a2 t ESBARC d2 t ESBWDH din1 t ESBWAH a2 t ESBDD din1 Altera Corporation a3 d3 dout2 ...

Page 67

... ESB Synchronous Read WE Rdaddress a0 t ESBDATASU CLK Data-Out ESB Synchronous Write (ESB Output Registers Used) WE din1 Data- Wraddress t ESBWESU CLK Data-Out Altera Corporation APEX 20KC Programmable Logic Device Data Sheet a1 t ESBDATAH t ESBDATACO2 d1 din2 a2 t ESBDATAH t ESBDATASU t ESBSWC dout0 dout1 Figure 35 shows the timing model for bidirectional I/O pin timing ...

Page 68

... Tables describes the f Table 39 describes the functional timing parameters. OE Register (1) PRN t XZBIDIR ZXBIDIR CLRN t OUTCOBIDIR PRN D Q CLRN PRN D Q CLRN timing parameters shown in MAX Parameter Bidirectional Pin t INSUBIDIR t INHBIDIR Figure 32. Altera Corporation ...

Page 69

... ESB macrocell register clock-to-output delay PTERMCO Table 38. APEX 20KC f Routing Delays MAX Symbol t Fan-out delay estimate using local interconnect F1-4 t Fan-out delay estimate using MegaLab interconnect F5-20 t Fan-out delay estimate using FastTrack interconnect F20+ Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Parameter Parameter 69 ...

Page 70

... Clock-to-output delay with PLL clock at IOE output register OUTCOPLL 70 Tables 40 and 41 describe APEX 20KC external timing parameters. The timing values for these pin-to-pin delays are reported for all pins using the 3.3-V LVTTL I/O standard. Note (1) Clock Parameter Parameter Conditions (2) (2) Altera Corporation ...

Page 71

... SSTL-3 Class II Input adder delay for the SSTL-3 Class II I/O standard SSTL-2 Class I Input adder delay for the SSTL -2 Class I I/O standard SSTL-2 Class II Input adder delay for the SSTL -2 Class II I/O standard Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Parameter Table 43. Tables 42 ...

Page 72

... Rdn = 430 Ω (2) Cload = 35 pF Rup = 450 Ω Rdn = 450 Ω (2) Cload = 35 pF Rup = 520 Ω Rdn = 480 Ω (2) Cload = 10 pF Rup = 1M Ω Rdn = 25 Ω (2) Cload = 30 pF Rup = 25 Ω (2) Cload2 = Ω (2) Cload2 = Ω (2) Cload = 4 pF R=100 Ω (2) Altera Corporation ...

Page 73

... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet Figure 36. AC Test Conditions for LVTTL, 2.5 V, 1.8 V, PCI & GTL+ I/O Standards Ouptut pin Figure 37. AC Test Conditions for SSTL-3 Class I & II I/O Standards Output pin Cload1 Figure 38. AC Test Conditions for the LVDS I/O Standard ...

Page 74

... Max Min 0.01 0.10 0.27 0.65 -8 Speed Grade Max Min 1.30 2.35 2.92 3.05 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 –0.24 0.00 1.09 2.10 2.50 1.48 0.72 1.10 and external timing parameters for MAX -9 Speed Grade Max Min Max 0.01 0.10 0.30 0.32 0.78 0.92 -9 Speed Grade Max Min Max 1.51 1.69 2.49 2.72 3.46 3.86 3.44 3.85 0.54 0.55 0.68 0.55 1.56 0.11 0.00 2.45 –0.28 –0.02 1.28 1.43 2.52 2.82 2.97 3.32 1.78 2.00 0.81 1.29 1.45 Altera Corporation Unit Unit ...

Page 75

... ESBCH t 1.33 ESBCL t 1.05 ESBWP t 0.87 ESBRP Table 48. EP20K200C External Timing Parameters Symbol -7 Speed Grade Min t 1.23 INSU t 0.00 INH t 2.00 OUTCO t 0.81 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL Altera Corporation APEX 20KC Programmable Logic Device Data Sheet -8 Speed Grade Max Min 0.15 0.81 0.98 -8 Speed Grade Max Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -8 Speed Grade Max Min Max 1.26 0.00 3.79 2.00 4.31 0.92 0.00 2.36 0.50 2 ...

Page 76

... LE Timing Parameters MAX Symbol -7 Speed Grade Min LUT 76 -8 Speed Grade Max Min Max 1.78 0.00 3.79 2.00 4.31 6.12 6.51 6.12 6.51 3.47 0.00 2.36 0.50 2.62 4.69 4.82 4.69 4.82 -8 Speed Grade Max Min Max 0.01 0.10 0.27 0.30 0.65 0.78 -9 Speed Grade Unit Min Max 1.99 ns 0.00 ns 2.00 4.70 ns 7. Speed Grade Unit Min Max 0.01 ns 0.10 ns 0.32 ns 0.92 ns Altera Corporation ...

Page 77

... ESBWESU t 2.01 ESBDATASU −0.20 t ESBWADDRSU t 0.02 ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD 0.58 PTERMSU t PTERMCO Table 52. EP20K400C f Routing Delays MAX Symbol -7 Speed Grade Min t F1-4 t F5-20 t F20+ Altera Corporation APEX 20KC Programmable Logic Device Data Sheet -8 Speed Grade Max Min Max 1.30 1.51 2.35 2.49 2.92 3.46 3.05 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 −0.24 0.00 1.09 1.28 2.10 2.52 2.50 2.97 1.48 1.78 0.72 1.10 1.29 -8 Speed Grade Max Min Max 0 ...

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... Table 54. EP20K400C External Timing Parameters Symbol -7 Speed Grade Min t 1.37 INSU t 0.00 INH t 2.00 OUTCO t 0.80 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL 78 -8 Speed Grade Max Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -8 Speed Grade Max Min Max 1.52 0.00 4.25 2.00 4.61 0.91 0.00 2.27 0.50 2.55 -9 Speed Grade Max Min Max 2.00 2.00 0.20 0.20 2.00 2.00 1.44 1.19 -9 Speed Grade Min Max 1.64 0.00 2.00 5. Altera Corporation Unit Unit ...

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... XZBIDIR t ZXBIDIR t 3.22 INSUBIDIRPLL t 0.00 INHBIDIRPLL t 0.50 OUTCOBIDIRPLL t XZBIDIRPLL t ZXBIDIRPLL Table 56. EP20K600C f LE Timing Parameters MAX Symbol -7 Speed Grade Min LUT Altera Corporation APEX 20KC Programmable Logic Device Data Sheet -8 Speed Grade Max Min Max 1.67 0.00 4.25 2.00 4.61 6.55 6.97 6.55 6.97 3.80 0.00 2.27 0.50 2.55 4.62 4.84 4.62 4.84 -8 Speed Grade Max Min 0.01 0.10 0.27 0.65 -9 Speed Grade ...

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... Speed Grade Min t F1-4 t F5-20 t F20 Speed Grade Max Min Max 1.30 1.51 2.35 2.49 2.92 3.46 3.05 3.44 0.50 0.50 0.63 0.50 1.43 0.03 0.00 2.27 −0.24 0.00 1.09 1.28 2.10 2.52 2.50 2.97 1.48 1.78 0.72 1.10 1.29 -8 Speed Grade Max Min Max 0.15 0.16 0.94 1.05 1.76 1.98 -9 Speed Grade Unit Min Max 1.69 ns 2.72 ns 3.86 ns 3.85 ns 0.54 ns 0.55 ns 0.68 ns 0.55 ns 1.56 ns 0.11 ns 0.00 ns 2.45 ns −0.28 ns −0.02 ns 1.43 ns 2.82 ns 3.32 ns 2.00 ns 0. Speed Grade Unit Min Max 0.18 ns 1.20 ns 2.23 ns Altera Corporation ...

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... ESBCL t 1.05 ESBWP t 0.87 ESBRP Table 60. EP20K600C External Timing Parameters Symbol -7 Speed Grade Min t 1.28 INSU t 0.00 INH t 2.00 OUTCO t 0.80 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL Altera Corporation APEX 20KC Programmable Logic Device Data Sheet -8 Speed Grade Max Min 1.66 1.66 0.20 0.20 1.66 1.66 1.28 1.06 -8 Speed Grade Max Min Max 1.40 0.00 4.29 2.00 4.77 0.91 0.00 2.37 0.50 2.63 -9 Speed Grade Max Min Max 2 ...

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... MAX Symbol -7 Speed Grade Min LUT 82 -8 Speed Grade Max Min 2.57 0.00 4.29 2.00 8.31 8.31 4.77 0.00 2.37 0.50 6.35 6.35 LE Timing Microparameters -8 Speed Grade Max Min 0.01 0.10 0.27 0.66 -9 Speed Grade Max Min Max 2.97 0.00 4.77 2.00 5.11 9.14 9.76 9.14 9. 2.63 - 6.94 6.94 -9 Speed Grade Max Min Max 0.01 0.10 0.30 0.32 0.79 0.92 Altera Corporation Unit Unit ...

Page 83

... ESBWADDRSU t 0.00 ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD 0.61 PTERMSU t PTERMCO Table 64. EP20K1000C f MAX Symbol -7 Speed Grade Min t F1-4 t F5-20 t F20+ Altera Corporation APEX 20KC Programmable Logic Device Data Sheet ESB Timing Microparameters -8 Speed Grade Max Min 1.48 2.36 2.93 3.08 0.50 0.51 0.62 0.51 1.47 0.07 0.00 2.19 –0.28 –0.03 1.12 2.11 2.56 1.49 0.69 1.13 Routing Delays -8 Speed Grade Max Min 0 ...

Page 84

... Table 66. EP20K1000C External Timing Parameters Symbol -7 Speed Grade Min t 1.14 INSU t 0.00 INH t 2.00 OUTCO t 0.81 INSUPLL t 0.00 INHPLL t 0.50 OUTCOPLL 84 -8 Speed Grade Max Min 1.66 1.66 0.20 0.20 1.66 1.66 1.26 1.05 -8 Speed Grade Max Min Max 1.14 0.00 4.63 2.00 5.26 0.92 0.00 2.32 0.50 2.55 -9 Speed Grade Max Min Max 2.00 2.00 0.20 0.20 2.00 2.00 1.41 1.18 -9 Speed Grade Min Max 1.11 0.00 2.00 5. Altera Corporation Unit Unit ...

Page 85

... ZXBIDIRPLL Table 68. Selectable I/O Standard Input Delays Symbol -7 Speed Grade Min LVCMOS LVTTL 2.5 V 1.8 V PCI GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II LVDS CTT AGP Altera Corporation APEX 20KC Programmable Logic Device Data Sheet -8 Speed Grade Max Min 2.54 0.00 4.63 2.00 8.98 8.98 5.27 0.00 2.32 0.50 6.67 6.67 Tables 68 and ...

Page 86

... Before and during device configuration, all I/O pins are pulled built-in weak pull-up resistor. -9 Speed Grade Max Min Max 0.00 0.00 0.00 0.00 0.00 0.00 1.41 1.57 –0.53 –0.56 –0.29 –0.39 –0.71 –0.75 –0.71 –0.75 –0.71 –0.75 –0.71 –0.75 –0.70 –0.73 0.00 0.00 0.00 0.00 Altera Corporation Unit Min CCIO ...

Page 87

... Device Pin- Outs Ordering Information Altera Corporation APEX 20KC Programmable Logic Device Data Sheet SRAM configuration elements allow APEX 20KC devices to be reconfigured in-circuit by loading new configuration data into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different configuration data, reinitializing the device, and resuming user-mode operation ...

Page 88

... Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample Speed Grade with 7 being the fastest Operating Temperature C: Commercial temperature (t I: Industrial temperature (t 20. Tables 40 and 41. 27. through 67. ˚ ˚ ˚ ˚ 100 C) J Altera Corporation ...

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... Altera Corporation APEX 20KC Programmable Logic Device Data Sheet 89 ...

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... Copyright © 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...

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