HDMP-1032A AGILTRON Incorporated, HDMP-1032A Datasheet
HDMP-1032A
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HDMP-1032A Summary of contents
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... GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate. Description The HDMP-1032A transmitter and HDMP-1034A receiver are used together to build a high-speed data link for point-to-point communication. These silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin PQFP packages. ...
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... Tx Operation Principles – Encoding & Phase Lock Loop .................................... 24 Rx Operation Principles – Decoding & Phase Lock Loop .................................... 25 Integrator Capacitor & Power Supply Bypassing/Grounding ................................................................................................. 26 TTL and High Speed I/O ............................................................................................. 26 Data Bus Line/Broadcast Transmission ................................................................. 27 Nomenclature Changes between HDMP-1032A/34A and HDMP-1022/24 .................................................................... 30 Pin Cross Reference Table ........................................................................................ 31 Page ...
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... HDMP-1022 fig TXCLK Tx Rx TXCLK D) 32 BIT SIMPLEX TRANSMISSION HDMP-1022 fig 1d Tx TXCLK Rx Tx RXCLK0/1 REFCLK E) 16 BIT DUPLEX TRANSMISSION Figure 1. Various configurations using the HDMP-1032A/1034A RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK Rx DEMUX RXCLK0/1 REFCLK RXCLK0/1 REFCLK ...
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... Word 960 MBits/sec The baud rate includes an addi- tional four encoding bits (20 bits total) that the HDMP-1032A/34A G-Link chipset transmits. The serial baud rate is calculated as: Serial Baud Rate = 20bits 60MW (– ...
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... TXFLAG ENCODER TXDATA TXCNTL SIGN W-FIELD TX[0-15] ENCODER Figure 3. HDMP-1032A Transmitter Block Diagram setting TCLKENB high, the user may provide an external TTL high speed serial clock at TXCLK. This clock replaces the internal VCO clock and is in- tended for diagnostic purposes only. This uncharacterized signal ...
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... HDMP-1034A Rx Block Diagram The HDMP-1034A receiver was designed to convert a serial data signal sent from the HDMP-1032A RXCAP1/0 + HSIN CDR REFCLK CLOCK GENERATOR RXCLK0/1 Figure 4 ...
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Demultiplexer (DEMUX) This block takes the recovered serial data from the CDR block and demultiplexes it into a 20-bit parallel word comprised of a 16-bit word-field and 4-bit code-field. Decoder (DECODE) This block decodes the 4-bit code-field and determines whether ...
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REFCLK. By adjusting the phase of the data word rather than REFCLK, the optimal setup time is achieved for the input latches of the chip interfacing to the Rx. As the relative phase between the HSIN± input and ...
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Multiple Channel Configuration The connections for a multiple channel configuration are shown in Figure 4.3. The daisy-chain signals SRQIN and SRQOUT are used to allow each receiver’s PASS system shift requests to propagate to the master, which is the last ...
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... Hold Time, for TX[0-15], TXDATA, TXCNTL and h TXFLAG Relative to Rising Edge of TXCLK. TXCLK TX[0-15] TXDATA TXCNTL TXFLAG t s HSOUT Figure 5. HDMP-1032A (Tx) Timing Diagram. 10 The setup and hold time param- eters, t and t , are referenced the rising edge of TXCLK. The start of a word, bit TX[0], in the high speed serial output ...
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... PASS system resets, PASSENB=1. WORD 1 W BIT 0 HSIN RXCLK1 RXCLK0 REFCLK Figure 6. HDMP-1034A (Rx) Timing Diagram. 11 RXDATA, RXCNTL and RXDSLIP are clocked out with the falling edge of RXCLK1 and appear after a delay RXCLK1 and its d complement RXCLK0 are both 50% duty cycle clocks. ...
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... HDMP-1032A (Tx), HDMP-1034A (Rx) DC Electrical Specifications Tc = –20°C to +85° 3.15V to 3.45V, Typical values are 25° Symbol Parameter V TTL Input High Voltage Level, Guaranteed high signal IH,TTL for all inputs. V TTL Input Low Voltage Level, Guaranteed low signal IL,TTL for all inputs. ...
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... CC Symbol Parameter F TXCLK and REFCLK Frequency Tolerance tol (REFCLK is referenced to TXCLK) Symm Symmetry (Duty Cycle) HDMP-1032A (Tx), HDMP-1034A (Rx) Absolute Maximum Ratings T = 25°C except as specified. Operation in excess of any one of these conditions may result in permanent damage to A the device. Symbol Parameter V Supply Voltage ...
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... T + (θ where T is the case temperature measured on the top center of the package and 3 3 for the HDMP-1032A and HDMP-1034A is 50°C/W. θ ja Unit Typ. °C 660 Unit Typ. °C 792 is measured on a standard ja is the power being dissipated ...
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... GND 1 TX[14] 2 TX[15] 3 TXCNTL 4 TXDATA 5 TXFLAG _TTL 8 CC GND_TTL 9 TXFLGENB 10 ESMPXENB 11 LOCKED GND Figure 7. HDMP-1032A (Tx) Package Layout, Top View. GND_TTL 1 RX[1] 2 RX[0] 3 RXREADY 4 RXERROR 5 RXDSLIP 6 V _TTL 7 CC GND_TTL GND 10 REFCLK 11 TSTCLK 12 SHFIN 13 SHFOUT 14 SRQOUT 15 ...
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... HDMP-1032A (Tx) Pin Definition User Mode Options Name Pin Type TXFLGENB 10 I-TTL ESMPXENB 11 I-TTL TXDATA 5 I-TTL TXCNTL 4 I-TTL High-Speed Serial/Parallel I/O HSOUT+ 20 HS_OUT HSOUT- 19 TX[0] 46 I-TTL TX[1] 47 TX[2] 50 TX[3] 51 TX[4] 52 TX[5] 53 TX[6] 54 TX[7] 55 TX[8] 58 TX[9] 59 TX[10] 60 TX[11] 61 TX[12] 62 TX[13] 63 TX[14] 2 TX[15] 3 TXFLAG 6 I-TTL 16 Signal Flag Bit Mode Select: When this input is high, the TXFLAG bit input is sent as an extra 17th data bit during data word transfers ...
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... HDMP-1032A (Tx) Pin Definition (continued) PLL/Clock Generator Name Pin Type TXCAP0 32 C TXCAP1 33 TXCLK 37 I-TTL TXDIV0 26 I-TTL TXDIV1 27 LOCKED 12 O-TTL Power Supply/Ground _TTL _HS _A1 _A2 57 CC GND GND_TTL ...
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... Enhanced Simplex Mode Enable: Enables descrambling of the Flag Bit encoding. The ESMPXENB pin on the Tx chip must be set to the same value. This mode should be enabled unless compatibility with previous versions of G-Link (i.e. HDMP-1022/1012) is desired which don’t have this feature. Enable Parallel Automatic Synchronization System: The parallel Rx data and control words are read out with REFCLK instead of the incoming word’ ...
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... HDMP-1034A (Rx) Pin Definition (continued) CDR/Clock Generator Name Pin Type RXCAP0 32 C RXCAP1 33 REFCLK 11 I-TTL RXDIV0 28 I-TTL RXDIV1 29 RXCLK0 37 O-TTL RXCLK1 38 Power Supply/Ground _TTL _HS GND GND_TTL ...
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... HDMP-1034A (Rx) Pin Definition (continued) Pass System RXDSLIP 6 O-TTL SHFIN 13 I-TTL SHFOUT 14 O-TTL SRQIN 34 I-TTL SRQOUT 15 O-TTL Test Mode/No Connect Pins TSTCLK 12 I-TTL #RESET 35 I-TTL WSYNCDSB 36 I-TTL Word Slip: This output is asserted whenever the phase of the parallel word relative to the reference clock has exceeded the range of the internal delay, which results in a slippage of one word ...
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... HDMP-103xA 8 TOP VIEW Mechanical Dimensions of HDMP-1032A/34A Dimensional Parameter D1/E1 (in millmeters) HDMP-103xA 14.00 ±0.10 Tolerance 21 Details Plastic 85% Tin, 15% Lead 300–800 µm 0.20 mm max 0.10 mm max ...
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... FIELD 16 BITS SERIAL BIT STREAM IDLE WORD WORD K Figure 9. HDMP-1032A/1034A (Tx/Rx Pair) Line Code. 22 page. Note that the leftmost bit in each table is the first bit to be transmitted in time, while the rightmost bit is the last bit to be transmitted. Data Word Codes In Data Word mode, all 16 bits of the Tx are transmitted to the Rx, along with a flag bit ...
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... Coding with ESMPXENB=0 (Compatible with previous G-Link chips, HDMP-1012/14, HDMP-1022/24) Word Type Flag W-Field w10 w11 w12 w13 w14 w15 Data Word Structure Data = True X10 X11 X12 X13 X14 X15 1 ...
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... TXCLK FREQUENCY DETECTOR INTERNAL CLOCKS CLOCK GENERATOR LOCK DETECT Figure 10. HDMP-1032A (Tx) Phase-Lock Loop. 24 all the internal clock signals required by the Tx chip. The data inputs, TX[0-15], as well as the control signals; TXDATA, TXCNTL and TXFLAG are latched in on the rising edge of an internally generated word rate clock ...
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... PHASE DETECTOR 1 INTERNAL CLOCKS 0 FREQUENCY DETECTOR REFCLK LOCK Figure 11. HDMP-1034A (Rx) Phase-Lock Loop. 25 • Word Decoding • Error Detection • Automatic Parallel Word Phase Adjustment Rx Data Path Figure 4 shows a simplified block diagram of the receiver. The data path consists of an Input Sampler, a Word Demultiplexer, a Coding Field (C-Field) Decoder, and a Word Field (W-Field) Decoder ...
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... HDMP-1032A BYPASS CAPACITOR C2 = PLL INTEGRATOR CAPACITOR NOTE PINS SUPPLY VOLTAGE SHOULD CC COME FROM A LOW NOISE SOURCE. Figure 12. HDMP-1032A (Tx) and HDMP-1034A (Rx) Power Supply Pins result, all of the separate power supplies ( _TTL and V _HS) can be connected CC onto this plane. The bypassing of ...
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For opti- mum performance, both outputs should see the same impedance necessary that all HS_OUT outputs be terminated into 50Ω. Figure 15 shows various methods of interfacing HS_OUT to HS_IN ...
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... HSIN+ Rx HDMP-1034A HSIN— RESISTOR VALUE R1 SETS PROPER BIAS FOR THE PECL OUTPUT STAGE. THE G-LINK Rx IS INTERNALLY TERMINATED AND DOESN’T REQUIRE EXTERNAL BIAS OR TERMINATION RESISTORS PECL INPUT + Tx HDMP-1032A HDMP-1034A 0.1 µF Z0 HSIN+ Z0 HSIN— 0.1 µ ...
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... Zstub 0.1 F 0 —5 V —5 V — HDMP-1034A HDMP-1034A HDMP-1034A Ω 50 Ω Zstub 0 —5 V — HDMP-1034A HDMP-1034A HDMP-1032A HDMP-0450 100 Ω ...
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... In addition, some names have been changed to names analogous to those used in Fibre Channel and Gigabit Ethernet. Examples are TXCLK instead of STRBIN and RXCLK instead of STRBOUT. A pin cross reference table for the HDMP-1032A/34A & HDMP-1022/24 is provided in the table on the next page. ...
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... Pin Cross Reference Table HDMP-1032A (Tx) Pin Name 1 GND 2 TX[14] 3 TX[15] 4 TXCNTL 5 TXDATA 6 TXFLAG VCC_TTL 9 GND_TTL 10 TXFLGENB 11 ESMPXENB 12 LOCKED 13 VCC 14 GND VCC_HS 18 GND_HS 19 HSOUT- 20 HSOUT VCC 25 GND 26 TXDIV0 27 TXDIV1 28 TCLKENB GND_A1 31 VCC_A1 32 TXCAP0 33 TXCAP1 GND ...
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Data subject to change. Copyright © 2001 Agilent Technologies, Inc. August 16, 2001 5988-3852EN ...