AD9826 Analog Devices, AD9826 Datasheet
AD9826
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AD9826 Summary of contents
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... Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter. The AD9826 can operate at speeds greater than 15 MSPS with reduced performance. The CDS amplifiers may be disabled for use with sensors that do not require CDS, such as Contact Image Sensors (CIS), CMOS active pixel sensors, and Focal Plane Arrays ...
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... POWER DISSIPATION 3-Channel Mode 1-Channel Mode NOTES 1 Linear Input Signal Range is from when the CCD’s reference level is clamped the AD9826’s input clamp. 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP 4V p-p MAX INPUT SIGNAL RANGE RESET TRANSIENT ...
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... CDSCLK1 CDSCLK2 Min Typ Max 2.0 0 4.5 0 2.95 0.05 Min Typ Max 200 (Fixed) AD9826 Unit Unit MHz Cycles ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality ...
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... Serial Interface Clock Input DI Serial Interface Load Pulse Analog Supply P Analog Ground AO ADC Bottom Reference Voltage Decoupling AO ADC Top Reference Voltage Decoupling AI Analog Input, Blue Channel AO Internal Bias Level Decoupling AI Analog Input, Green Channel AO Clamp Bias Level Decoupling AI Analog Input, Red Channel AD9826 ...
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... The ADC output codes’ standard deviation is calculated in LSB, and can be converted to an equivalent voltage, using the relationship 1 LSB = 4 V/65536 = 61 V. The noise may then be referred to the input of the AD9826 by dividing by the PGA gain. CHANNEL-TO-CHANNEL CROSSTALK In an ideal 3-channel system, the signal in one channel will not influence the signal level of another channel ...
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... GAIN SETTING Typical Performance Characteristics– 1.0 0.5 0 –0.5 –1.0 64000 200 0 1.0 0.5 0 –0.5 –1.0 200 0 64000 AD9826 400 600 800 1000 400 600 800 1000 GAIN SETTING ...
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... AD9826 TIMING DIAGRAMS ANALOG t INPUTS CDSCLK1 t C1C2 CDSCLK2 t ADCLK ADCCLK t ADCLK OUTPUT DATA R(n–2) G(n–2) G(n–2) D<7:0> LOW HIGH BYTE BYTE It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge. ANALOG t INPUTS CDSCLK1 t C1C2 ...
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... BYTE BYTE BYTE PIXEL (n+ C2ADF ADCLK CH2(n–2) CH1(n–1) HIGH LOW HIGH LOW BYTE BYTE BYTE BYTE AD9826 PIXEL (n+2) t PRA CH1(n) CH2(n–1) HIGH LOW HIGH LOW BYTE BYTE BYTE BYTE CH2(n–1) CH1(n) HIGH LOW HIGH LOW BYTE ...
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... AD9826 ANALOG INPUTS CDSCLK2 t ADCLK ADCCLK t ADCLK OUTPUT R (n–2) G (n–2) G (n–2) DATA D<7:0> HIGH LOW BYTE BYTE ANALOG INPUTS CDSCLK2 ADCCLK t t ADCLK ADCLK OUTPUT DATA PIXEL (n–4) PIXEL (n–4) D<7:0> HIGH BYTE LOW BYTE NOTE IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.” ...
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... PIXEL n OEB R/Wb SDATA SCLK t LS SLOAD SDATA R/Wb SCLK t LS SLOAD n+1 n HIGH BYTE DB15–DB8 PIXEL n RDV AD9826 LB HB n+2 n n+2 n ...
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... AD9826 ANALOG INPUTS CDSCLK1 CDSCLK2 ADCCLK RED RED (n–1) PGA OUT GREEN GREEN (n–1) PGA OUT BLUE PGA BLUE (n–1) OUT MUX GREEN (n–1) OUT OUTPUT DATA R(n–2) G(n–2) G(n–2) D<7:0> HIGH LOW BYTE BYTE NOTES 1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE. ...
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... A voltage applied to this pin will be subtracted from the voltages applied to the Red, Green, and Blue inputs in the first amplifier stage of the AD9826. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 5. CDSCLK1 should be grounded in this mode ...
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... Register description). Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the AD9826’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding used ...
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... MUX Configuration Register The MUX Configuration Register controls the sampling chan- nel order and the 2-Channel Mode configuration in the AD9826. Bits D8 and D3–D0 should always be set low. Bit D7 is used when operating in 3-Channel or 2-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the Red channel first, then the Green channel, and then the Blue channel ...
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... S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 F input capacitor, level-shifting the CCD signal into the AD9826’s input common-mode range. The time constant of the input clamp is determined by the internal 5 k resistance and the external 0 ...
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... PGA to maximize the ADC’s dynamic range. 4pF CML S3 4pF CML VRED FROM CIS MODULE AVDD R1 DC OFFSET R2 S1, S2 CLOSED S3 CLOSED AD9826 AD9826 VINR RED RED- SHA OFFSET VING GREEN GREEN- SHA OFFSET VINB BLUE BLUE- SHA OFFSET OFFSET 0 ...
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... AD9826 without the use of coupling capacitors. The analog 3.50 input signals must already be dc-biased between 0 V and 4 V. Also, the OFFSET pin should be grounded if the inputs to the AD9826 are to be referenced to ground offset voltage 2.25 should be applied to the OFFSET pin in the case where a coarse GAIN – V/V offset needs to be removed from the inputs ...
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... Data Sheet changed from REV REV. A. Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to Figure Edits to Figure OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead 5.3 mm SSOP (RS-28) 0.407 (10.34) 0.397 (10.08 0.07 (1.79) PIN 1 0.066 (1.67) 8° 0.0256 0.015 (0.38) 0° SEATING 0.009 (0.229) (0.65) 0.010 (0.25) PLANE BSC 0.005 (0.127) AD9826 0.03 (0.762) 0.022 (0.558) Page ...
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