CS5014-BL28 Cirrus Logic, Inc., CS5014-BL28 Datasheet
CS5014-BL28
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CS5014-BL28 Summary of contents
Page 1
... Monolithic CMOS A/D Converters – Microprocessor Compatible – Parallel & Serial Output – Inherent Track/Hold Input True 12-bit, 14-bit, and 16-bit Precision Conversion Times – CS5016: 16.25 µs – CS5014: 14.25 µs – CS5012A: 7.20 µs ± Linearity Error: 0.001% FS – Guaranteed No Missing Codes Self-calibration Maintains Accuracy – ...
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... Min (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 1) (Note 2) (Note (Note 1) 72 (Note 3) CS5012A CS5014 CS5016 CS5012A VA+, VD+ = 5V; MIN MAX CS5012A Typ Max -40 to +85 ±1/4 ±1/2 ±1/8 ±1/4 ±1/2 ±1/32 ±1/4 ±1/2 ±1/16 ±1/4 ± ...
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... With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection improves the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply rejection versus frequency. DS14F8 DS14F9 (continued) Min (Note 4) 100 (Note 7) (Note 7) (Note 8) CS5012A CS5014 CS5016 CS5012A CS5012A Typ Max -40 to +85 25 100 103 137 ...
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... Noise Unipolar Mode Bipolar Mode Notes detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28 for the CS5016. * Refer to Parameter Definitions (immediately following the pin descriptions at the end of this data sheet). Specifications are subject to change without notice. ...
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... CS5014 ANALOG CHARACTERISTICS Parameter* Specified Temperature Range Analog Input Aperture Time Aperture Jitter Input Capacitance Unipolar Mode Bipolar Mode Conversion & Throughput Conversion Time -14 (Notes 5 and 6) Acquisition Time -14 Throughput -14 Power Supplies DC Power Supply Currents Power Dissipation Power Supply Rejection ...
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... Typ Max Min 0 to +70 (Note 1) (Note (Note 1) (Note 2) (Note 1) (Note 2) (Note 1) (Note 2) (Note 2) (Note 1) 100 85 90 (Note 3) CS5012A CS5014 CS5016 CS5016 VA+, VD+ = 5V; MAX CS5016 Typ Max Min Typ Max -40 to +85 -55 to +125 0.001 0.0015 ±1/4 16 ±2 ±3 ±1 ±1 ± ...
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... DS14F8 DS14F9 (continued) CS5016-J, K CS5016-A, B Min Typ Max Min 0 to +70 25 100 (Note 4) (Note 6) (Note 6) 50 (Note 7) (Note 7) 120 250 (Note 8) CS5012A CS5014 CS5016 CS5016 CS5016-S, T Typ Max Min Typ Max -40 to +85 -55 to +125 25 25 100 100 275 375 165 220 16.25 3.0 3.75 ...
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... Any Digital Output t 1/f hpw CLK CS5012A t 49/f c 57/f CS5014 CS5016 65 (Note 11) t 4/f epw CLK pwl t pwh t 2/f ss CLK t 2/f sh CLK CS5012A, CS5014, CS5016 Min Typ Max - - - +50 - 53/f +235 CLK CLK - 61/f +235 CLK ...
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... Rise and Fall Times t pwl t pwh Serial Output Timing Hi Read and Calibration Control Timing t hpw t c LAST CONVERSION DATA VALID Conversion Timing CS5012A, CS5014, CS5016 Hi epw t dd NEW DATA VALID 2-15 9 ...
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... Negative Analog VREF 2.5 (Note 14) V AGND AIN V -VREF AIN (AGND, DGND = 0V, all voltages with repect to ground.) Symbol (Note 15) VD+ VD- VA+ VA- (Note 16 INA V IND stg CS5012A, CS5014, CS5016 Typ Max Units - - - 0 0 ± 2. -40 A). µ OH out Typ Max Units 5.0 VA+ -5 ...
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... The conversion algorithm op- erates on this fixed charge, and the signal at the analog input pin is ignored. In effect, the entire DAC capacitor array serves as analog memory VREF AGND To MCU CS5012A, CS5014, CS5016 S1 C/X Dummy Bit 0 LSB . Switch S1 is closed tot ...
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... CLKIN (Optional) Figure 3a. Asynchronous Sampling 12 2-18 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 Auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. To achieve complete accuracy from the DAC, the CS5012A/14/16 use a novel self-calibration scheme. Each bit capacitor, shown in Figure 1, actually consists of several capacitors which can be manipulated to adjust the overall bit weight ...
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... A0 Figure 4a. Conversions Asynchronous to CLKIN DS14F8 DS14F9 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 the odd address (A0 high) to avoid initiating a software controlled reset (see Reset below). The calibration control inputs, CAL, and INTRLV are inputs to a set of transparent latches. These signals are internally latched by CS return- ing high ...
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... Master Clock Period) clk CS5012A, CS5014, CS5016 1 / Throughput ( cycles) Conversion ( cycles) * Acquisition (15 cycles) CS5014 CS5016 CLK for CS5016 where f ...
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... CLKIN cycles plus 2.25 µs (1.32 µs for the CS5012A -7 version only) must be allowed for signal acquisition before HOLD is activated. Un- der microprocessor-independent operation (CS, RD low; A0 high) the CS5014’s and CS5016’s EOC output will not fall at the completion of the calibration cycle, but EOT will fall 15 CLKIN cycles later. ...
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... CS5012A and one calibration per 72,051 conversions in the CS5014 and CS5016). This is initiated by bringing both the INTRLV input and CS low (or hard-wiring INTRLV low), interleave extends the CS5012A/14/16’s effective conversion time by 20 CLKIN cycles ...
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... To interface with a 16-bit data bus, the BW input to the CS5012A/14/16 should be held high and all data bits (12, 14 and 16 for the CS5012A, CS5014 and CS5016 respectively) read in paral- lel on pins D4-D15 (CS5012A), D2-D15 (CS5014), or D0-D15 (CS5016). With an 8-bit bus, the converter’s result must be read in two portions. In this instance, BW should be held low and the 8 MSB’ ...
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... The current load on the external reference circuitry thus varies in re- sponse with the analog input. Therefore, the external reference must not exhibit significant CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 DS14F8 DS14F9 ...
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... CLKIN/4. DS14F8 DS14F9 pedance of less than 15 Ω at frequencies greater than 10 kHz. Similarly, for the CS5014 with a 4.5V reference (275µV/LSB), better than 1/4 LSB accuracy can be insured with an output impedance of 4Ω or less (maximum error of 40 µV). A 2.2 µF capacitor exhibits an imped- ance of less than 4Ω ...
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... The recommended refer- ence voltage is between 2.5 and 4.5 V for the CS5012A and 4.5 V for the CS5014/16. The CS5012A/14/16 can actually accept reference voltages up to the positive analog supply. How- ever, the buffer’s offset may increase as the reference voltage approaches VA+ thereby in- creasing external drive requirements at VREF ...
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... CS5014/16 can slew at 5V/µs. In bipolar mode, only half the capacitor array is connected to the analog input so the CS5012A can slew at 40V/ -16 and the CS5014/16 can slew at 10V/µs. After the first six CLKIN cycles, the CS5012A will slew at µ s for pre-charging µ ...
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... AGND pin, which should be used as the entire system’s analog ground reference point. 22 2-28 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 The digital and analog supplies to the CS5012A/14/16 are pinned out separately to minimize coupling between the analog and digital sections of the chip. All four supplies should be decoupled to their respective grounds using µ ...
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... Bows in the transfer curve generate harmonic distortion. The worst-case condition of bit-weight errors (DNL) has traditionally also de- fined the point of maximum INL. 1 MHz Bit-weight errors have a drastic effect on a con- verter’s ac performance. They can be analyzed as step functions superimposed on the input signal. CS5012A, CS5014, CS5016 2-29 23 ...
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... F igur e 14. C S5012A Differ ential Nonlinear ity Plot +1 +1 +1 2-30 2,048 Codes 8,192 Codes F igur e 15. C S5014 Differ ential Nonlinear ity Plot 32,768 Codes F igur e 16. C S5016 Differ ential Nonlinear ity Plot CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 4,095 16,383 65,535 DS14F9 DS14F8 ...
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... CS5012A calibrates its bit weight errors to a small fraction of an LSB at 12-bits yielding peak distortion below the noise floor (see Figure 18). The CS5014 calibrates its bit weights to within ±1/16 LSB at 14-bits (±0.0004% FS) yielding peak distortion as low as -105 dB (see Fig- ure 21). The CS5016 calibrates its bit weights to within ± ...
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... Signal Amplitude Relative to -80dB Full Scale -100dB -120dB Figure 21. CS5014 FFT plot with 1 kHz CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 Sampling Rate: 100kHz Full Scale: 9Vp-p S/N+D: 73.6dB dc 1.0 Input Frequency (kHz) Full Scale Input 0dB Sampling Rate: 56 kHz Full Scale: 9V p-p S/(N+D): 85 ...
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... Best performance at the higher frequencies is achieved with a 2.5 volt reference 100 Input Frequency (kHz) CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 0dB Sampling Rate: 50 kHz Full Scale: 9V p-p S/(N+D): 92 kHz dc Input Frequency Full Scale Input CS5012A-KP7 tested un =100 kSps ...
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... Analog Input Amplitude Figure 27. CS5016 S/(N+D) vs. Input Amplitude (9Vp-p Full-Scale Input) Signal to Noise + Distortion vs Signal Level As illustrated in Figures 25 - 28, the CS5014/16’s on-chip self-calibration provides very accurate bit weights which yield no degradation in quantiza- tion noise with low-level input signals. In fact, quantization noise remains below the noise floor in the CS5016, which dictates the converter’ ...
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... Since the CS5014/16 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converter’s HOLD input falls. It need only acquire the analog input by the time the entire conversion cycle finishes ...
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... External 4MHz External 4MHz Figure 35. Examples of Measured Clock Feedthrough If sampling is performed asynchronously with the master clock, clock feedthrough will appear error at the CS5014/16’s output. With a fixed CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 0dB Sampling Rate: 56 kHz Full Scale: 9V p-p S/(N+D): 64.6 dB ...
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... Also, the overall effect of clock feedthrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5014/16 can be op- erated in bipolar mode which inherently doubles the LSB size over the unipolar mode. DS14F8 ...
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... Generator TST 11 32 REFBUF DGND 0.1 µF 0.1 µF VA- VD Ω CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 RST Function Hold and Start Convert 0 Initiate Burst Calibration 0 Stop Burst Cal and Begin Track 0 Initiate Interleave Calibration 0 Terminate Interleave Cal 0 0 Read Output Data ...
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... HOLD DGND VD D10 D11 D12 D13 D14 D15 DS14F9 CS5012A CS5014 CS5016 CS5012A 10 CS5014 11 CS5016 Top View SDATA SCLK EOC EOT VD- ...
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... When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW and A0. 34 DS14F8 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 DS14F9 2-41 ...
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... CAL is latched low again. Calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/ the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning ...
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... Reference buffer output. A 0.1 Miscellaneous TST – Test, PIN 35. Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be tied to DGND. 36 DS14F8 CS5012A CS5014 CS5016 µ F ceramic capacitor must be tied between this pin and VA-. CS5012A, CS5014, CS5016 DS14F9 2-43 ...
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... The range of variation in the aperture time. Effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. NOTE: Temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. 2-44 DS14F9 CS5012A CS5014 CS5016 CS5012A, CS5014, CS5016 DS14F8 37 ...
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... PACKAGE DIMENSIONS D2/E2 38 CS5012A CS5014 CS5016 44 pin PLCC E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 17.40 D1/E1 16.51 D2/E2 14. NO. OF TERMINALS MILLIMETERS INCHES NOM MAX MIN NOM MAX 4.45 4.57 0.165 0.175 0.180 2.79 3.04 0.090 0.110 0.120 0.41 0.53 0.013 0.016 0.021 17.53 17.65 0.685 0.690 0.695 16.59 16.66 0.650 0.653 0.656 15.50 16.00 0.590 0.610 ...
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... S/N Ratio Linearity 16.25 µ 0.0015% Peak Relfow Temp 225 °C 260 °C 225 °C 260 °C 225 °C 260 °C CS5012A CS5014 CS5016 Temperature Package -40 to +85 °C 44-pin PLCC Temperature Package -40 to +85 °C 44-pin PLCC MSL Rating* Maximum Floor Life 2 2 ...
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... AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks o service marks of their respective owners. 40 www.cirrus.com CS5012A CS5014 CS5016 DS14F9 ...