CS5322-BL Cirrus Logic, Inc., CS5322-BL Datasheet
CS5322-BL
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CS5322-BL Summary of contents
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... AIN- VREF+ VREF- AGND http://www.cirrus.com Description The CS5321/CS5322 chipset functions as a unique A/D converter intended for very high-resolution measurement of signals below 1600 Hz specif- ically designed for applications that require both a high dynamic range and a low total harmonic distor- tion. conversion, and anti-alias filtering. ...
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... CS5321 ABSOLUTE MAXIMUM RATINGS ............................................... 7 CS5322 FILTER CHARACTERISTICS ...................................................... 8 CS5322 POWER SUPPLY ....................................................................... 10 CS5322 SWITCHING CHARACTERISTICS ............................................ 10 CS5322 DIGITAL CHARACTERISTICS ................................................... 15 CS5322 RECOMMENDED OPERATION CONDITIONS ......................... 15 CS5322 ABSOLUTE MAXIMUM RATINGS ............................................. 15 2. GENERAL DESCRIPTION ............................................................................ 16 2.1. Analog Input ...................................................................................... 18 2.2. The OFST Pin.................................................................................... 18 2.3. Input Range and Overrange Conditions ............................................ 19 2.4. Voltage Reference ............................................................................. 20 2.5. Clock Source ..................................................................................... 20 2 ...
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... Figure 24. 1024 Point FFT Plot with Full Scale Input, 100 Hz Input, HBR = 0, ten averages ............................................. 22 LIST OF TABLES Table 1. Output Coding for the CS5321 and CS5322 Combination ....................... 21 Table 2. Configuration Data Bits ............................................................................ 25 Table 3. Status Data (from the SOD Pin) ............................................................... 26 Table 4. Bandwidth Selection: Truth Table ............................................................ 27 DS454F3 = 62 ...
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... DR (Note 3) SDR HBR = 1 HBR = 0 (Note 4) IMD (Note 5) FSE (Note 5, (Note 5) V ZSE (Note 7) (Note 8) (Note 5,6) TC ZSE +85 C, CS5322-BL is guaranteed from -40 CS5321/ ss1 ss2 dd1 dd2 CS5321 Min Typ Max Unit - 103 - dB - 118 - dB 116 121 ...
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... Notes: 9. The upper bandwidth limit is determined by the CS5322 digital filter. 10. This input voltage range is for the configuration shown in Figure 20, the System Connection Diagram, and applies to signal from Hz. Refer to CS5322 Filter Characteristics for the values of f3. 11. All outputs unloaded. All logic inputs forced ...
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CS5321 SWITCHING CHARACTERISTICS = -5 V ± 5%; Inputs: Logic Logic ss2 Parameter MCLK Frequency MCLK Duty Cycle MCLK Jitter (In-band) Rise Times: Any Digital Input Any Digital Output Fall Times: ...
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... V, See Note 20) Parameter DC Supply: Ambient Operating Temperature Notes: 20. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5321 ABSOLUTE MAXIMUM RATINGS * Parameter DC Supply: Input Current, Any Pin Except Supplies ...
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... Note 1); VD+ = 5.0 V; GND = Passband Flatness -3dB Freq (dB) (Hz) PB 0.2 1652.5 0.04 824.3 0.08 411.9 0.1 205.9 0.1 102.9 0.1 51.5 0.1 25 Figure 6. CS5322 Digital Filter Passband Ripple CS5321/22 Stopband f3 (Hz) Group Delay (Note 22) (ms) 2000 7.25 1000 14.5 500 29 250 58 125 116 62.5 232 31.25 464 250 Hz ...
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... Figure 11. CS5322 Impulse Response 62 DS454F3 Figure 8. CS5322 Digital Filter Passband Ripple Figure 10. CS5322 Digital Filter Passband Ripple -5 ,2 06, 12, 18, 25, 31, 37, 43, 50,00 0 ...
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... CS5321/22 CS5322-BL Typ Max Unit 2 0.6 2.5 mW Min Typ Max Units 0.512 1.024 1.2 MHz 100 100 100 100 ...
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... rdd t t rph rpl rds Serial Port Read Timing Serial Port Write Timing Figure 13. CS5322 Serial Port Timing CS5321/22 t rst t rhc t rch H i-Z LSB rsp ...
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... CS5322 SWITCHING CHARACTERISTICS Parameter Test Data (TDATA) Timing SYNC Setup Time to CLKIN rising SYNC Hold Time after CLKIN rising TDATA Setup Time to CLKIN rising after SYNC TDATA Hold Time after CLKIN rising ORCAL Setup Time to CLKIN rising ORCAL Hold Time after CLKIN rising ...
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rite ...
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... Symbol (Note 24 (Note 25) t rise (Note 25) t fall mss t msh (Note 26) t msd Figure 17. CS5321/CS5322 Interface Timing CS5321/22 Min Typ Max Units 0.512 1.024 1 100 - 50 200 - - 100 - 50 200 ...
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... Parameter DC Supply: Positive Negative Ambient Operating Temperature Notes: 29. The maximum voltage differential between the Positive Supply of the CS5321 and the Positive Digital Supply of the CS5322 must be less than 0.25 V. CS5322 ABSOLUTE MAXIMUM RATINGS * Parameter DC Supply: Positive Negative Input Current, Any Pin Except Supplies ...
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... The CS5321 is a fourth-order CMOS monolithic analog modulator designed specifically for very high resolution measurement of signals between dc and 1600 Hz. Configuring the CS5321 with the CS5322 FIR filter results in a high resolution A/D converter system that performs sampling and A/D conversion with a dynamic range exceeding 120 dB. ...
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... Figure 19. CS5322 Block Diagram CS5321/ ...
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... Figure 20 illustrates the CS5321 and CS5322 sys- tem connections. The input components on AINR and AIN+ should be identical values for optimum performance. In choosing the components the ca- pacitor should be a minimum of 0.1 µ ...
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... If this occurs the MFLG pin will transi- tion from a low to a high and result in an error bit being set in the CS5322. The input signal must be reduced to within the full scale range of the con- verter for at least 32 MCLK cycles for the modula- tor to recover from this error condition. µ ...
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... S/N slightly lower (1-2 dB) than when using a 4.5 V reference. The voltage reference should be de- signed to yield less than 2 µVrms of noise in band at the VREF+ pin of the CS5321. The CS5322 filter selection will determine the bandwidth over which the voltage reference noise will affect the CS5321/22 dynamic range ...
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... MCLK/8. The chip set will ex- hibit about 3 dB less S/N performance when the HBR pin is changed from a logic "1" logic "0" for the same output word rate from the CS5322. 2.6 Low Power Mode The CS5321 includes a low power operating mode (LPWR =1) ...
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Performance Figure 22, 23 and 24 illustrate the spectral perfor- mance of the CS5321/22 and chipset when operat- ing from a 1.024 MHz master clock. Ten 1024 point FFTs were averaged to produce the plots. Figure 22 illustrates the ...
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... PWDN is as- serted before CLKIN stops. The CS5322 exits the power-down state on the first CLKIN rising edge after the PWDN pin is brought low. The CS5322 then enters an idle state until trig- gered by a SYNC event. CS5321/22 23 ...
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... CSEL and TDATA must not both be asserted high. 2.13 SYNC Operation The SYNC pin is used to start convolutions and synchronize the CS5322 and CS5321 to an external sampling source or timing reference. The SYNC event is recognized on the first CLKIN rising edge after the SYNC pin goes high. SYNC may remain high indefinitely ...
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... The results of the last calibration will be held in the offset register until the end of a new calibra- tion, or until the CS5322 is reset using the RESET pin. USEOR does not alter the offset register value, only its usage. ...
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... Any high level on the CS5322 MFLG pin will set the MFLG status bit. The bit is cleared on a status register read or RESET operation, only if the MFLG pin on the CS5322 has returned low. A in- ternal nominal 100 kΩ pulldown resistor is on the MFLG pin. ...
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... In host mode (H/S=0) they follow the corresponding configura- tion bits. A brief explanation of the eight bits are as follows: PWDN - When high, indicates that the CS5322 is in the power-down state. ORCAL - When high, indicates a potential calibra- tion start. USEOR - When high, indicates the Offset Register is used ...
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Board Layout Considerations All of the 0.1 µF filter capacitors on the power sup- plies, AIN+, and AINR, should be placed very close to the chip and connect to the nearest ground pin on the device. The capacitors between ...
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CS5321 PIN DESCRIPTIONS Power Supplies V Positive Power One, PIN 2 dd1 – Positive supply voltage. Nominally +5 Volts. V Positive Power Two, PIN 22 dd2 – Positive supply voltage. Nominally +5 Volts. V Negative Power One, PIN 3 ...
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... A CMOS-compatible clock input to this pin (nominally 1.024 MHz) provides the necessary clock for operation of the modulator and data output portions of the A/D converter. MCLK is normally supplied by the CS5322 MSYNC – Modulator Sync, PIN 25 A transition from a low to high level on this input will re-initialize the CS5321. MSYNC resets a divider-counter to align the MDATA output bit stream from the CS5321 with the timing inside the CS5322 ...
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... CS5322 PIN DESCRIPTIONS CHIP SELECT FRAME SYNC CLOCK INPUT CLKIN RESET RESET MODULATOR SYNC MSYNC MODULATOR FLAG MODULATOR CLOCK POSITIVE DIGITAL POWER DIGITAL GROUND DGND MODULATOR DATA MDATA TEST DATA TDATA CHANNEL SELECT HARDWARE/SOFTWARE MODE POWER DOWN PWDN Power Supplies VD+ – Positive Digital Power, Pin 8, 21 Positive digital supply voltage. Nominally +5 volts. DGND – ...
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SOD - Serial Output Data, Pin 24 The output coding is 2’s complement with the data bits presented MSB first, LSB last. Data changes on the rising edge of SCLK. An internal nominal 100 kΩ pull-up resistor is included. Digital ...
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DECC - Decimation Rate Control, Pin 16 See Table 4. H/S - Hardware/Software Mode Select, Pin 13 When high, the device pins control device operation; when low, the value entered by a prior configuration write controls device operation ...
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... CS5321/22 of 000000(H). Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in mV. Offset Drift The change in the Offset value with temperature. Measurement of this parameter uses the circuit configuration illustrated in the System Connection Diagram. Units in µV/°C. 34 CS5321/22 Hz (See “CS5322 3 Hz. 3 DS454F3 ...
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PACKAGE DIMENSIONS 28L PLCC PACKAGE DRAWING DIM DS454F3 INCHES MIN MAX MIN 0.165 0.180 4.043 0.090 0.120 2.205 0.013 0.021 0.319 0.485 0.495 11.883 0.450 ...
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... CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free) 8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5321-BL CS5321-BLZ (Lead Free) CS5322-BL CS5322-BLZ (Lead Free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 9. REVISION HISTORY Revision Date PP3 OCT 2003 Initial Release. F1 AUG 2005 Update ordering information ...