MC68HC908GZ48CFA Freescale Semiconductor, Inc, MC68HC908GZ48CFA Datasheet
MC68HC908GZ48CFA
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MC68HC908GZ60 MC68HC908GZ48 MC68HC908GZ32 Data Sheet M68HC08 Microcontrollers MC68HC908GZ60 Rev. 6.0 04/2007 freescale.com ...
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...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2006, 2007. All rights reserved. ...
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Revision Date Level April, N/A Initial release 2004 9.7.3 Keyboard Interrupt ...
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Revision History (Continued) Revision Date Level 12.2 Features — Corrected timer link connection from TIM2 channel 0 to TIM1 channel 0. 12.9 Timer Link — Corrected timer link connection from TIM2 channel 0 to October, 5.0 TIM1 channel 0. 2006 ...
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Revision History MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.6.6 FLASH-1 Program Operation ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents Computer Operating Properly (COP) Module 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 10.10 Enhanced Serial Communications Interface Module (ESCI 126 10.10.1 Wait Mode ...
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Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 13.6 Port ...
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ESCI Control Register ...
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Table of Contents Serial Peripheral Interface (SPI) Module 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Clock Generation Module (CGM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...
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Chapter 1 General Description 1.1 Introduction The MC68HC908GZ60, MC68HC908GZ48, and MC68HC908GZ32 are members of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available ...
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General Description • Standard low-power modes of operation: – Wait mode – Stop mode • Master reset pin and power-on reset (POR) • On-chip FLASH memory: – MC68HC908GZ60 — 60 Kbytes – MC68HC908GZ48 — 48 Kbytes – MC68HC908GZ32 — 32 ...
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Specific features in 48-pin LQFP are: – Port bits: PTA0–PTA7; shared with ADC and KBI modules – Port bits: PTB0–PTB7; shared with ADC module – Port C is only 7 bits: PTC0–PTC6; shared ...
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General Description M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 62,078 BYTES USER RAM — 2048 BYTES MONITOR ROM USER FLASH VECTOR SPACE — 52 BYTES CLOCK GENERATOR MODULE OSC1 1–8 ...
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PTE0/TxD PTE1/RxD PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS/MCLK PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 Figure 1-3. 48-Pin LQFP Pin Assignments MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. ...
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General Description 64 63 RST 1 PTE0/TxD 2 PTE1/RxD 3 PTE2 4 PTE3 5 PTE4 6 PTE5 7 PTF0 8 PTF1 9 PTF2 10 PTF3 11 IRQ 12 PTD0/SS/MCLK 13 PTD1/MISO 14 PTD2/MOSI 15 PTD3/SPSCK Figure ...
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Note: Component values shown represent typical applications. 1.5.2 Oscillator Pins (OSC1 and OSC2) OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A low on ...
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General Description V is the low reference supply for the ADC, and by default the V REFL to the same voltage potential as V 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7/AD15–PTA0/KBD0/AD8) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or ...
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Port F I/O Pins (PTF7/T2CH5–PTF0) PTF7–PTF4 are special-function, bidirectional I/O port pins that can be individually programmed to be timer interface module (TIM2) pins. PTF3–PTF0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability. PTF7–PTF0 are ...
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General Description MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...
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Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • 62,078 bytes of user FLASH memory • 2048 bytes of random-access memory (RAM) • 52 bytes of user-defined vectors 2.2 ...
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Memory • $FF81; FLASH-2 block protect register, FL2BPR • $FF88; FLASH-1 control register, FL1CR Data registers are shown in Figure $0000 I/O REGISTERS ↓ 64 BYTES $003F $0040 RAM-1 ↓ 1024 BYTES $043F $0440 I/O REGISTERS ↓ 34 BYTES $0461 ...
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Addr. Register Name Read: Port A Data Register $0000 (PTA) Write: See page 173. Reset: Read: Port B Data Register $0001 (PTB) Write: See page 176. Reset: Read: Port C Data Register $0002 (PTC) Write: See page 178. Reset: Read: ...
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Memory Addr. Register Name Read: Data Direction Register E $000C (DDRE) Write: See page 184. Reset: Read: Port A Input Pullup Enable $000D Register (PTAPUE) Write: See page 175. Reset: Read: Port C Input Pullup Enable $000E Register (PTCPUE) Write: ...
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Addr. Register Name Read: ESCI Data Register $0018 (SCDR) Write: See page 212. Reset: Read: ESCI Baud Rate Register $0019 (SCBR) Write: See page 212. Reset: Read: Keyboard Status and Control $001A Register (INTKBSCR) Write: See page 120. Reset: Read: ...
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Memory Addr. Register Name Read: TIM1 Counter Modulo $0024 Register Low (T1MODL) Write: See page 273. Reset: Read: TIM1 Channel 0 Status and $0025 Control Register (T1SC0) Write: See page 274. Reset: Read: TIM1 Channel 0 $0026 Register High (T1CH0H) ...
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Addr. Register Name Read: TIM2 Channel 0 Status and $0030 Control Register (T2SC0) Write: See page 293. Reset: Read: TIM2 Channel 0 $0031 Register High (T2CH0H) Write: See page 297. Reset: Read: TIM2 Channel 0 $0032 Register Low (T2CH0L) Write: ...
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Memory Addr. Register Name Read: ADC Status and Control $003C Register (ADSCR) Write: See page 68. Reset: Read: ADC Data High Register $003D (ADRH) Write: See page 70. Reset: Read: ADC Data Low Register $003E (ADRL) Write: See page 70. ...
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Addr. Register Name Read: TIM2 Channel 3 Status and $0459 Control Register (T2SC3) Write: See page 293. Reset: Read: TIM2 Channel 3 $045A Register High (T2CH3H) Write: See page 297. Reset: Read: TIM2 Channel 3 $045B Register Low (T2CH3L) Write: ...
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Memory Addr. Register Name Read: Break Flag Control Register $FE03 (BFCR) Write: See page 238. Reset: Read: Interrupt Status Register 1 $FE04 (INT1) Write: See page 231. Reset: Read: Interrupt Status Register 2 $FE05 (INT2) Write: See page 233. Reset: ...
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Addr. Register Name Read: FLASH-1 Block Protect Register (FL1BPR) (1) $FF80 Write: See page 47. Reset: Read: FLASH-2 Block Protect Register (FL2BPR) (1) $FF81 Write: See page 54. Reset: 1. Non-volatile FLASH register Read: FLASH-1 Control Register $FF88 (FL1CR) Write: ...
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Memory Table 2-1. Vector Addresses (Continued) Vector Priority Highest MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Vector Address $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) IF14 $FFE1 ...
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Random-Access Memory (RAM) The RAM locations are broken into two non-continuous memory blocks. The RAM addresses locations are $0040–$043F and $0580–$097F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere ...
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Memory Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents. 2.6.2 FLASH-1 Control and Block Protect Registers The FLASH-1 array has two registers that control its ...
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FLASH-1 Block Protect Register The FLASH-1 block protect register (FL1BPR) is implemented as a byte within the FLASH-1 memory; therefore, it can only be written during a FLASH programming sequence. The value in this register determines the starting location ...
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Memory 2.6.3 FLASH-1 Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due ...
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B. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. However, care must be taken to ensure that these operations do not access any address within the FLASH array memory space ...
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Memory During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail. Use this step-by-step procedure to ...
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Algorithm for programming a row (64 bytes) of FLASH memory NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step10) ...
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Memory 2.6.7 Low-Power Modes The WAIT and STOP instructions will place the MCU in low power-consumption standby modes. 2.6.7.1 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of ...
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Programming tools are available from Freescale. Contact your local Freescale representative for more information. A security feature prevents viewing of the FLASH contents. 2.7.2 FLASH-2 Control and Block Protect Registers The FLASH-2 array has two registers that control its operation, ...
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Memory 2.7.2.2 FLASH-2 Block Protect Register The FLASH-2 block protect register (FL2BPR) is implemented as a byte within the FLASH-1 memory; therefore, can only be written during a FLASH-1 programming sequence. The value in this register determines the starting location ...
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Decreasing the value in FL2BPR by one increases the protected range by one page (128 bytes). However, programming the block protect register with $FE protects a range twice that size, 256 bytes, in the corresponding array. $FE means that locations ...
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Memory (minimum 100 μs). 8. Wait for a time, t NVHL 9. Clear the HVEN bit. , (typically 1 μs) after which the memory can be accessed in normal read mode. 10. Wait for a time, t RCV A. Programming ...
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FLASH-2 Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 64 consecutive bytes with address ranges as follows: • $XX00 to $XX3F • $XX40 to $XX7F • $XX80 to $XXBF • ...
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Memory E. The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, ...
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Algorithm for programming a row (64 bytes) of FLASH memory NOTES: The time between each FLASH address change (step 7 to step 7) or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step10) ...
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Memory MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev Freescale Semiconductor ...
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the 10-bit analog-to-digital converter (ADC). 3.2 Features Features of the ADC module include: • 24 channels with multiplexed input • Linear successive approximation with monotonicity • 10-bit resolution • Single ...
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Analog-to-Digital Converter (ADC) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 62,078 BYTES USER RAM — 2048 BYTES MONITOR ROM USER FLASH VECTOR SPACE — 52 BYTES CLOCK GENERATOR MODULE OSC1 ...
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INTERNAL DATA BUS READ DDRx WRITE DDRx RESET WRITE PTx READ PTx CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO CGMXCLK BUS CLOCK 3.3.2 Voltage Conversion When the input voltage to the ADC equals V input voltage equals V the ADC converts ...
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Analog-to-Digital Converter (ADC) 3.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide ...
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Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result, represented as a signed magnitude ...
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Analog-to-Digital Converter (ADC) 3.6 Low-Power Modes The WAIT and STOP instruction can put the MCU in low power- consumption standby modes. 3.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC ...
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ADC Voltage Reference High Pin (V The ADC analog portion uses V pin to the same voltage potential as V good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. For ...
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Analog-to-Digital Converter (ADC) 3.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: $003C Bit 7 Read: COCO Write: R Reset Reserved Figure 3-4. ADC Status and Control ...
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The voltage levels supplied from internal reference nodes, as specified in operation of the ADC converter both in production test and for user applications. ADCH4 ADCH3 ...
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Analog-to-Digital Converter (ADC) 3.8.2 ADC Data Register High and Data Register Low 3.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The ADRL register holds the two LSBs of the ...
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Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds ...
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Analog-to-Digital Converter (ADC) 3.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: $003F Bit 7 Read: ADIV2 Write: Reset: 0 Figure 3-9. ADC Clock Register (ADCLK) ADIV2–ADIV0 — ADC Clock Prescaler Bits ...
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Chapter 4 Clock Generator Module (CGM) 4.1 Introduction This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, ...
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Clock Generator Module (CGM) OSCILLATOR (OSC) OSC2 OSC1 SIMOSCEN (FROM SIM) OSCENINSTOP (FROM CONFIG) PHASE-LOCKED LOOP (PLL) V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 CGMVDV FREQUENCY DIVIDER MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev CGMRCLK BCS ...
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Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration ...
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Clock Generator Module (CGM) frequency The circuit determines the mode of the PLL and the lock condition based on this RCLK comparison. 4.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of ...
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The following conditions apply when in manual mode: • ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. • Before entering tracking ...
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Clock Generator Module (CGM) In cases where desired bus frequency has some tolerance, choose f either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See ...
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Program the PLL registers accordingly the VPR bits of the PLL control register (PCTL), program the binary equivalent the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), ...
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Clock Generator Module (CGM) 4.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in ...
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I/O Signals The following paragraphs describe the CGM I/O signals. 4.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 4.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output ...
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Clock Generator Module (CGM) 4.4.8 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f directly from the crystal oscillator circuit. and OSC2 and may not represent the ...
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Addr. Register Name Read: PLL Multiplier Select Low $0039 Register (PMSL) Write: See page 86. Reset: Read: PLL VCO Select Range $003A Register (PMRS) Write: See page 87. Reset: Read: $003B Reserved Register Write: Reset: NOTES: 1. When AUTO = ...
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Clock Generator Module (CGM) Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO ...
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PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): • Selects automatic or manual (software-controlled) bandwidth control mode • Indicates when the PLL is locked • In automatic bandwidth control mode, indicates when the PLL is in acquisition ...
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Clock Generator Module (CGM) 4.5.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: $0038 Bit 7 Read: 0 Write: Reset ...
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MUL7–MUL0 — Multiplier Select Bits These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See be written when the PLLON bit in the PCTL is set. A value of $0000 ...
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Clock Generator Module (CGM) 4.6 Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL ...
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Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 4.8.1 Acquisition/Lock Time ...
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Clock Generator Module (CGM) External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even ...
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: • Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • COP timeout period ...
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Configuration Register (CONFIG) Address: $001E Bit 7 Read: 0 MCLKSEL Write: Reset: 0 Note: MSCANEN is only reset via POR (power-on reset). = Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) MCLKSEL — MCLK Source Select Bit 1 = Crystal frequency ...
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OSCENINSTOP — Oscillator Enable In Stop Mode Bit OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See Chapter 4 Clock Generator Module the rest of the MCU stops. See cease to generate clocks ...
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Configuration Register (CONFIG) LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module (see (LVI)). The voltage mode selected for the LVI should match the operating V Electrical Specifications) for the ...
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Chapter 6 Computer Operating Properly (COP) Module 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset ...
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Computer Operating Properly (COP) Module The COP counter is a free-running 6-bit counter preceded by the 12-bit SIM counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 CGMXCLK cycles, depending ...
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COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Chapter 5 Configuration Register (CONFIG). 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP ...
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Computer Operating Properly (COP) Module To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution ...
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...
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Central Processor Unit (CPU 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 7.3.2 Index Register The ...
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Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...
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Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 8.2 Features Features of the IRQ module include: • A dedicated external interrupt pin (IRQ) • IRQ interrupt control bits • Hysteresis buffer ...
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External Interrupt (IRQ) RESET ACK VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set until both of these events occur: • Vector fetch ...
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IRQ Pin A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is ...
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External Interrupt (IRQ) 8.6 IRQ Status and Control Register The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: • Shows the state of the IRQ flag • Clears the IRQ latch • ...
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0–PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup/pulldown device is also ...
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Keyboard Interrupt Module (KBI) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 62,078 BYTES USER RAM — 2048 BYTES MONITOR ROM USER FLASH VECTOR SPACE — 52 BYTES CLOCK GENERATOR MODULE ...
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The KBIP7–KBIP0 bits determine the polarity of the keyboard pin detection. These bits along with the MODEK bit determine whether a logic level ( and/or a falling (or rising) edge is being detected. • If the keyboard interrupt ...
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Keyboard Interrupt Module (KBI) If the MODEK bit is set and depending on the KBIPx bit, the keyboard interrupt pins are both falling (or rising) edge and low (or high) level sensitive, and both of the following actions must occur ...
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An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to ...
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Keyboard Interrupt Module (KBI) 9.7.1 Keyboard Status and Control Register The keyboard status and control register: • Flags keyboard interrupt requests • Acknowledges keyboard interrupt requests • Masks keyboard interrupt requests • Controls keyboard interrupt triggering sensitivity Address: $001A Bit ...
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Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin. Address: $001B Bit 7 Read: KBIE7 Write: Reset: 0 Figure 9-5. Keyboard Interrupt Enable Register (INTKBIER) ...
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Keyboard Interrupt Module (KBI) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 122 Freescale Semiconductor ...
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Chapter 10 Low-Power Modes 10.1 Introduction The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in ...
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Low-Power Modes 10.3 Break Module (BRK) 10.3.1 Wait Mode The break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the ...
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Computer Operating Properly Module (COP) 10.6.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 10.6.2 Stop Mode Stop mode turns off the CGMXCLK input to the COP ...
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Low-Power Modes 10.9 Low-Voltage Inhibit Module (LVI) 10.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of ...
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Timer Interface Module (TIM1 and TIM2) 10.12.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are ...
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Low-Power Modes 10.15 Exiting Wait Mode These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: • External reset — A low on the RST pin resets the MCU and ...
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MSCAN module interrupt — A CPU interrupt request from the MSCAN08 loads the program counter with the contents of: – $FFD4 and $FFD5; MSCAN08 transmitter – $FFD6 and $FFD7; MSCAN08 receiver – $FFD8 and $FFD9; MSCAN08 error – $FFDA ...
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Low-Power Modes MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 130 Freescale Semiconductor ...
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Chapter 11 Low-Voltage Inhibit (LVI) 11.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V and can force a reset when the V 11.2 Features Features of the LVI module include: • Programmable ...
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Low-Voltage Inhibit (LVI) LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 5-2. Configuration Register 1 (CONFIG1) reset occurs, the MCU remains in reset until V to exit reset. See 15.3.2.5 Low-Voltage Inhibit (LVI) Reset and ...
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Voltage Hysteresis Protection Once the LVI has triggered (by having V V rises above the rising trip point voltage continually entering and exiting reset the hysteresis voltage, V TRIPF 11.3.4 LVI Trip Selection ...
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Low-Voltage Inhibit (LVI) 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 11.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module ...
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Chapter 12 MSCAN08 Controller (MSCAN08) 12.1 Introduction The MSCAN08 is the specific implementation of the scalable controller area network (MSCAN) concept targeted for the M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as ...
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MSCAN08 Controller (MSCAN08) M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 62,078 BYTES USER RAM — 2048 BYTES MONITOR ROM USER FLASH VECTOR SPACE — 52 BYTES CLOCK GENERATOR MODULE OSC1 ...
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External Pins The MSCAN08 uses two external pins, one input (CAN pin represents the logic level on the CAN for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is ...
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MSCAN08 Controller (MSCAN08) completed within the inter-frame sequence (IFS able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the ...
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MSCAN08 Figure 12-3. User Model for Message Buffer Organization 12.4.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers ...
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MSCAN08 Controller (MSCAN08) To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see MSCAN08 Transmitter Flag Register). The ...
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Two identifier acceptance filters, each to be applied to: a. The 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages The 11 bits of the identifier plus the ...
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MSCAN08 Controller (MSCAN08) ID28 IDR0 ID21 ID10 IDR0 ID3 AM7 CIDMR0 AM0 AC7 CIDAR0 AC0 ID ACCEPTED (FILTER 0 HIT) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID ACCEPTED (FILTER 1 HIT) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID ACCEPTED (FILTER ...
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Interrupts The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked. For details, see through 12.13.8 MSCAN08 Transmitter Control 1. Transmit Interrupt: At least one of the three transmit buffers ...
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MSCAN08 Controller (MSCAN08) Table 12-1. MSCAN08 Interrupt Vector Addresses Function Wakeup Error interrupts Receive Transmit 12.7 Protocol Violation Protection The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following ...
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Table 12-2. MSCAN08 versus CPU Operating Modes MSCAN08 Mode Power Down Sleep Soft Reset Normal 1. ‘X’ means don’t care. 12.8.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit ...
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MSCAN08 Controller (MSCAN08) During sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ into sleep mode. When in sleep mode, the MSCAN08 stops its internal clocks. ...
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MSCAN08 bus activity can wake the MCU from CPU stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronization is achieved the MSCAN08 will not respond to incoming data. 12.8.4 CPU Wait Mode The MSCAN08 module remains active during ...
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MSCAN08 Controller (MSCAN08) OSC CGM MSCAN08 ÷ programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08. A bit ...
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The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See 12.13.3 MSCAN08 Bus Timing Register the user’s responsibility to make sure that the bit timing settings are in compliance with the ...
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MSCAN08 Controller (MSCAN08) 12.11 Memory Map The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128. MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 ...
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Programmer’s Model of Message Storage This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each ...
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MSCAN08 Controller (MSCAN08) 12.12.1 Message Buffer Outline Figure 12-12 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in the 13-byte data structure are ...
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Addr. Register Read: $05b0 IDR0 Write: Read: $05b1 IDR1 Write: Read: $05b2 IDR2 Write: Read: $05b3 IDR3 Write: Figure 12-13. Standard Identifier Mapping 12.12.2 Identifier Registers The identifiers consist of either 11 bits (ID10–ID0) for the standard bits ...
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MSCAN08 Controller (MSCAN08) 12.12.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3–DLC0 — Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective ...
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Programmer’s Model of Control Registers The programmer’s model has been laid out for maximum simplicity and efficiency. overview on the control register block of the MSCAN08. Addr. Register Bit 7 Read: $0500 CMCR0 Write: Read: $0501 CMCR1 Write: Read: ...
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MSCAN08 Controller (MSCAN08) Addr. Register Bit 7 Read: $0514 CIDMR0 AM7 Write: Read: $0515 CIDMR1 AM7 Write: Read: $0516 CIDMR2 AM7 Write: Read: $0517 CIDMR3 AM7 Write: Figure 12-15. MSCAN08 Control Register Structure (Continued) 12.13.1 MSCAN08 Module Control Register 0 ...
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SFTRES — Soft Reset When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers enter and stay ...
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MSCAN08 Controller (MSCAN08) CLKSRC — Clock Source This flag defines which clock source the MSCAN08 module is driven from (see 1 = The MSCAN08 clock source is CGMOUT (see 0 = The MSCAN08 clock source is CGMXCLK/2 (see The CMCR1 ...
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The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set. 12.13.4 MSCAN08 Bus Timing Register 1 Address: $0503 Bit 7 Read: SAMP Write: Reset: 0 Figure 12-19. Bus Timing Register 1 ...
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MSCAN08 Controller (MSCAN08) 12.13.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing the corresponding bit position. A flag can be cleared only when ...
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TERRIF — Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the transmit error counter exceeding 127 and the bus-off interrupt flag is not set while this flag is set. ...
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MSCAN08 Controller (MSCAN08) 12.13.6 MSCAN08 Receiver Interrupt Enable Register Address: $0505 Bit 7 Read: WUPIE Write: Reset: 0 Figure 12-21. Receiver Interrupt Enable Register (CRIER) WUPIE — Wakeup Interrupt Enable wakeup event will result in a wakeup ...
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MSCAN08 Transmitter Flag Register The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag can be cleared by writing the corresponding bit position. Writing a 0 has ...
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MSCAN08 Controller (MSCAN08) 12.13.8 MSCAN08 Transmitter Control Register Address: $0507 Bit 7 Read: 0 Write: Reset: 0 Figure 12-23. Transmitter Control Register (CTCR) ABTRQ2–ABTRQ0 — Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message ...
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IDAM2–IDAM0— Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see Acceptance Filter). Table 12-9 will be accepted so that the foreground buffer will never be reloaded. Table 12-9. Identifier Acceptance Mode Settings IDAM2 ...
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MSCAN08 Controller (MSCAN08) 12.13.11 MSCAN08 Transmit Error Counter Address: $050F Bit 7 Read: TXERR7 Write: Reset: 0 Figure 12-26. Transmit Error Counter (CTXERR) This read-only register reflects the status of the MSCAN08 transmit error counter. Both error counters may only ...
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AC7–AC0 — Acceptance Code Bits AC7–AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the ...
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MSCAN08 Controller (MSCAN08) MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6 168 Freescale Semiconductor ...
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Chapter 13 Input/Output (I/O) Ports 13.1 Introduction Bidirectional input-output (I/O) pins form seven parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, port D and port F are software configurable ...
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Input/Output (I/O) Ports Addr. Register Name Read: Data Direction Register A $0004 (DDRA) Write: See page 174. Reset: Read: Data Direction Register B $0005 (DDRB) Write: See page 176. Reset: Read: Data Direction Register C $0006 (DDRC) Write: See page ...
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Addr. Register Name Read: Data Direction Register F (DDRF) $0444 Write: See page 185. Reset: Read: Data Direction Register G (DDRG) $0445 Write: See page 187. Reset: Figure 13-1. I/O Port Register Summary (Sheet Table 13-1. Port ...
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Input/Output (I/O) Ports Table 13-1. Port Control Register Bits Summary (Continued) Port Bit DDR Module Control 0 DDRD0 1 DDRD1 SPI 2 DDRD2 3 DDRD3 D 4 DDRD4 TIM1 5 DDRD5 6 DDRD6 TIM2 7 DDRD7 0 DDRE0 SCI 1 ...
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Port A Port 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module and the ADC module. Port A also has software configurable pullup devices if configured as an input ...
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Input/Output (I/O) Ports 13.3.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing DDRA bit enables the output buffer for the corresponding port ...
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PTAPUE DDRA PTA Bit Bit Bit ( Don’t care 2. I/O pin pulled internal pullup device DD 3. Writing affects data register, but does ...
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Input/Output (I/O) Ports 13.4 Port B Port 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 13.4.1 Port B Data Register The port B data register (PTB) contains a data ...
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DDRB7–DDRB0 — Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7–DDRB0, configuring all port B pins as inputs Corresponding port B pin configured as output 0 = Corresponding port B pin ...
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Input/Output (I/O) Ports 13.5 Port C Port 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. PTC[1:0] are shared with the MSCAN module. 13.5.1 Port C Data ...
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DDRC6–DDRC0 — Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC6–DDRC0, configuring all port C pins as inputs Corresponding port C pin configured as output 0 = Corresponding port C pin ...
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Input/Output (I/O) Ports 13.5.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that ...
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T1CH1 and T1CH0 — Timer 1 Channel I/O Bits The PTD7/T1CH1–PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1–PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. ...
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Input/Output (I/O) Ports When bit DDRDx reading address $0003 reads the PTDx data latch. When bit DDRDx reading address $0003 reads the voltage level on the pin. The data latch can always be written, ...
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PTDPUE7–PTDPUE0 — Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin ...
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Input/Output (I/O) Ports 13.7.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing DDRE bit enables the output buffer for the corresponding port ...
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Port F Port 8-bit special-function port that shares four of its pins with the timer interface (TIM2) module. 13.8.1 Port F Data Register The port F data register (PTF) contains a data latch for each of ...
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Input/Output (I/O) Ports READ DDRF ($0444) WRITE DDRF ($0444) WRITE PTF ($0440) READ PTD ($0440) When bit DDRFx reading address $0440 reads the PTFx data latch. When bit DDRFx reading address $0440 reads the ...
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PTG7–PTG0 — Port G Data Bits These read/write bits are software-programmable. Data direction of each port G pin is under the control of the corresponding bit in data direction register G. Reset has no effect on port G data. AD23–AD16 ...
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Input/Output (I/O) Ports READ DDRG ($0445) WRITE DDRG ($0445) WRITE PTG ($0441) READ PTG ($0441) DDRG PTG I/O Pin Bit Bit Mode ( Input, Hi Output Don’t care 2. Hi-Z = High impedance ...
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Chapter 14 Enhanced Serial Communications Interface (ESCI) Module 14.1 Introduction The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU). 14.2 Features Features include: • Full-duplex operation • Standard mark/space non-return-to-zero (NRZ) ...
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Enhanced Serial Communications Interface (ESCI) Module M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 62,078 BYTES USER RAM — 2048 BYTES MONITOR ROM USER FLASH VECTOR SPACE — 52 BYTES CLOCK ...
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Pin Name Conventions The generic names of the ESCI input/output (I/O) pins are: • RxD (receive data) • TxD (transmit data) ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input ...
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Enhanced Serial Communications Interface (ESCI) Module ESCI DATA REGISTER RECEIVE RxD SHIFT REGISTER LINR SCTIE TCIE SCRIE ILIE TE RE RWU SBK WAKEUP CONTROL BUS CLOCK ENHANCED PRESCALER CGMXCLK ÷ -> SCI_CLK = BUSCLK SL ...
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Addr. Register Name Read: ESCI Prescaler Register $0009 (SCPSC) Write: See page 214. Reset: Read: ESCI Arbiter Control $000A Register (SCIACTL) Write: See page 217. Reset: Read: ESCI Arbiter Data $000B Register (SCIADAT) Write: See page 218. Reset: Read: ESCI ...
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Enhanced Serial Communications Interface (ESCI) Module 14.4.2 Transmitter Figure 14-5 shows the structure of the SCI transmitter and the registers are summarized in The baud rate clock source for the ESCI can be selected via the configuration bit, SCIBDSRC. PRE- ...
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To initiate an ESCI transmission: 1. Enable the ESCI by writing the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1). 2. Enable the transmitter by writing the transmitter enable bit (TE) in ...
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Enhanced Serial Communications Interface (ESCI) Module 14.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in ...
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LINR SCP1 SCP0 PRE- ÷ 4 SCALER BKF PDS2 RPF PDS1 CGMXCLK OR PDS0 BUS CLOCK PSSB4 WAKE PSSB3 ILTY PSSB2 PSSB1 PEN PSSB0 PTY CPU INTERRUPT REQUEST ERROR CPU INTERRUPT REQUEST Figure 14-6. ESCI Receiver Block Diagram 14.4.3.1 Character ...
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Enhanced Serial Communications Interface (ESCI) Module 14.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the ...
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If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, ...
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Enhanced Serial Communications Interface (ESCI) Module 14.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data ...