XC68HC912D60CPV8 Freescale Semiconductor, Inc, XC68HC912D60CPV8 Datasheet
XC68HC912D60CPV8
Available stocks
Related parts for XC68HC912D60CPV8
XC68HC912D60CPV8 Summary of contents
Page 1
MC68Hc912D60A MC68HC912D60C MC68HC912D60P Technical Data HC12 Microcontrollers MC68HC912D60A/D Rev. 3.1 08/2005 freescale.com ...
Page 2
...
Page 3
MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data — Rev. 3.1 Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor ...
Page 4
Technical Data 4 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 5
Technical Data — MC68HC912D60A List of Paragraphs Table ...
Page 6
List of Paragraphs Section 17. MSCAN Controller . . . . . . . . . . . . . . . . . . . . 303 Section 18. Analog-to-Digital Converter . . . . . . . . ...
Page 7
Technical Data — MC68HC912D60A 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Technical Data — List of Paragraphs Technical Data — Table of Contents Technical Data — List of ...
Page 8
Table of Contents 3.1 3.2 3.3 3.4 3.5 3.6 4.1 4.2 Section 5. Operating Modes and Resource Mapping 5.1 5.2 5.3 5.4 5.5 5.6 6.1 6.2 6.3 6.4 7.1 Technical Data 8 Section 3. Pinout and Signal Descriptions Contents . ...
Page 9
MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . ...
Page 10
Table of Contents 9.6 9.7 9.8 9.9 10.1 10.2 10.3 10.4 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 Real-Time Interrupt ...
Page 11
MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Introduction . . . . . . . . . . . . . ...
Page 12
Table of Contents 16.2 16.3 16.4 16.5 16.6 16.7 16.8 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 Clock System . . . . . . . . . . . . . . . . . . ...
Page 13
Section 22. Appendix: Changes from MC68HC912D60 22.1 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Functional Description . . . . . . ...
Page 14
Table of Contents 22.2 Section 23. Appendix: Information on MC68HC912D60A 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 Major Changes From Rev 1.0 to Rev 2 ...
Page 15
Technical Data — MC68HC912D60A Figure 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 3-6 5-1 6-1 10-1 STOP Key Wake-up Filter (falling edge trigger) timing 135 11-1 Internal Clock Relationships . . . . . ...
Page 16
List of Figures 14-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . . 227 14-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . ...
Page 17
Multiplexed Expansion Bus Timing Diagram . . . . . . . . . . . . . 421 20-9 SPI Timing Diagram ( ...
Page 18
List of Figures Technical Data 18 MC68HC912D60A — Rev. 3.1 List of Figures Freescale Semiconductor ...
Page 19
Technical Data — MC68HC912D60A Table 1-1 1-2 2-1 2-2 3-1 3-2 3-3 3-4 4-1 5-1 5-2 5-3 5-4 8-1 8-2 8-3 8-4 9-1 9-2 11-1 Summary of STOP Mode Exit Conditions ...
Page 20
List of Tables 14-3 Prescaler Selection 240 15-1 ...
Page 21
Tag Pin Function 403 20-1 ...
Page 22
List of Tables Technical Data 22 MC68HC912D60A — Rev. 3.1 List of Tables Freescale Semiconductor ...
Page 23
Technical Data — MC68HC912D60A 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.2 Introduction The MC68HC912D60A microcontroller unit (MCU 16-bit device available in two package options, 80-pin QFP and 112-pin TQFP. On- chip peripherals include a 16-bit central processing ...
Page 24
General Description 1.3 Devices Covered in this Document The MC68HC912D60C and MC68HC912D60P are devices similar to the MC68HC912D60A, but with different oscillator configurations. Refer to Section 12. Oscillator The generic term MC68HC912D60A is used throughout this document to mean all ...
Page 25
MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Analog-to-digital converters – 8-channels, 10-bit resolution in 112TQFP – 8-channels, 8-bit resolution in 80QFP 1M bit per second, CAN 2 software compatible module – ...
Page 26
General Description • • • • • • Technical Data 26 Serial interfaces – Two asynchronous serial communications interfaces (SCI) – MI-Bus implemented on final devices – Synchronous serial peripheral interface (SPI) LIM (light integration module) – WCR (windowed COP ...
Page 27
Ordering Information 112-Pin TQFP 80-Pin TQFP 112-Pin TQFP 80-Pin TQFP 112-Pin TQFP 80-Pin TQFP * Important: M temperature operation is available only for single chip modes MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Table 1-1. Device Ordering Information Ambient Temperature ...
Page 28
General Description Table 1-2. Development Tools Ordering Information Description MCUez Serial Debug Interface Evaluation board NOTE: SDBUG12 & E Micro Product. It can be obtained from P & E from their web site (http://www.pemicro.com) for approximately $100. ...
Page 29
Block Diagrams 60K byte flash EEPROM Single-wire background BKGD debug module XFC PLL VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Multiplexed Address/Data Bus DDRA PORT A Wide bus Narrow bus Figure 1-1 MC68HC912D60A ...
Page 30
General Description 60K byte flash EEPROM 2K byte RAM 1K byte EEPROM Single-wire background BKGD debug module XFC PLL VDDPLL VSSPLL EXTAL XTAL RESET PE0 XIRQ PE1 IRQ PE2 R/W PE3 LSTRB/TAGLO PE4 ECLK PE5 MODA/IPIPE0 PE6 MODB/IPIPE1/CGMTST PE7 DBE/CAL/ECLK ...
Page 31
Technical Data — MC68HC912D60A 2.1 Contents 2.2 2.3 2.4 2.5 2.6 2.7 2.2 Introduction The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers ( bits) for high-speed extended math ...
Page 32
Central Processing Unit Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8- bit accumulators ...
Page 33
Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag is used only for ...
Page 34
Central Processing Unit Table 2-1. M68HC12 Addressing Mode Summary Addressing Mode Source Format INST Inherent (no externally supplied operands) INST #opr8i Immediate INST #opr16i Direct INST opr8a Extended INST opr16a INST rel8 Relative INST rel16 Indexed INST oprx5,xysp (5-bit offset) ...
Page 35
Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The ...
Page 36
Central Processing Unit 2.7 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only ...
Page 37
Technical Data — MC68HC912D60A 3.1 Contents 3.2 3.3 3.4 3.5 3.6 MC68HC912D60A — Rev. 3.1 Freescale Semiconductor Section 3. Pinout and Signal Descriptions MC68HC912D60A Pin Assignments in 112-pin QFP . . . . . . . . 38 MC68HC912D60A Pin ...
Page 38
Pinout and Signal Descriptions 3.2 MC68HC912D60A Pin Assignments in 112-pin QFP PW2/PP2 1 PW1/PP1 2 PW0/PP0 3 IOC0/PT0 4 IOC1/PT1 5 IOC2/PT2 6 IOC3/PT3 7 PG7 8 KWG6/PG6 9 KWG5/PG5 10 KWG4/PG4 PGUPD ...
Page 39
T L PIN 1 112 IDENT 1 VIEW 0.050 C θ C1 VIEW AB Figure 3-2. 112-pin TQFP Mechanical Dimensions (case no. 987) MC68HC912D60A — Rev. 3.1 Freescale ...
Page 40
Pinout and Signal Descriptions 3.3 MC68HC912D60A Pin Assignments in 80-pin QFP 1 PW2/PP2 2 PW1/PP1 3 PW0/PP0 4 IOC0/PT0 5 IOC1/PT1 6 IOC2/PT2 7 IOC3/PT3 8 KWG4/PG4 IOC4/PT4 12 IOC5/PT5 13 IOC6/PT6 IOC7/PT7 ...
Page 41
0.20 M 0.05 A-B 0. -C- H SEATING PLANE G DATUM -H- PLANE W DETAIL C Figure 3-4. 80-pin QFP Mechanical Dimensions (case no. 841B) MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 42
Pinout and Signal Descriptions 3.4 Power Supply Pins MC68HC912D60A power and ground pins are described below and summarized in All power supply pins must be connected to appropriate supplies account must any pins be left floating. 3.4.1 Internal ...
Page 43
DDPLL SSPLL Provides operating voltage and ground for the Phased-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. NOTE: The VSSPLL pin should always be grounded even if the PLL is ...
Page 44
Pinout and Signal Descriptions Table 3-1. MC68HC912D60A Power and Ground Connection Summary Pin Number Mnemonic 80-pin QFP 10 30, 75 DDX V 29, 74 SSX V 61 DDA V 62 SSA V ...
Page 45
NOTE: When selecting a crystal recommended to use one with the lowest possible frequency in order to minimise EMC emissions. 3.5.1.2 External Oscillator Connections XTAL is the crystal output. The XTAL pin must be left unterminated when an ...
Page 46
Pinout and Signal Descriptions output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the part to ...
Page 47
If neither clock monitor fail nor COP timeout are pending, processing begins by fetching the normal reset vector ($FFFE:FFFF). 3.5.4 Maskable Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. ...
Page 48
Pinout and Signal Descriptions 3.5.6 Mode Select (SMODN, MODA, and MODB) The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1. MODA ...
Page 49
Read/Write (R/W) In all modes this pin can be used as general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit ...
Page 50
Pinout and Signal Descriptions 3.5.13 Inverted ECLK (ECLK) The ECLK pin (PE7) can be used to latch the address for de- multiplexing. It has the same behavior as the ECLK, except is inverted. In expanded modes this pin is used ...
Page 51
Table 3-2. MC68HC912D60A Signal Description Summary Pin Number Pin Name 80-pin 112-pin ADDR[7:0] 23–16 31–24 DATA[7:0] ADDR[15:8] 48–41 64–57 DATA[15:8] DBE 25 36 ECLK 25 36 CAL 25 36 CGMTST 26 37 MODB/ IPIPE1, 26, 27 37, 38 MODA/ IPIPE0 ...
Page 52
Pinout and Signal Descriptions Table 3-2. MC68HC912D60A Signal Description Summary Pin Number Pin Name 80-pin 112-pin SDO/MOSI 68 94 SDI/MISO 67 93 TxD1 66 92 RxD1 65 91 TxD0 64 90 RxD0 63 89 14–11, IOC[7:0] 18–15, 7–4 7–4 84/82/80/78/ ...
Page 53
AD0, port AD1 (available only in 112TQFP), PE[1:0], RxCAN and TxCAN, a data direction register which controls the direction of each pin. After reset all ...
Page 54
Pinout and Signal Descriptions When the PUPB bit in the PUCR register is set, all port B input pins are pulled-up internally by an active pull-up device. This bit has no effect if the port is being used in expanded ...
Page 55
Port G Port G pins are used for key wake-ups that can be used with the pins configured as inputs or outputs. The key wake-ups are triggered with a falling edge signal (KWPG). An interrupt is generated if the ...
Page 56
Pinout and Signal Descriptions configured for output. On reset the DDRH bits are cleared and the corresponding pin is configured for input. Port PHUPD determines what type of resistive load is used for Port H input pins when PUPH bit ...
Page 57
Port AD1 pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to Port AD1 is not available in the 80-pin package. 3.6.8 Port AD0 ...
Page 58
Pinout and Signal Descriptions 3.6.10 Port S Port S is the 8-bit interface to the standard serial interface consisting of the two serial communications interfaces (SCI1 and SCI0) and the serial peripheral interface (SPI) subsystems. Port S pins are available ...
Page 59
Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset Refer to Table ...
Page 60
Pinout and Signal Descriptions 3.6.12 Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced ...
Page 61
Technical Data — MC68HC912D60A 4.1 Contents 4.2 4.2 Register Block The register block can be mapped to any 2K byte boundary within the standard 64K byte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper ...
Page 62
Registers Address Bit 7 6 $0000 PA7 PA6 $0001 PB7 PB6 $0002 DDA7 DDA6 $0003 DDB7 DDB6 $0004 0 0 $0005 0 0 $0006 0 0 $0007 0 0 $0008 PE7 PE6 $0009 DDE7 DDE6 $000A NDBE CGMTE $000B SMODN ...
Page 63
Address Bit 7 6 $0021 0 BKDBE $0022 Bit 15 14 $0023 Bit 7 6 $0024 Bit 15 14 $0025 Bit 7 6 $0026 0 0 $0027 0 0 $0028 PG7 PG6 $0029 PH7 PH6 $002A DDG7 DDG6 $002B DDH7 ...
Page 64
Registers Address Bit 7 6 $004B Bit 7 6 $004C Bit 7 6 $004D Bit 7 6 $004E Bit 7 6 $004F Bit 7 6 $0050 Bit 7 6 $0051 Bit 7 6 $0052 Bit 7 6 $0053 Bit 7 ...
Page 65
Address Bit 7 6 $0072 Bit 15 14 $0073 Bit 7 Bit 6 $0074 Bit 15 14 $0075 Bit 7 Bit 6 $0076 Bit 15 14 $0077 Bit 7 Bit 6 $0078 Bit 15 14 $0079 Bit 7 Bit 6 ...
Page 66
Registers Address Bit 7 6 $0096 Bit 15 14 $0097 Bit 7 6 $0098 Bit 15 14 $0099 Bit 7 6 $009A Bit 15 14 $009B Bit 7 6 $009C Bit 15 14 $009D Bit 7 6 $009E Bit 15 ...
Page 67
Address Bit 7 6 $00BA Bit 15 14 $00BB Bit 7 6 $00BC Bit 15 14 $00BD Bit 7 6 $00BE Bit 15 14 $00BF Bit 7 6 $00C0 BTST BSPL $00C1 SBR7 SBR6 $00C2 LOOPS WOMS $00C3 TIE TCIE ...
Page 68
Registers Address Bit 7 6 $00EF EEDIV7 EEDIV6 EEDIV5 $00F0 NOBDML NOSHB Reserved $00F1 SHPROT 1 $00F2 0 0 $00F3 BULKP 0 $00F4 0 0 $00F5 0 0 $00F6 0 0 $00F7 0 0 $00F8 0 0 $00F9 0 0 ...
Page 69
Address Bit 7 6 $0119 AC7 AC6 $011A AC7 AC6 $011B AC7 AC6 $011C AM7 AM6 $011D AM7 AM6 $011E AM7 AM6 $011F AM7 AM6 $0120– $013C $013D 0 0 $013E PCAN7 PCAN6 $013F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 ...
Page 70
Registers Address Bit 7 6 $01F0 Bit 15 14 $01F1 Bit 7 Bit 6 $01F2 Bit 15 14 $01F3 Bit 7 Bit 6 $01F4 Bit 15 14 $01F5 Bit 7 Bit 6 $01F6 Bit 15 14 $01F7 Bit 7 Bit ...
Page 71
Technical Data — MC68HC912D60A Section 5. Operating Modes and Resource Mapping 5.1 Contents 5.2 5.3 5.4 5.5 5.6 5.2 Introduction Eight possible operating modes determine the operating configuration of the MC68HC912D60A. Each mode has an associated default memory map and ...
Page 72
Operating Modes and Resource Mapping The states of the BKGD, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal. BKGD MODB There are two ...
Page 73
Special Operating Modes There are three special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. In addition, there is a special peripheral mode, in which an external ...
Page 74
Operating Modes and Resource Mapping 5.4 Background Debug Mode Background debug mode (BDM auxiliary operating mode that is used for system development. BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM ...
Page 75
BDM is active. While BDM is active, the user memory from $FF00 to $FFFF is not in the map except through serial BDM commands. Bit 7 6 SMODN MODB RESET RESET ...
Page 76
Operating Modes and Resource Mapping ESTR — E Clock Stretch Enable Determines if the E Clock behaves as a simple free-running clock bus control signal that is active only for external bus cycles. ESTR is always 1 ...
Page 77
EME — Emulate Port E In single-chip mode PORTE and DDRE are always in the map regardless of the state of this bit PORTE and DDRE are in the memory map expanded mode, ...
Page 78
Operating Modes and Resource Mapping data made of the 28K byte FEE28 array mapped from $1000 to $7FFF at reset and of the 32 K byte FEE32 array mapped from $8000 to $FFFF at reset. MAPROM bit in ...
Page 79
MMSWAI — Memory Mapping Interface Stop in Wait Control This bit controls access to the memory mapping interface when in Wait mode. Normal modes: write anytime; special modes: write never. Read anytime Memory mapping interface continues to function ...
Page 80
Operating Modes and Resource Mapping 5.5.3 EEPROM Mapping The MC68HC912D60A has 1K bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After ...
Page 81
Miscellaneous System Control Register Additional mapping and external resource controls are available. To use external resources the part must be operated in one of the expanded modes. Bit 7 6 MAPROM NDRF RESET RESET MISC ...
Page 82
Operating Modes and Resource Mapping RFSTR1, RFSTR0 — Register Following Stretch This two bit field determines the amount of clock stretch on accesses to the 512 byte Register Following Map valid regardless of the state of the NDRF ...
Page 83
Memory Maps The following diagrams illustrate the memory map for each mode of operation immediately after reset. $0000 $0200 $0800 $0C00 $1000 $8000 EXT $FF00 VECTORS VECTORS $FFFF NORMAL EXPANDED SINGLE CHIP Figure 5-1 MC68HC912D60A — Rev. 3.1 Freescale ...
Page 84
Operating Modes and Resource Mapping Technical Data 84 Operating Modes and Resource Mapping MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 85
Technical Data — MC68HC912D60A 6.1 Contents 6.2 6.3 6.4 6.2 Introduction Internally the MC68HC912D60A has full 16-bit data paths, but depending upon the operating mode and control registers, the external multiplexed bus may bits. There are ...
Page 86
Bus Control and Input/Output that was accessed is on the low half of the data bus and the data for address + the high half of the data bus. 6.4 Registers Not all registers are visible in ...
Page 87
Bit 7 6 Single Chip PA7 PA6 RESET: — — Expanded ADDR15/ ADDR14/ & Periph: DATA15 DATA14 Expanded ADDR15/ ADDR14/ narrow DATA15/ DATA14/ DATA7 DATA6 PORTA — Port A Register Bits PA[7:0] are associated respectively with addresses ADDR[15:8], DATA[15:8] and ...
Page 88
Bus Control and Input/Output Bit 7 6 Single Chip PB7 PB6 RESET: — — Expanded ADDR7/ ADDR6/ & Periph: DATA7 DATA6 Expanded ADDR7 ADDR6 narrow PORTB — Port B Register Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0] (except ...
Page 89
BIT 7 6 PE7 PE6 RESET: — — DBE or MODB or Alt. Pin ECLK or IPIPE1 or Function CAL CGMTST PORTE — Port E Register This register is associated with external bus control signals and interrupt inputs, including data ...
Page 90
Bus Control and Input/Output PE[1:0] are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can be read regardless of whether the alternate interrupt functions are enabled. This register is not in the map in peripheral ...
Page 91
In normal expanded modes, the reset vector is located in external memory. The DBE and ECLK are required for de-multiplexing address and data, but LSTRB and R/W are only needed by the system when there are external writable resources. Therefore ...
Page 92
Bus Control and Input/Output PIPOE — Pipe Status Signal Output Enable Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. NECLK — No External E Clock Normal single chip: write once; special single chip: write anytime; all ...
Page 93
RDWE — Read/Write Enable Normal: write once; Special: write anytime EXCEPT the first time. Read anytime. This bit has no effect in single-chip modes. R/W is used for external writes. After reset in normal expanded mode disabled. If ...
Page 94
Bus Control and Input/Output Bit 7 6 PUPH PUPG RESET PUCR — Pull-Up Control Register These bits select pull-up resistors for any pin in the corresponding port that is currently configured as an input. This register is not ...
Page 95
Bit RDPH RESET RDRIV — Reduced Drive of I/O Lines These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time ...
Page 96
Bus Control and Input/Output Technical Data 96 Bus Control and Input/Output MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 97
Technical Data — MC68HC912D60A 7.1 Contents 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.2 Introduction The two Flash EEPROM modules (32-Kbyte and 28-Kbyte) for the MC68HC912D60A serve as electrically erasable and programmable, non-volatile ROM emulation memory. The ...
Page 98
Flash Memory 7.3 Overview The Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two ...
Page 99
Flash EEPROM Registers FEE32LCK/FEE28LCK — Flash EEPROM Lock Control Register Bit RESET LOCK — Lock Register Bit FEE32MCR/FEE28MCR — Flash EEPROM Module Configuration Register Bit RESET This ...
Page 100
Flash Memory FEESWAI — Flash EEPROM Stop in Wait Control HVEN — High-Voltage Enable This bit enables the charge pump to supply high voltages for program and erase operations in the array. HVEN can only be set if either PGM ...
Page 101
Normal Operation The Flash EEPROM allows a byte or aligned word read in one bus cycle. A misaligned word read requires an additional bus cycle. The Flash EEPROM array responds to read operations only. Write operations are ignored. 7.7.3 ...
Page 102
Flash Memory Use this step-by-step procedure to program a row of Flash memory. 1. Set the PGM bit. This configures the memory for program 2. Write to any aligned word Flash address within the row address 3. Wait for a ...
Page 103
Flash Memory 7.9 Erasing the Flash EEPROM The following sequence demonstrates the recommended procedure for erasing any of the Flash EEPROM array. 1. Set the ERAS bit. 2. Write to any valid aligned word address in the Flash array. The ...
Page 104
Flash Memory 7.11 Flash protection bit FPOPEN The FPOPEN bit is located in EEMCR – EEPROM Module Configuration Register, bit 4. FPOPEN – Opens the Flash array for program or erase FPOPEN can be read at anytime. FPOPEN can be ...
Page 105
Technical Data — MC68HC912D60A 8.1 Contents 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.2 Introduction The MC68HC912D60A EEPROM nonvolatile memory is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. ...
Page 106
EEPROM Memory program/erase voltage. Programming voltage is derived from the internal V 8.3 EEPROM Selective Write More Zeros The EEPROM can be programmed such that one or multiple bits are programmed (written to a logic “0” time. However, ...
Page 107
EEPROM Programmer’s Model The EEPROM module consists of two separately addressable sections. The first is an eight-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array ...
Page 108
EEPROM Memory A steady internal self-time clock is required to provide accurate counts to meet EEPROM program/erase requirements. This clock is generated via a programmable 10-bit prescaler register. Automatic program/erase termination is also provided. In ordinary situations, with crystal operating ...
Page 109
EEDIV[9:0] — Prescaler divider Loaded from SHADOW word at reset. Read anytime. Write once in normal modes (SMODN =1) if EELAT = 0 and anytime in special modes (SMODN =0) if EELAT = 0. The prescaler divider is required to ...
Page 110
EEPROM Memory EEMCR — EEPROM Module Configuration Bit 7 6 NOBDML NOSHW (3) RESET: — — 1. Bit 5 has a test function and should not be programmed. 2. The FPOPEN bit is available only on the 1L02H and later ...
Page 111
FPOPEN — Opens the Flash Block for Program or Erase Loaded from SHADOW word at reset. Read anytime. Write anytime in special modes (SMODN=0). Write once ’0’ is allowed in normal mode. EESWAI — EEPROM Stops in Wait Mode Read ...
Page 112
EEPROM Memory EEPROT — EEPROM Block Protect Bit 7 6 SHPROT 1 RESET Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. SHPROT — SHADOW Word Protection BPROT[4:0] — EEPROM ...
Page 113
EEPROG — EEPROM Control Bit 7 6 BULKP 0 RESET BULKP — Bulk Erase Protection Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. AUTO — Automatic shutdown of program/erase operation. EEPGM is cleared ...
Page 114
EEPROM Memory ERASE — Erase Control Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming. Unless BULKP is set, erasure is by byte, aligned word, row or bulk. EELAT — EEPROM Latch Control Read ...
Page 115
Program/Erase Operation A program or erase operation should follow the sequence below if AUTO bit is clear: 1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1 2. Write a byte or an aligned word to ...
Page 116
EEPROM Memory 8.8 Programming EEDIVH and EEDIVL Registers The EEDIVH and EEDIVL registers must be correctly set according to the oscillator frequency before any EEPROM location can be programmed or erased. 8.8.1 Normal mode The EEDIVH and EEDIVL registers are ...
Page 117
Protect the SHADOW word by setting SHPROT bit in EEPROT MC68HC912D60A — Rev. 3.1 Freescale Semiconductor EEPROM location at address $0FC0 and $0FC1. Do not program other bits of the high byte of the SHADOW word (location $0FC0); otherwise ...
Page 118
EEPROM Memory Technical Data 118 EEPROM Memory MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 119
Technical Data — MC68HC912D60A 9.1 Contents 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.2 Introduction CPU12 exceptions include resets and interrupts. Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles ...
Page 120
Resets and Interrupts maskable. The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. The priorities of the non-maskable sources are: 1. POR or RESET pin 2. Clock monitor reset 3. COP ...
Page 121
Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level triggered interrupt. These level triggered interrupt pins should only be released during the appropriate interrupt service routine. Generally the interrupt service routine will ...
Page 122
Resets and Interrupts Vector Address Interrupt Source $FFFE, $FFFF Reset $FFFC, $FFFD Clock monitor fail reset $FFFA, $FFFB COP failure reset $FFF8, $FFF9 Unimplemented instruction trap $FFF6, $FFF7 SWI $FFF4, $FFF5 XIRQ $FFF2, $FFF3 IRQ $FFF0, $FFF1 Real time interrupt ...
Page 123
Interrupt Control and Priority Registers Bit 7 6 IRQE IRQEN RESET INTCR — Interrupt Control Register IRQE — IRQ Select Edge Sensitive Only IRQE can be read anytime and written once in normal modes. In special modes, ...
Page 124
Resets and Interrupts Bit RESET HPRIO — Highest Priority I Interrupt Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime. To give a maskable interrupt source highest priority, write the ...
Page 125
External Reset The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than eight ECLK cycles after an internal device releases reset. When a reset condition is ...
Page 126
Resets and Interrupts 9.7 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states, as follows. 9.7.1 Operating Mode and Memory Map Operating mode and default memory mapping are determined by the ...
Page 127
If the MCU comes out of reset in an expanded mode, port A and port B are used for the address/data bus, and port E pins are normally used to control the external bus (operation of port E pins can ...
Page 128
Resets and Interrupts required to complete the instruction. Some of the longer instructions can be interrupted and will resume normally after servicing the interrupt. When the CPU begins to service an interrupt, the instruction queue is cleared, the return address ...
Page 129
Technical Data — MC68HC912D60A 10.1 Contents 10.2 10.3 10.4 10.2 Introduction The 112QFP MC68HC912D60A offers 16 additional I/O port pins with key wake-up capability them (KWG7 is used for I detect). Only two (KWG4 and KWH4) are ...
Page 130
I/O Ports with Key Wake-up Pull-up/down status is selected by PGUPD and PHUPD input pins: pull- up when PxUPD pin is high, pull-down when PxUPD pin is low. On 80QFP these pins are tied internally so that KWG4 is pull-up ...
Page 131
Bit 7 6 DDG7 DDG6 RESET DDRG — Port G Data Direction Register Data direction register G is associated with port G and designates each pin as an input or output. Read and write anytime Bit 7 6 ...
Page 132
I/O Ports with Key Wake-up Bit 7 6 WI2CE KWIEG6 RESET KWIEG — Key Wake-up Port G Interrupt Enable Register Read and write anytime. WI2CE — Wake-up I When WI2CE is set, PG6 and PG7 operate in wired-OR ...
Page 133
Bit KWIFG6 RESET KWIFG — Key Wake-up Port G Flag Register Each flag, except bit 6, is set by a falling edge on its associated input pin. To clear the flag, write one to the ...
Page 134
I/O Ports with Key Wake-up Bit 7 6 KWIFH7 KWIFH6 RESET KWIFH — Key Wake-up Port H Flag Register Read and write anytime. Each flag is set by a falling edge on its associated input pin. To clear ...
Page 135
The filter is shared by all the KWU pins. Hence any valid triggering level on any KWU pin is seen by the filter. The ...
Page 136
I/O Ports with Key Wake-up Technical Data 136 I/O Ports with Key Wake-up MC68HC912D60A — Rev. 3.1 Freescale Semiconductor ...
Page 137
Technical Data — MC68HC912D60A 11.1 Contents 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 Real-Time Interrupt ...
Page 138
Clock Functions 11.3 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses ...
Page 139
T1CLK T2CLK T3CLK T4CLK INT ECLK PCLK XCLK CANCLK Figure 11-1. Internal Clock Relationships 11.4 Phase-Locked Loop (PLL) The phase-locked loop (PLL) of the MC68HC912D60A is designed for robust operation in an Automotive environment. The allowed PLL crystal or ceramic ...
Page 140
Clock Functions EXTAL REDUCED CONSUMPTION OSCILLATOR XTAL EXTALi SLOW MODE SLWCLK PROGRAMMABLE CLOCK DIVIDER ÷2 SLDV <5:0> EXTALi Figure 11-2. PLL Functional Diagram The PLL may be used to run the MCU from a different time base than the incoming ...
Page 141
Acquisition and Tracking Modes The lock detector compares the frequencies of the VCO feedback clock, DIVCLK, and the final reference clock, REFCLK. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit ...
Page 142
Clock Functions for the base clock. See the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. The following ...
Page 143
Limp-Home and Fast STOP Recovery modes If the crystal frequency is not available due to a crystal failure or a long crystal start-up time, the MCU system clock can be supplied by the VCO at its minimum operating frequency, ...
Page 144
Clock Functions VCO clock at its minimum frequency, f clock, allowing the MCU to continue operating. The MCU is said to be operating in “limp-home” mode with the forced VCO clock as the system clock. PLLON and BCSP (‘bus clock ...
Page 145
All clocks return to their normal settings and Clock Monitor control is returned to the CME & FCME bits. If AUTO and BCSP bits were set before the clock loss (selecting the PLL to provide ...
Page 146
Clock Functions Therefore, if the MCU is powered up without an external clock, limp- home mode is entered provided the MCU normal mode of operation. VDD Power-On Detector EXTALi Clock Monitor Fail Limp-Home 0 --> 4096 13-stage ...
Page 147
During this power up sequence, after the POR pulse falling edge, the VCO supplies the limp-home clock frequency to the 13-stage counter, as the BCSP output is forced high and MCS is forced low. XCLK, BCLK and MCLK are forced ...
Page 148
Clock Functions 11.6.3 STOP Exit and Fast STOP Recovery Stop mode is entered when a STOP instruction is executed. Recovery from STOP depends primarily on the state of the three status bits NOLHM, CME & DLY. The DLY bit controls ...
Page 149
EXTALi Clock Monitor Fail Limp-Home 13-stage counter (Clocked by XCLK) BCSP STOP (DLY = 1) STOP (DLY = 0) SYSCLK Figure 11-5. STOP Exit and Fast STOP Recovery 11.6.4 STOP exit without Limp Home mode, clock monitor disabled (NOLHM=1, CME=0, ...
Page 150
Clock Functions 11.6.5 Executing the STOP instruction without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is ...
Page 151
EXTALi clock cycles can occur on SYSCLK. This may lead to a code runaway. 11.6.7 STOP exit in Limp Home mode without Delay (Fast Stop Recovery) (NOLHM=0, CME=X, DLY=0) Fast STOP recovery refers to any exit from STOP using ...
Page 152
Clock Functions Each time the 13-stage counter reaches a count of 4096 XCLK cycles (every 8192 cycles), a check of the clock monitor status is performed. If the clock monitor indicates the presence of an external clock limp-home mode is ...
Page 153
Pseudo-STOP exit in Limp Home mode with Delay (NOLHM=0, CME=X, DLY=1) When coming out of Pseudo-STOP mode with the NOLHM bit cleared and the DLY bit set, the MCU goes into limp-home mode (regardless of the state of the ...
Page 154
Clock Functions 11.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit is set and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is ...
Page 155
Table 11-1. Summary of STOP Mode Exit Conditions Mode STOP exit without Limp Home mode, clock monitor disabled Executing the STOP instruction without Limp Home mode, clock monitor enabled STOP exit in Limp Home mode with Delay STOP ...
Page 156
Clock Functions 11.6.15 PLL Register Descriptions Bit RESET SYNR — Synthesizer Register Read anytime, write anytime, except when BCSP = 1 (PLL selected as bus clock). If the PLL is on, the count in ...
Page 157
Bit 7 6 LOCKIF LOCK RESET PLLFLG — PLL Flags Read anytime, refer to each bit for write conditions. LOCKIF — PLL Lock Interrupt Flag To clear the flag, write one to this bit in PLLFLG. Cleared in ...
Page 158
Clock Functions Bit 7 6 LOCKIE PLLON RESET: 0 (1) — PLLCR — PLL Control Register 1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low. 2. Cleared when VDDPLL power supply is high. Forced ...
Page 159
ACQ — Not in Acquisition If AUTO = 1 (ACQ is Read Only) If AUTO = 0 PSTP — Pseudo-STOP Enable In Pseudo-STOP mode, the oscillator is still running while the MCU is maintained in STOP mode. This allows for ...
Page 160
Clock Functions Bit BCSP RESET CLKSEL — Clock Generator Clock select Register Read and write anytime. Exceptions are listed below for each bit. BCSP and BCSS bits determine the clock used by the main system ...
Page 161
Bit RESET SLOW — Slow mode Divider Register Read and write anytime. A write to this register changes the SLWCLK frequency with minimum delay (less than one SLWCLK cycle), thus allowing immediate tune- up ...
Page 162
Clock Functions 11.7 System Clock Frequency formulas See Figure SLWCLK = EXTALi / ( 2 x SLOW ) SLWCLK = EXTALi PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1) ECLK = SYSCLK / 2 XCLK ...
Page 163
PHASE PLLCLK LOCK LOOP EXTALi EXTAL REDUCED EXTALi CONSUMPTION OSCILLATOR XTAL EXTALi SLOW MODE SLWCLK CLOCK DIVIDER Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system including ...
Page 164
Clock Functions the transition, the clock select output will be held low and all CPU activity will cease until the transition is complete. The Module Clock Select bit MCS determines the clock used by the ECT module and the baud ...
Page 165
MCLK REGISTER: TMSK2 BITS: PR2, PR1, PR0 TEN 0:0:0 0:0:1 ÷ 2 ÷ 0:1:0 2 0:1:1 ÷ 2 ÷ 1:0:0 2 1:0:1 ÷ 2 ÷ 1:1:0 2 1:1:1 ÷ 2 PORT T7 PAEN MC68HC912D60A — Rev. 3.1 Freescale Semiconductor REGISTER: ...
Page 166
Clock Functions PCLK 5-BIT MODULUS COUNTER (PR0-PR4) ÷ 2 REGISTER: SP0BR BITS: SPR2, SPR1, SPR0 0:0:0 ÷ 2 0:0:1 ÷ 0:1:0 2 ÷ 2 0:1:1 ÷ 2 1:0:0 ÷ 2 1:0:1 ÷ 2 1:1:0 ÷ 2 1:1:1 Figure 11-9. Clock ...
Page 167
In addition, windowed COP operation can be selected. In this mode, writes to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 11.10 Real-Time Interrupt There is a ...
Page 168
Clock Functions 11.12 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2K byte space. Bit 7 6 RTIE RSWAI RESET RTICTL — Real-Time Interrupt Control Register RTIE — Real ...
Page 169
RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select Read and write anytime. Rate select for real-time interrupt. The clock used for this module is the XCLK. RTR2 RTR1 RTR0 Divide X By OFF ...
Page 170
Clock Functions Bit 7 6 CME FCME RESET: 0/1 0 RESET: 0/1 0 COPCTL — COP Control Register CME — Clock Monitor Enable Read and write anytime. If FCME is set, this bit has no meaning nor effect. On reset ...
Page 171
FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset Writes are not allowed in normal modes, anytime in special modes. Read anytime. If DISR is set, this bit has no effect. WCOP — Window COP mode Write once in ...
Page 172
Clock Functions Divide CR2 CR1 CR0 X clock OFF ...
Page 173
Clock Functions Bit 7 6 Bit 7 6 RESET COPRST — Arm/Reset COP Timer Register Always reads $00. Writing $55 to this address is the first step of the COP watchdog sequence. Writing $AA to this address is ...
Page 174
Clock Functions Technical Data 174 MC68HC912D60A — Rev. 3.1 Clock Functions Freescale Semiconductor ...
Page 175
Technical Data — MC68HC912D60A 12.1 Contents 12.2 12.3 12.4 12.5 12.2 Introduction The oscillator implementation on the original 0.65µ (non-suffix) HC12 D- family is a ‘Colpitts Oscillator with Translated Ground’. This design was carried over to the first 0.5µ devices ...
Page 176
Oscillator Level Control circuit to provide a lower power oscillator than traditional Pierce oscillators based on simple inverter circuits. In the following sections, each particular oscillator implementation is described in detail. Refer to the appropriate sections for the mask set ...
Page 177
Figure 12-1. MC68HC912D60A Colpitts Oscillator Architecture 12.3.2 MC68HC912D60A Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting ...
Page 178
Oscillator • • • • • NOTE: An increase in the EXTAL–XTAL parasitic as a result of reducing EXTAL–VSS parasitic is acceptable provided component value is reduced by the appropriate value. • NOTE: EXTAL and XTAL routing resistances are less ...
Page 179
MC68HC912D60C Colpitts Oscillator Specification This section applies to the 2L02H mask set, which refers to the newest set of CGM improvements (to the MC68HC912D60A) with the Colpitts oscillator configuration enabled. The name for these devices is MC68HC912D60C. 12.4.1 MC68HC912D60C ...
Page 180
Oscillator Figure 12-2. MC68HC912D60C Colpitts Oscillator Architecture There are the following primary differences between the previous (’A’) and new (’C’) Colpitts oscillator configurations: • • Technical Data 180 CFLT 2 RFLT RFLT CFLT EXTAL Resonator Hysteresis was added to the ...
Page 181
Clock Buffer Hysteresis The input clock buffer uses an Operational Transconductance Amplifier (labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify the input signal on the EXTAL pin into a full-swing clock for ...
Page 182
Oscillator 12.4.1.2 Internal Parasitic Reduction Any oscillator circuit’s gain margin is reduced when a low AC-impedance (low resistance or high capacitance) is placed in parallel with the resonator. In the Colpitts oscillator configuration, this impedance is dominated by the parasitic ...
Page 183
Input ESD Resistor Path Modification To satisfy the condition of oscillation, the oscillator circuit must not only provide the correct amount of gain but also the correct amount of phase shift. In the Colpitts configuration, the phase shift due ...
Page 184
Oscillator 12.4.2 MC68HC912D60C Oscillator Circuit Specifications 12.4.2.1 Negative Resistance Margin Negative Resistance Margin (NRM figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in ...
Page 185
NRM measurement techniques can also generate misleading results when applied to Automatic Level Control (ALC) style oscillator circuits such as the D60x/Dx128x. Many NRM methods slowly increase series resistance until oscillation stops. ALC-style oscillators reduce the gain of the oscillator ...
Page 186
Oscillator 12.4.2.3 Optimizing Component Values The maximum ESR possible (given a worst-case Gain Margin not the optimum operating point. In some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional ...
Page 187
Important Information For Calculating Component Values Before attempting to apply the information in section Parameters, the following data from the resonator vendor is required: • • • • 12.4.3.1 How to Use This Information The following ...
Page 188
Oscillator 3. Within this range, choose the EXTAL–XTAL capacitance closest 4. If the ideal component is between two valid component values (the 5. Choose the size of the XTAL–VSS capacitance equal to the 6. If the frequency of the crystal ...
Page 189
Table 12-1. MC68HC912D60C EXTAL–XTAL Capacitor Values vs. Maximum ESR, Shunt Maximum ESR vs. EXTAL–XTAL capacitor value, 1MHz resonators 3 1570 Shunt 5 1460 Capacitance (pF) 7 1350 (VDDPLL=VDD) 10 1210 C (pF) 100pF EXTAL-XTAL Maximum ESR vs. EXTAL–XTAL capacitor value, ...
Page 190
Oscillator Maximum ESR vs. EXTAL–XTAL capacitor value, 8MHz resonators 3 Shunt 5 Capacitance (pF) 7 (VDDPLL=VDD Shunt 5 Capacitance (pF) 7 (VDDPLL= (pF) EXTAL-XTAL Maximum ESR vs. EXTAL–XTAL capacitor value, 10MHz resonators 3 Shunt 5 Capacitance ...
Page 191
MC68HC912D60C DC Blocking Capacitor Guidelines Due to the placement of the resonator from EXTAL to VSS and the nature of the microcontroller’s inputs, there will bias voltage of approximately (VDD–2V) across the pins of the resonator. ...
Page 192
Oscillator Figure 12-3. MC68HC912D60C Crystal with DC Blocking Capacitor Technical Data 192 - OTA CFLT + 2 RFLT - ALC + RFLT CFLT RESD EXTAL Resonator 1nF DC-blocking capacitor C DC Oscillator BUF BIAS EN GM XTAL C X-EX C ...
Page 193
MC68HC912D60C Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on ...
Page 194
Oscillator • NOTE: EXTAL and XTAL routing resistances are less important than capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance. 12.5 MC68HC912D60P Pierce Oscillator Specification This section applies to the 3L02H mask set, which refers to ...
Page 195
There are the following primary differences between the previous Colpitts (‘A’) and new Pierce (‘P’) oscillator configurations: • • • MC68HC912D60A — Rev. 3.1 Freescale Semiconductor CFLT 2 RFLT EXTAL Figure 12-4. MC68HC912D60P Pierce Oscillator Architecture Oscillator architecture was changed ...
Page 196
Oscillator • 12.5.1.1 Oscillator Architecture Change from Colpitts to Pierce The primary difference from the ‘A’ to the ‘P’ versions of the MC68HC912D60 is the architecture, or configuration, of the oscillator. The previous version (‘A’) is connected in Colpitts configuration, ...
Page 197
Clock Buffer Hysteresis The input clock buffer uses an Operational Transconductance Amplifier (labeled ‘OTA’ in the figure above) followed by a digital buffer to amplify the input signal on the EXTAL pin into a full-swing clock for use by ...
Page 198
Oscillator 12.5.1.3 Bias Current Process Optimization For proper oscillation, the gain margin of the oscillator must exceed one or the circuit will not oscillate. Process variance in the bias current (which controls the gain of the amplifier) can cause the ...
Page 199
MC68HC912D60P Oscillator Circuit Specifications 12.5.2.1 Negative Resistance Margin Negative Resistance Margin (NRM figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in series ...
Page 200
Oscillator NRM measurement techniques can also generate misleading results when applied to Automatic Level Control (ALC) style oscillator circuits such as the D60x/Dx128x. Many NRM methods slowly increase series resistance until oscillation stops. ALC-style oscillators reduce the gain of the ...