CS493292-CL Cirrus Logic, Inc., CS493292-CL Datasheet
CS493292-CL
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CS493292-CL Summary of contents
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... Memory PLL STC VA AGND DGND[3:1] VD[3:1] This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2002 (All Rights Reserved) TM ® , LOGIC7 , and SRS Circle Surround II See page 85 APPLICATION CORE DECODER FUNCTIONALITY DVD Audio MLP, AC-3, AAC, DTS, MPEG 5 ...
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... IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc ...
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Ground ...................................................................................................................... 32 4.4 Pads ......................................................................................................................... 32 5. CLOCKING ..................................................................................................................... 32 6. CONTROL ...................................................................................................................... 32 6.1 Serial Communication .............................................................................................. 33 6.1.1 SPI Communication ...................................................................................... 33 2 6.1 Communication ...................................................................................... 35 6.1.3 INTREQ Behavior: A Special Case .............................................................. ...
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DESCRIPTIONS ....................................................................................................... 80 13.ORDERING INFORMATION............................................................................................ 85 14.PACKAGE DIMENSIONS ............................................................................................... 85 LIST OF FIGURES Figure 1. RESET Timing ..................................................................................................................... 7 Figure 2. CLKIN with CLKSEL = VSS = PLL Enable .......................................................................... 7 ® Figure 3. Intel Parallel Host Mode Read ...
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Figure 38. Fast Autoboot Sequence Using GFABT Codes ...............................................................60 Figure 39. Performing a Reset ..........................................................................................................62 Figure 40. Non-Paged Memory .........................................................................................................64 Figure 41. Example Contents of a Paged 32 Kilobytes External Memory (Total 256 Kilobytes) .......64 Figure 42. CDB49300-MEMA.0 Daughter Card ...
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CHARACTERISTICS AND SPECIFICATIONS 1.1. Absolute Maximum Ratings (AGND, DGND = 0 V; all voltages with respect Parameter DC power supplies: Input current, any pin except supplies Digital input voltage Storage temperature CAUTION: Operation at or beyond ...
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Switching Characteristics — RESET = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter RESET minimum pulse width low (-CL) RESET minimum pulse width low (-IL) All ...
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Switching Characteristics — Intel = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter Address setup before CS and RD low or CS and WR low Address ...
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A1 A7:0 T ias icdr A1 A7 icdw DS339PP4 idhr T idd ...
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Switching Characteristics — Motorola = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter Address setup before CS and DS low Address hold time after CS and ...
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Figure 5. Motorola ...
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Switching Characteristics — SPI Control Port = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter SCCLK clock frequency CS falling to SCCLK rising Rise time of ...
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DS339PP4 CS49300 Family DSP 13 ...
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Switching Characteristics — I 1.10 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter SCCLK clock frequency Bus free time between transmissions Start-condition hold time (prior to ...
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DS339PP4 CS49300 Family DSP 15 ...
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Switching Characteristics — Digital Audio Input = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter SCLKN1(2) period for both Master and Slave mode SCLKN1(2) duty cycle ...
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...
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Switching Characteristics — CMPDAT, CMPCLK = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter Serial compressed data clock CMPCLK period CMPDAT setup before CMPCLK high CMPDAT ...
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Switching Characteristics — Digital Audio Output = 25 °C; VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic Parameter MCLK period MCLK duty cycle SCLK period for Master or Slave ...
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MCLK (Input) SCLK (Output) MCLK (Output) SCLK (Output Figure 12. Digital Audio Output Data, Input and Output Clock Timing 20 T sdmi ...
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FAMILY OVERVIEW The CS49300 family contains system on a chip solutions for multichannel audio decompression and digital signal processing. The CS49300 family is split into 4 sub-families targeted at the DVD, broadcast and audio/video receiver (AVR), and effects and ...
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PES layer decode for audio/video synchronization and DVD Audio Pack layer support. The CS49300 will support all of the above decoding and PCM processing standards. CS4931X - Broadcast Sub-family. The CS4931X sub-family is targeted at audio decoding ...
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DTS tables on chip. CS49330 - General Purpose, Car Audio Processor, PCM Effects & Multichannel Post- Processing Device. The CS49330 sub-family is targeted at any system that may ...
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TYPICAL CONNECTION DIAGRAMS Six typical connection diagrams have been presented to illustrate using the part with the different communication modes available. They are as follows: 2 ® Figure 13, "I C Control" on page 26 2 ® Figure 14, ...
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Sometimes GPIO[11:0], or some subset thereof, is used when referring to the pins in a general sense. 3.2. Termination Requirements The CS493XX incorporates open drain pins which must be pulled high for proper operation. ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + 1 uF ...
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Supply (+2.5VD) SYSTEM CONTROLLER / OCTAL F/F OCTAL F/F Q[7:0] Q[7:0] A[15:8] D[7:0] D[7:0] A[7:0] D[7:0] DS339PP4 NOTE: A capacitor ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + 1 uF ...
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Supply (+2.5VD) SYSTEM CONTROLLER / OCTAL F/F OCTAL F/F Q[7:0] Q[7:0] A[15:8] D[7:0] D[7:0] A[7:0] D[7:0] DS339PP4 NOTE: A capacitor ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2. ...
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Supply (+2.5VD) NOTE: A capacitor pair (1 uF and 0.1 uF) must be supplied for each power pin. NOTE: +2.5VA is simply +2.5VD after filtering through the ferrite bead. Pin 32 must be referenced to +2.5VA + + 1 ...
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Ground For two layer applications, care should be taken to have sufficient ground between the DSP and parts in which it will be interfacing (DACs, ADCs, DIR, microcontrollers, external memory etc). ...
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Only the subsection describing the communication mode being used needs to be read by the system designer. 6.1. Serial Communication The CS493XX has a serial control port that supports both SPI and communication. The following sections will communication mode in ...
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Once again it is crucial that the serial clock transitions from high to low on the last bit of the last byte before chip select is raised loss of data will occur. The same write routine could ...
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Understanding the role of INTREQ is important for successful communication. INTREQ is guaranteed to remain low (once it has gone low) until the second to last rising edge of SCCLK of the last byte to be transferred out of ...
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CS49300 Family DSP DS339PP4 ...
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After each byte (including the address and each data byte) the host must release the data line and provide a ninth clock for the CS493XX to acknowledge. The CS493XX will drive the data line low during the ninth clock ...
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CS493XX, a stop condition should be issued and the read sequence should be restarted. 5) The data is ready to be clocked out on the SCDIO line at this point. Data clocked out by ...
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The timing diagram in Figure 24, "I2C® Timing" on page 40 shows the relative edges of the control 2 ® lines for read and write. 6.1.3. INTREQ Behavior: A Special Case When communicating with the CS493XX there ...
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CS49300 Family DSP DS339PP4 ...
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D0 (SCCLK N-1), but it can go low at the rising edge of SCCLK for the NACK bit (SCCLK unsolicited message has arrived unsolicited messages arrive, the INTREQ pin will remain ...
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Host Message (HOSTMSG) Register, A[1:0] = 00b 7 6 HOSTMSG7 HOSTMSG6 HOSTMSG5 HOSTMSG7–0 Host data to and from the DSP. A read or write of this register operates handshake bits between the internal DSP and the external host. This register ...
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When the host is downloading code to the CS493XX or configuring the application code, control messages will be written to (and read from) the Host Message register. The Host Control register is used during messaging sessions to determine when the ...
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Byte in Intel Mode Information provided in this section is intended as a functional description of how to write control information to the CS493XX. The system designer must insure that all of the timing constraints of the Intel ...
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The host should now terminate the read cycle by driving the CS and RD pins high. 6.2.2. Motorola Parallel Host Communication Mode The Motorola parallel host communication mode is implemented using the pins given in INTREQ pin is controlled ...
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CS and DS pins high. 6.2.2.2.Reading a Byte in Motorola Mode The flow diagram shown in Figure 27 the sequence of events that define a one-byte read in Motorola mode. The ...
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Host Control Register again. If HINBSY is low, then the host may write a control byte into the Host Message Register. 3) The host knows that the DSP is ready for a new ...
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INTREQ = 0 YES READ_BYTE_*(HOST CONTROL REGISTER) HOUTRDY==1 YES READ_BYTE_*(HOST MESSAGE REGISTER) YES MORE BYTES TO READ? NO WAIT 100 uS READ_BYTE_*(HOST CONTROL REGISTER) HOUTRDY==1 NO FINISHED Figure 29. Typical Parallel Host Mode Control Read Sequence Flow Diagram 48 host ...
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EXTMEM serves as the active low chip select output. Pin Name Pin Description /EMOE * External Memory Output Enable & Address Latch Strobe /EMWR * External Memory Write Strobe /EXTMEM External Memory Select EMAD7 Address and Data Bit 7 EMAD6 ...
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Paging of the external memory is handled entirely by the host controller. The host controller should directly control all address bits outside of the memory space to be used by ...
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EMAD[7:0] CS493XX EXTMEM EMOE EMWR EMAD7:0 Figure 31. External Memory Read (16-bit address) EXTMEM EMOE EMWR EMAD7:0 Figure 32. External Memory Write (16-bit address) DS339PP4 3.3V ...
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BOOT PROCEDURE & RESET In this section the process of booting and downloading to the CS493XX will be covered as well as how to perform a soft reset. Host boot and autoboot and reset are covered in this section. ...
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RESET(LOW) (NOTE 1) WRITE_*(DOWNLOAD_ BOOT, MSG_SIZE) N INTREQ LOW? Y READ_*(MESSAGE) N MESSAGE == BOOTSTART? Y WRITE_*(.LD FILE, DOWNLOAD FILE SIZE) N INTREQ LOW? Y READ_*(MESSAGE) N MESSAGE == BOOT_SUCCESS? Y WRITE_*(BOOT_ SUCCESS_RECEIVED, MSG-SIZE) WAIT 5 MS (NOTE 4) WRITE_*(HW_CONFIG_MSG, ...
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RESET(LOW) (NOTE 1) READ HOSTCTL REGISTER N HOUTRDY LOW? Y READ_*(MESSAGE) N MESSAGE == BOOTSTART? Y WRITE_*(.LD FILE, DOWNLOAD FILE SIZE) READ HOSTCTL REGISTER N HOUTRDY LOW? Y READ_*(MESSAGE) N MESSAGE == BOOT_SUCCESS? Y WRITE_*(BOOT_ SUCCESS_RECEIVED, MSG-SIZE) WAIT 5 MS ...
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CS493XX sends out the boot message BOOT_START (0x01) and the host should proceed to step initialization fails, the CS493XX sends out an INIT_FAILURE boot message byte (0xFD or 0xFE), INVALID_MSG byte (0xFB), or BOOT_ERROR byte (0xFA or ...
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Autoboot Autoboot is a feature available on all DSPs in the CS493XX family which gives the decoder the ability to load application code into itself from an external memory. Because external memory is accessed through the external memory interface, ...
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In autoboot mode, latching the most significant byte would be perfectly valid since the most significant bits are guaranteed to be zeros (the three bytes represent a true 24-bit address). The flow chart given in Figure 36, "Autoboot Sequence" on ...
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RESET(LOW) (NOTE 1) ABOOT(LOW) RESET(HIGH) (NOTE 2) RELEASE ABOOT WAIT 200 MS (NOTE 3) READ_*(VARIABLE) (NOTE 4) N CORRECT VALUE? Y AUTOBOOT COMPLETE WRITE_*(HW_CONFIG_MSG, HW_MSG_SIZE) (NOTE 4) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) (NOTE 4) WRITE_*(KICKSTART, MSG_SIZE) (NOTE 4) 58 WAIT 5 MS Notes: ...
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RESET). Note: This time has been tested using the ac3_493263_13.ld application code release, however other application code releases MAY take longer than 200mS as they have may an increased image size and may take longer ...
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RESET(LOW) (NOTE 1) WRITE_*(DOWNLOAD_ BOOT, MSG_SIZE) N INTREQ LOW? Y WRITE_*(GFABTX.LD FILE, DOWNLOAD FILE SIZE) WAIT 135 MS, 100 MS (NOTE 5) READ_*(VARIABLE) (NOTE 4) N CORRECT VALUE? Y AUTOBOOT COMPLETE WRITE_*(HW_CONFIG_MSG, HW_MSG_SIZE) (NOTE 6) WRITE_*(SW_CONFIG_MSG, SW_MSG_SIZE) ...
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Design Considerations when using GFABT Codes The designer should be aware that the gfabt codes do not lock the PLL, so therefore the actual time in- volved with autobooting is subject to the open loop VCO frequency. The PLL ...
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The host should then send the message SOFT_RESET (0x000001). This will reset the previously downloaded application with all of the hardware configurations in their default states. The application code user’s guide ...
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... Dolby Digital with Pro Logic II 5.1 Channel System Dolby Digital with Enhanced PL II, Dolby Digital/ C.O.S., DTS DTS 5.1 Channel System C.O.S. Basic 6.1 Channel System C.O.S. Enhanced 6.1 Channel System C.O.S. Premium 6.1/7.1 Channel System N/A, No IBA Premium 6.1/7.1 Codes not avail- Channel System able for the with AAC CS493292 Support 63 ...
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D olby D igital with Pro Logic II C ode or 0x0FF FF another Full D ownload C ode Figure 40. Non-Paged Memory external ROM, in order to have access to the single application code stored in the 32 ...
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GPIO pins of the DSP via 2 messaging to the SPI port. 8.8. CDB49300-MEMA.0 The CDB49300-MEMA external memory adapter card designed for CDB4923/CDB4930 REV-A.0 Evaluation Board. The schematic for the ...
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CS49300 Family DSP DS339PP4 ...
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HARDWARE CONFIGURATION After download or soft reset, and before kickstarting the application (please see the Audio Manager in the Application Messaging Section of any Application Code User’s Guide for more information on kickstarting), the host has the option of ...
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It should be noted that in the multichannel modes the SCLK rate must be greater than the number of bits per channel multiplied by the number of channels. In the example SCLK must be ...
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Compressed Data Input Port The compressed data input port, or CDI, can be used for both compressed and PCM data input. Table 14 shows the mnemonic, pin name ...
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During delivery of a block of data the FIFO threshold should not be checked. In other words the FIFO indicators are level sensitive and indicate that a block can be delivered when they are low. They may return high during ...
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Fs is the output sample rate. SCLK is the bit clock used to clock data out on AUDATA0, AUDATA1, AUDATA3. LRCLK is the data framing clock whose frequency is typically ...
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HARDWARE CONFIGURATION After download or soft reset, and before kickstarting the application (please see the Audio Manager in the Application Messaging Section of any application code user’s guide for more information on kickstarting), the host has the option of ...
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C - SCLK Polarity D - FIFO Setup (only valid for parallel modes of data delivery) The following tables show the different values for each parameter as well as the hex message that needs to be sent. When creating the ...
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B Value Data Format 1 PCM - Left Justified 24-bit Compressed - Left Justified 16-bit (Compressed meaning any type of compressed data such as IEC61937- packed AC-3, DTS, MPEG Multichannel, AAC or MP3 elementary stream data from a DVD or ...
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B Value Data Format 8 PCM - Left Justified 24-bit Multichannel PCM (6 Channel) - Left Justified 20-bit (for Post-Processing Codes that can accept 6 channels on one line like THX Surround EX application code) 82 PCM - Left Justified ...
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Output Data Hardware Configuration The naming convention for the DAO configuration is as follows: OUTPUT where the parameters are defined as DAO Mode (Master/Slave for LRCLK and SCLK Data Format ...
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DAO Data Format Of AUDATA0 (or AUDATA0 B Value for Multichannel Modes) 22 Multichannel (2 channel) 20-bit Left Justified (SCLK must be at least 128Fs for this mode) (Configuration of AUDATA3 as S/PDIF (IEC60958) or Digital Audio in ...
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Output Configuration Considerations 1) All PCM output is 24-bit resolution 2) An SCLK frequency of at least 128Fs must be selected for the 20-bit multichannel (6 channel) mode SCLK frequency of at least 128Fs must be selected ...
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Concatenating the messages together gives the following hardware configuration message that should be sent after download or soft reset: WORD# VALUE WORD# 1 0x800210 12 2 0x3FBFC0 13 3 0x800110 14 4 0xC0002C 15 5 0x800217 ...
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PIN DESCRIPTIONS AUDATA3, XMT958 WR,DS,EMWR,GPIO10 RD,R/W,EMOE,GPIO11 A1, SCDIN A0, SCCLK DATA7,EMAD7,GPIO7 DATA6,EMAD6,GPIO6 DATA5,EMAD5,GPIO5 DATA4,EMAD4,GPIO4 DATA3,EMAD3,GPIO3 DATA2,EMAD2,GPIO2 DATA1,EMAD1,GPIO1 DATA0,EMAD0,GPIO0 SCDIO, SCDOUT,PSEL,GPIO9 ABOOT, INTREQ EXTMEM, GPIO8 VA—Analog Positive Supply: Pin 34 Analog positive supply ...
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CLKSEL—DSP Clock Select: Pin 31 This pin selects the clock mode of the CS493XX. When CLKSEL is low, CLKIN is connected to the internal PLL from which all internal clocks are derived. When CLKSEL is high CLKIN is connected to ...
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CS—Host Parallel Chip Select, Host Serial SPI Chip Select: Pin 18 In parallel host mode, this pin serves as the active-low chip-select input signal. In serial host SPI mode, this pin is used as the active-low chip-select input signal. INPUT ...
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MCLK—Audio Master Clock: Pin 44 Bidirectional master audio clock. MCLK can be an output from the CS493XX that provides an oversampled audio-output clock at either 128 Fs, 256 Fs, or 512 Fs. MCLK can be an input at 128 Fs, ...
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SDATAN1—PCM Audio Data Input Number One: Pin 22 Digital-audio data input that can accept from one to six channels of compressed or PCM data. SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been configured. ...
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... CS493253-CL 44-Pin PLCC CS493253-IL 44-Pin PLCC CS493254-CL 44-Pin PLCC CS493254-IL 44-Pin PLCC CS493263-CL 44-Pin PLCC CS493263-IL 44-Pin PLCC CS493264-CL 44-Pin PLCC CS493264-IL 44-Pin PLCC CS493292-CL 44-Pin PLCC CS493302-CL 44-Pin PLCC CS493302-IL 44-Pin PLCC 14. PACKAGE DIMENSIONS 44L PLCC PACKAGE DRAWING DIM MIN A ...
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