LPC47N227-MN Standard Microsystems, LPC47N227-MN Datasheet
LPC47N227-MN
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LPC47N227-MN Summary of contents
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... DMA Options Forceable Write Protect and Disk - Change Controls LPC47N227TQFP for 100 Pin TQFP Package LPC47N227-MN for 100 Pin STQFP Package FEATURES !" Floppy Disk Available on Parallel Port Pins (ACPI Compliant) !" Enhanced Digital Data Separator 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, ...
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... DMA Transfers - 16-Bit Address Qualification - The SMSC LPC47N227 and ACPI 1.0b compliant Super I/O Controller. The LPC47N227 implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 29 GPIO pins. The LPC47N227 incorporates SMSC’ ...
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FEATURES............................................................................................................................................ 1 GENERAL DESCRIPTION .................................................................................................................... 2 PIN CONFIGURATION .......................................................................................................................... 4 DESCRIPTION OF PIN FUNCTIONS .................................................................................................... 5 Buffer Type Description .................................................................................................................... 12 BLOCK DIAGRAM .............................................................................................................................. 13 3.3 VOLT OPERATION / 5 VOLT TOLERANCE................................................................................. 14 Power Functionality ........................................................................................................................... 14 VCC Power....................................................................................................................................... 14 ...
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... PIN CONFIGURATION Note: Pinouts are the same for both the TQFP and STQFP Packages. 1 DRVDEN0 DRVDEN1 2 nMTR0 3 nDSKCHG 4 nDS0 5 GP24 6 7 VSS nDIR 8 nSTEP 9 LPC47N227 nWDATA 10 nWGATE 11 nHDSEL 12 nINDEX 13 nTRK0 14 100 Pin TQFP nWRTPRT 15 nRDATA 16 nIO_PME 17 18 VTR CLOCKI 19 LAD0 20 LAD1 ...
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... Serial IRQ pin used with the PCI_CLK pin to transfer LPC47N227 interrupts to the host. nIO_PME (O12/OD12) This active low Power Management Event signal allows the LPC47N227 to request wakeup. FLOPPY DISK INTERFACE DRVDEN0 (O12/OD12) Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F ...
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TQFP/STQFP PIN # NAME 8 Direction Control 9 Step Pulse 10 Write Data 11 Write Gate 12 Head Select 13 Index 14 Track 0 15 Write Protected 16 Read Disk Data 84 Receive Data 1 85 Transmit Data 1 BUFFER ...
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TQFP/STQFP PIN # NAME 86 Data Set Ready 1 97 Data Set Ready 2 87 Request to Send 1 98 Request to Send 2 88 Clear to Send 1 99 Clear to Send 2 BUFFER TYPE PER 1 SYMBOL FUNCTION ...
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TQFP/STQFP PIN # NAME 89 Data Terminal nDTR1 Ready 1 100 Data Terminal nDTR2 Ready 2 90 Ring nRI1 Indicator 1 (Note 8) 92 Ring nRI2 Indicator 2 (Note 8) 91 Data Carrier nDCD1 Detect 1 94 Data Carrier nDCD2 ...
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TQFP/STQFP PIN # NAME SYMBOL 66 Initiate Output/ nINIT/ FDC Direction nDIR Control (Note 4) 67 Printer Select nSLCTIN/ Input/ FDC Step Pulse nSTEP (Note 4) 68 Port Data 0/ PD0/ FDC Index nINDEX 69 Port Data 1/ PD1/ FDC ...
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TQFP/STQFP PIN # NAME SYMBOL 78 Paper End/ PE/ FDC Write Data nWRDATA 79 Busy/ BUSY/ FDC Motor On 1 nMTR1 80 Acknowledge/ nACK/ FDC Drive Select 1 nDS1 81 Error/ nERROR FDC Head nHDSEL Select 82 Autofeed nALF/ Output/ ...
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TQFP/STQFP PIN # NAME SYMBOL 6, General GP24, 32-39, 40-47 Purpose I/O GP30-GP37 48, GP40-GP47 (Note 9) 54-56, GP10, 57-59 GP15-GP17, GP20-GP22 49 General GP11/ Purpose I/O (System Option) (SYSOPT) (Note 5) (Note 9) 50 General GP12/ Purpose I/O/ System ...
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An external pullup resistor is required to move the base IO address for configuration to 0x04E. Note 6: V must not be greater than 0.5V above V CC Note 7: This pin is output only and is ...
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SMI PME WDT SER_IRQ SERIAL CONFIGURATION IRQ PCI_CLK LAD0 LAD1 LAD2 LPC BUS LAD3 INTERFACE nLFRAME nLDRQ nPCI_RESET nLPCPD nCLKRUN CLOCK GEN nMTR0, nDS0, nDIR, nSTEP, DRVDEN0*, CLOCKI V Vcc Vss TR nWGATE, HDSEL, DRVDEN1*, nWDATA BLOCK DIAGRAM ...
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... Volt Operation / 5 Volt Tolerance The LPC47N227 is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected. The LPC interface pins are 3.3 V only. These signals meet PCI DC specifications for 3.3V signaling. These pins are: !" ...
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... The maximum VCC current, I outputs open (not loaded), and all inputs in a fixed state (i.e 3.3V). Power Management Events (PME/SCI) The LPC47N227 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI) events. The terms PME and SCI are used synonymously ...
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... Note 1: Refer to the configuration register descriptions for setting the base address. Host Processor Interface (LPC) The host processor communicates with the LPC47N227 through a series of read/write registers via the LPC interface. addresses for these registers are shown in Table 1. Register access is accomplished through I/O ...
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... LPC47N227 monitors the bus to determine whether the cycle is intended for it. The use of nLFRAME allows the LPC47N227 to enter a lower power state internally. There is no need for the LPC47N227 to monitor the bus when it is inactive can decouple its state machines and data from the bus, and internally gate its clocks ...
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... The nLFRAME signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0. I/O Read and Write Cycles The LPC47N227 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1 ...
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... If the LPC47N227 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The LPC47N227 will choose to assert 0101 or 0110, but not switch between the two patterns. The data (or wait state SYNC) will immediately follow the 0000 or 1001 value ...
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... LPC47N227, data will still be transferred in the next two nibbles. This data may be invalid, but it will be transferred by the LPC47N227. host was writing data to the LPC47N227, the data had already been transferred. In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. ...
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... The FDC is compatible to the 82077AA using SMSC's proprietary floppy disk controller core. The LPC47N227 supports one floppy disk drive directly through the FDC interface pins and two Table 2 – Status, Data and Control Registers (Shown with base addresses of 3F0 and 370) ...
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PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status ...
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BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 nHEAD SELECT ...
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BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 5 DRIVE SELECT ...
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Digital Output Register (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the DOR ...
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... The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. unaffected by a software reset. TAPE SEL1 (TDR. Note: The LPC47N227 supports one floppy drive directly on the FDC interface pins and two floppy drives on the Parallel Port. Normal Floppy Mode DRIVE DOR VALUE 0 1CH 1 ...
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DB7 DB6 REG 3F3 0 0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DIGITAL OUTPUT REGISTER Bit Note: CR06-Bx = Configuration Register 06, ...
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BIT 5 UNDEFINED Should be written as a logic "0". BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data separator circuits will ...
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DT1 DT0 DRVDEN1 ( DRATE0 1 0 DRATE0 0 1 DRATE0 1 1 DRATE1 Table 10 – Default Precompensation Delays DATA RATE Main Status Register (MSR) Address 3F4 READ ONLY The Main Status Register is a read-only register ...
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BIT 7 RQM Indicates that the host can transfer data if set access is permitted if set Data Register (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are ...
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FIFO THRESHOLD EXAMPLES 1 byte 2 bytes 8 bytes 15 bytes Digital Input Register (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 DSK 0 CHG RESET N/A N/A COND. BIT 0 - ...
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BIT 7 DSKCHG This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the Force Disk Change Register (CR17). See the Configuration section for register description. ...
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PS/2 Model 30 Mode RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values. BIT ...
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Table 13 – Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable 0 MA Missing Address Mark DESCRIPTION The ...
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BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark BIT NO. SYMBOL NAME Write ...
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Pin (Hardware Reset) The nPCI_RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. ...
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Command" condition. Execution Phase All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non- DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each ...
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Data Transfer Termination The FDC supports terminal count explicitly through the TC cycle and implicitly through the underrun/overrun and end-of-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a ...
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SYMBOL NAME DTL Special Sector By setting N to zero (00), DTL may be used to control the number of Size bytes transferred in disk read/write commands. The sector size ( set to 128. If the actual ...
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SYMBOL NAME N Sector Size Code This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. transferred is determined by the DTL parameter. Otherwise the sector size is (2 ...
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SYMBOL NAME WGATE Write Gate Alters timing allow for pre-erase loads in perpendicular drives. Instruction Set PHASE R Command W MT MFM ──────── C ──────── W ──────── H ──────── W ──────── ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R ─────── ST0 ─────── R ─────── PCN ─────── PHASE R Command ─── SRT ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ──── SRT ──── LOCK R 0 EIS EFIFO R RELATIVE SEEK DATA ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 ──────── ...
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PHASE R Command PHASE R Command W ───── Invalid Codes ───── Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was ...
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Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. If the FDC detects a pulse on the nINDEX pin twice ...
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This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 21 describes the effect of the SK bit on the ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST 0 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT 1 0 Less than EOT Equal to EOT 1 Less than EOT Equal to EOT NC: No Change, ...
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The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC is ...
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Table 23 – Verify Command Result Phase Table DTL <= EOT DTL > EOT # Sectors Per Side 0 1 < Sectors Remaining AND <= EOT 0 1 ...
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SYSTEM 34 (DOUBLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 80x 12x 50x 12x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 SYNC 40x 6x 26x ...
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Table 24 – Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Issue Read/Write command. The Seek command does not have a result phase. Therefore highly recommended that the Sense Interrupt Status command is issued after the Seek command to terminate it and to provide verification of the head ...
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The HLT (Head Load Time) defines the time between when the Head Load signal goes high and the read/write operation starts. The values change with the data rate speed selection and are documented in Table 26. The ...
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Defaults to one byte. A "00" selects one byte; "0F" selects 16 bytes. PRETRK - Pre-Compensation Start Track Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" ...
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The Relative Seek command differs from the Seek command in that it steps the head the absolute number of tracks specified in the command instead of making a comparison against an internal register. The Seek command is good for drives ...
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The Gap2 and VCO timing requirements for perpendicular recording type drives are dictated by the design of the read/write head. In the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. ...
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... Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS. SERIAL PORT (UART) The LPC47N227 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start ...
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... Similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47N227. All other system functions operate in their normal manner, including the A1 ...
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Bit 0 This bit enables the Received Data Available Interrupt (and timeout interrupts in the FIFO mode) when set to logic "1". Bit 1 This bit enables the Transmitter Holding Register Empty Interrupt when set to logic "1". Bit ...
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Bit 0 Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs. disables both the XMIT and RCVR FIFOs and clears all bytes from both FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode, data ...
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Bit 0 This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit logic "0", an interrupt is pending and the contents of the IIR may ...
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Table 29 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT 0 LEVEL Highest Second ...
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Address Offset = 3H, DLAB = 0, READ/WRITE Start LSB Data 5-8 bits MSB This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits ...
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Bit 5 Stick Parity bit. When parity is enabled it is used in conjunction with bit 4 to select Mark or Space Parity. When LCR bits 3, 4 and 5 are 1 the Parity bit is transmitted and checked as ...
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This feature allows the processor to verify the transmit and receive data paths of the Serial Port. In the diagnostic mode, the receiver and the transmitter interrupts are fully operational. The MODEM Control Interrupts are also operational but the interrupts' ...
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Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of ...
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Bit 3 Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD input to the chip has changed state. Note: Whenever bit set to a logic "1", a MODEM Status Interrupt is generated. ...
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FIFO drops below its programmed trigger level. B. The IIR receive data available indication also occurs when the FIFO trigger level is reached cleared when the FIFO drops below the ...
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There is no trigger level reached or timeout condition indicated in the FIFO Polled Mode, however, the RCVR and XMIT FIFOs are still fully capable of holding characters. DESIRED DIVISOR USED TO BAUD RATE GENERATE 16X CLOCK 50 2304 75 ...
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Table 31 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 32 – Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 32 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 2 Data Bit 3 Data Bit 4 Enable Enable 0 Receiver Line MODEM Status ...
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FIFO Mode Operation GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO Operation The Tx portion of the UART transmits data through TXD as soon as the CPU ...
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... The LPC47N227 infrared interface provides a two-way wireless communications port using infrared as the transmission medium. Several infrared protocols have been provided in this implementation including IrDA v1.2 (SIR/FIR), ASKIR, and Consumer IR (FIGURE 2). For more information consult the SMSC Infrared Communication Controller (IRCC) specification. The IrDA v1.0 (SIR) and ASKIR formats are driven by the ACE registers found in UART2. The UART2 registers are described in “ ...
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... Mode) to program the data rate, while the other has a second Rx data pin (IRRX3). The LPC47N227 uses Pin 63 for these functions. Pin 63 has IR Mode and IRRX3 as its first and second alternate function, respectively. These functions are selected through CR29 as shown in Table 33. ...
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If the Half Duplex option is chosen there Half Duplex Time-out that constrains IRCC direction mode changes. This time-out starts as each bit is transferred and prevents direction mode changes until the time-out expires. The timer is ...
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This pin will remain low following a VCC POR until serial port 2 is enabled by setting the UART2 power down bit (CR02, bit 7), at which time the pin will reflect the state of the transmit output of ...
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... Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The LPC47N227 also provides a mode for support of the floppy disk controller on the parallel port. The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up ...
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Table 35 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 83 2-9 68- (1) = Compatible Mode (3) = High Speed Mode Note: ...
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If the TIMEOUT_SELECT bit is cleared (‘0’), the TIMEOUT bit is cleared on the trailing edge of the read of the EPP Status Register (default) !" If the TIMEOUT_SELECT bit is set (‘1’), the TIMEOUT bit is cleared on a ...
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BIT 2 nINIT - nINITIATE OUTPUT This bit is output onto the nINIT output without inversion. BIT 3 SLCTIN - PRINTER SELECT INPUT This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects ...
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ADDRESS OFFSET = 06H The EPP Data Port 2 is located at an offset of '06H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP ...
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If it has not already done so, the peripheral should latch the information byte now. b) The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more ...
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EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the I/O write cycle when nWAIT is active low during ...
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Table 36 - EPP Pin Descriptions EPP SIGNAL EPP NAME TYPE nWRITE nWrite O PD<0:7> Address/Data I/O INTR Interrupt I WAIT nWait I DATASTB nData Strobe O RESET nReset O ADDRSTB nAddress O Strobe PE Paper End I SLCT Printer ...
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PError Xflag, Select Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from Microsoft. The bit map of the Extended Parallel Port registers is data ...
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Table 37 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Table 38 - ECP Register Definitions NAME ADDRESS (Note 1) data +000h R/W ecpAFifo +000h R/W dsr +001h R/W dcr +002h R/W cFifo +400h R/W ecpDFifo +400h R/W tFifo +400h R/W cnfgA +400h R cnfgB +401h R/W ecr +402h R/W ...
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Device Status Register (DSR) ADDRESS OFFSET = 01H The Status Port is located at an offset of '01H' from the base address. Bits are not implemented as register bits, during a read of the Printer Status Register ...
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BITS 6 and 7 during a read are a low level, and cannot be written. cFifo (Parallel Port Data FIFO) ADDRESS OFFSET = 400h Mode = 010 Bytes written or DMAed from the system to this FIFO are transmitted by ...
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ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET ...
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This bit shall be set to 1 whenever there are writeIntrThreshold or more bytes free in the FIFO. case dmaEn=0 direction=1: This bit shall be set to 1 whenever there are readIntrThreshold or more valid bytes to be read from ...
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Table 40A - Extended Control Register R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it ...
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Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low Data Compression The ECP port supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in ...
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FIFO. Also, an interrupt is generated when serviceIntr is cleared to 0 whenever there are readIntrThreshold or more bytes in the FIFO. 3. When nErrIntrEn is 0 and nFault transitions from high to low or when nErrIntrEn is set ...
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Programmed I/O Mode or Non-DMA Mode The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O. Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing the FIFO in Test Mode. Programmed I/O transfers ...
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Status Register reads: nBUSY = SLCT = 0, nACK = 1, nERR = 1 The following FDC pins are all in the high impedence state when the PPFDC is actually selected by the drive select ...
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Table 43 – FDC Parallel Port Pins CONNECTOR TQFP/STQFP PIN # CHIP PIN # ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. FDC Power Management Direct ...
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... This makes the behavior of the pins during powerdown very important. The pins of the LPC47N227 can be divided into two major categories: system interface and floppy disk drive interface. The floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part's power supply range ...
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PCI_CLK SER_IRQ FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table ...
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Auto Power Management is enabled by Bit[4] in CR07 . When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown when not being used. The EPP logic is in powerdown under any ...
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... The LPC47N227 supports the serial interrupt to transmit interrupt information to the host system. The serial interrupt scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The PCI_CLK, SER_IRQ and nCLKRUN pins are used for this interface. The Serial IRQ/CLKRUN Enable bit D7 in CR29 activates the serial interrupt interface. ...
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... Slaves must continuously sample the Stop Frames pulse width to determine the next SER_IRQ Cycle’s mode. SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47N227 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-around phase. ...
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SER_IRQ PERIOD The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Management Interrupt ...
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... PME and SMI status and enable registers. The edge is programmable through the polarity bit of the GPIO control register. User Note: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the corresponding IRQ must not be used for any of the devices in the LPC47N227. Otherwise contention may occur. 117 ...
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... The LPC47N227 will not assert nCLKRUN under any conditions if SIRQ_CLKRUN_EN is inactive (“0”). The SIRQ_CLKRUN_EN bit CR29. The LPC47N227 will not assert nCLKRUN already driven low by the central resource; i.e., the PCI CLOCK GENERATOR in FIGURE 3. The LPC47N227 will not assert nCLKRUN unless the line has been deasserted for two successive clocks ...
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... DMA request by a device in LPC47N227. The “assertion” detection logic runs asynchronously to the PCI Clock and regardless of the Serial IRQ mode; i.e., “continuous” or “quiet”. 2 Note : The nCLKRUN signal is ‘1’ for at least two consecutive clocks before LPC47N227 asserts (‘0’) it. MASTER KONA FIGURE 3 – nCLKRUN SYSTEM IMPLEMENTATION EXAMPLE ...
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... Note 1: The signal “ANY IRQ CHANGE/DRQ ASSERTION” is the same as “CHANGE/ASSERTION” in Table 47. Note 2: The LPC47N227 continually monitors the state of nCLKRUN to maintain the PCI Clock until an active “ANY IRQ CHANGE/DRQ ASSERTION” condition has been transferred to the host in a SER_IRQ/DMA cycle. For example, if “ANY IRQ CHANGE/DRQ ASSERTION” is asserted before nCLKRUN is de-asserted (not shown in FIGURE 4), the LPC47N227 must assert nCLKRUN as needed until the SER_IRQ/DMA cycle has completed ...
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... The LPC47N227 provides a set of flexible Input/Output control functions to the system designer through the 29 independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. GPIO Pins The following pins include GPIO functionality as defined in the table below. ...
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Each GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in the Configuration section. The data register for each GPIO port is represented as a bit in one of the 8- bit GPIO DATA ...
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Each GPIO port has an 8-bit control register that controls the behavior of the pin. These registers are defined in the Configuration section of this specification. Each GPIO port may be configured as either an input or an output. If ...
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... WRITE NO EFFECT The LPC47N227 provides 21 GPIOs that can directly generate a PME. See the table in the next section. The GPIO Polarity Registers in the Configuration section select the edge on these GPIO pins that will set the associated status bit in the PME_STS1 – PME_STS3 registers. The default is the low- to-high edge. If the corresponding enable bit in the PME_EN1 – ...
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GPIOs that can directly generate an SMI. See the table in the next section. GPIO PME and SMI Functionality The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 ...
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GPIO PME GP10-GP11 Yes GP12 Yes Yes/nIO_SMI GP13-GP17 Yes GP20-GP22 Yes GP23-GP24 Yes GP30-GP37 Yes GP40-GP47 No Note 1: Since GP12 can be used to generate an SMI and as the nIO_SMI output, do not enable GP12 to generate an ...
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... SYSTEM MANAGEMENT INTERRUPT (SMI) The LPC47N227 implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output consists of the enabled interrupts from Super I/O Device Interrupts (Parallel Port, Serial Port 1 and 2 and FDC) and many of the GPIOs pins ...
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... Status bits are cleared on a write of ‘1’. In the LPC47N227 the nIO_PME pin can be programmed open drain, active low, driver. The LPC47N227 nIO_PME pin is fully isolated from other external devices that might pull the nIO_PME signal low ...
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Runtime Registers Block Summary The runtime registers are located at the address programmed in the Runtime Register Block Base Address configuration register located in CR30. The part performs 16-bit address qualification on the Runtime Register Base Address (bits[11:0] are decoded ...
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... VTR POR DESCRIPTION Bit[0] PME_Status = 0 (default Set when LPC47N227 would normally assert the nIO_PME signal, independent of the state of the PME_En bit. Set when a bit in a PME Wake Status register and its associated enable bit set. Bit[7:1] Reserved PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET. Writing a “ ...
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NAME/DEFAULT REGISTER OFFSET PME_STS2 03 Default = 0x00 (R/W) on VTR POR PME_STS3 04 Default = 0x00 (R/W) on VTR POR DESCRIPTION PME Wake Status Register 2 This register indicates the state of the individual PME wake sources, independent of ...
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... The PME Wake Enable register is not affected by Vcc POR, SOFT RESET or HARD RESET. PME Wake Enable Register 2 This register is used to enable individual LPC47N227 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
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... VTR POR and HARD RESET DESCRIPTION PME Wake Enable Register 3 This register is used to enable individual LPC47N227 PME wake sources onto the nIO_PME wake bus. When the PME Wake Enable register bit for a wake source is active (“1”), if the source asserts a wake event so that the associated status bit is “ ...
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NAME/DEFAULT REGISTER OFFSET SMI_EN1 0A Default = 0x00 (R/W) on VTR POR SMI_EN2 0B Default = 0x00 (R/W) on VTR POR GP1 0C Default = 0x00 R/W on VTR POR GP2 0D Default = 0x00 R/W on VTR POR DESCRIPTION ...
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NAME/DEFAULT REGISTER OFFSET GP3 0E Default = 0x00 R/W on VTR POR GP4 0F Default = 0x00 R/W on VTR POR Note: Reserved bits return 0 on read. DESCRIPTION General Purpose I/O Data Register 3 Bit[0]GP30 Bit[1]GP31 Bit[2]GP32 Bit[3]GP33 Bit[4]GP34 ...
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... CONFIG PORT INDEX PORT DATA PORT 1 Note : The INDEX and DATA ports are active only when the LPC47N227 is in the configuration state. 2 Note : The INDEX PORT is only readable in the configuration state. Configuration State The configuration registers are used to select programmable chip options. The LPC47N227 operates in two possible states: the run state and the configuration state ...
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... To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The LPC47N227 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. Programming Example The following is a configuration register programming example written in Intel 8086 assembly language. ...
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The configuration registers are set to their default values at power up (Table 55) and are RESET as indicated in Table 55 and the register descriptions that follow. Table 55 – Configuration Registers Summary REGISTER HARD 1 INDEX TYPE RESET ...
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REGISTER HARD 1 INDEX TYPE RESET CR27 R/W - CR28 R/W - CR29 R/W - CR2A R/W - CR2B R/W - CR2C R/W - CR2D R/W - CR2E R/W - CR2F R/W - CR30 R/W - CR31 R/W - CR32 ...
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CR00 CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. FDC Power/Valid Configuration Cycle Type: R/W BIT NO. BIT NAME 0-2 Reserved 1 3 FDC Power 4,5,6 Reserved 7 Valid 1 ...
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CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. Type: R/W BIT NO. BIT NAME 0,1 Reserved 2 Parallel Port 1 Power 3 Parallel Port Mode 4 Reserved 5,6 Reserved 7 ...
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CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. Type: R/W BIT NO. BIT NAME 0-2 Reserved 3 UART1 Power 1 Down 4-6 Reserved 7 UART2 Power 1 Down 1 NOTE ...
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CR03 can only be accessed in the configuration state and after the CSR has been initialized to 03H. Type: R/W BIT NO. BIT NAME 0 Reserved 1 Enhanced Floppy Mode 2 2,3 Reserved 4 DRVDEN1 5 MFM 6 IDENT 7 ...
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CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. Type: R/W BIT NO. BIT NAME 1,0 Parallel Port Extended Modes 2,3 Parallel Port FDC 3 4 MIDI MIDI ...
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... Note : In the LPC47N227, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control CR05.1 (Table 62). If the FDC Output Control is active DRVDEN1 will behave as follows if CR03 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03 the DRVDEN1 output pin stays high. If the FDC Output Control is inactive the DRVDEN1 Control will have no affect on the DRVDEN1 output pin ...
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CR06 can only be accessed in the configuration state and after the CSR has been initialized to 06H. CR06 holds the floppy disk drive type IDs for up to four floppy disk drives (see Table 6 – Drive Type ID ...
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Auto Power Management and Boot Drive Select Type: R/W BIT NO. BIT NAME 7 Floppy Disk Enable CR08 Register CR08 is reserved. The default value of this register after power up is 00H. CR09 CR09 can only be accessed in ...
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Type: R/W BIT NO. BIT NAME 0 THR0 1 THR1 2 THR2 3 THR3 4,5 Reserved 6,7 IR Output Mux CR0B CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. CR0B ...
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Type: R/W BIT NO. BIT NAME 0 FDD0 DTR0 1 FDD0 DTR1 2 FDD1 DTR0 3 FDD1 DTR1 4 FDD2 DTR0 5 FDD2 DTR1 6 FDD3 DTR0 7 FDD3 DTR1 Table 68 – Drive Rate Table (Recommended) DRT1 DRT0 0 ...
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... UART 2 Speed CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the LPC47N227 Device ID. The default value of this register after power up is 5AH on VCC POR. CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. ...
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... Test 23 CR12 - CR13 CR12 and CR13 are the LPC47N227 Configuration Ports base address registers (Table 73 and Table 74). These registers are used to relocate the Configuration Ports base address beyond the power-up defaults determined by the SYSOPT pin programming. CR12 contains the Configuration Ports base address bits A[7:0]. CR13 contains the Configuration Ports base address bits A[10:8]. The address bits A[15:11] must be ‘ ...
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Configuration Ports base address. Configuration Ports Base Address Byte 0 (Note) Type: R/W BIT NO. BIT NAME 0 Reserved Note: The Configuration Ports Base ...
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CR14 can only be accessed in the configuration state and after the CSR has been initialized to 14H. CR14 shadows the bits in the write-only FDC run-time DSR register. Type: R BIT NO. BIT NAME 0,1 Data Rate Select 0-1 ...
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CR16 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the bits in the write-only UART2 run-time FCR register. description. CR17 CR17 can only be accessed in the configuration state ...
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CR18 - CR1E registers are reserved. Reserved registers cannot be written and return 0 when read. The default value of these registers after power up is 00H on VCC POR. CR1F CR1F can only be accessed in the configuration state ...
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Type: R/W BIT NO. BIT NAME 0 Reserved 1 Reserved 2 ADR4 3 ADR5 4 ADR6 5 ADR7 6 ADR8 7 ADR9 CR21 CR21 can only be accessed in the configuration state and after the CSR has been initialized to ...
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Writing these bits does not affect the ECP hardware DMA or IRQ channels that are configured in CR26 and CR27. Type: R/W BIT NO. BIT NAME 2:0 ECP DMA Select ECP DMA software Indicator 5:3 ECP IRQ Select 6,7 ...
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CR24 can only be accessed in the configuration state and after the CSR has been initialized to 24H. CR24 is used to select the base address of Serial Port 1 (UART1). locations on 8-byte boundaries from 100H - 3F8H. zero. ...
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CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H. CR26 is used to select the DMA for the FDC (Bits and the Parallel Port (bits 0 - 3). ...
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... CR28 is used to select the IRQ for Serial Port 1 (bits and for Serial Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 90). Any unselected IRQ output (registers CR27 - CR29 tristate. Shared IRQs are not supported in the LPC47N227. Type: R/W BIT NO. ...
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Table 92 – UART Interrupt Operation UART1 UART1 UART1 IRQ OUT2 bit Output State asserted 1 de-asserted asserted 1 asserted 1 de-asserted 1 de-asserted It is the responsibility of the software to ...
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CR2B can only be accessed in the configuration state and after the CSR has been initialized to 2BH. CR2B is used to set the SCE (FIR) base address ADR[10:3]. 224 locations on 8-byte boundaries from 100H - 7F8H. ADR8 to ...
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CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. CR2D is used to set the IR Half Duplex Turnaround Delay Time for the IR port. This value 25.5msec ...
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SCE Address Decoding: address bits A[15:12] must be ‘0000’ to access Runtime Register Block registers. A[3:0] are decoded as XXXXb. Runtime Registers Block Base Address Type: R/W BIT NO. BIT NAME 0 ADR4 1 ADR5 2 ADR6 3 ADR7 4 ...
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CR32 can only be accessed in the configuration state and after the CSR has been initialized to 32H. CR32 is GPIO Polarity Register 1 and is used to select the polarity of GP10-GP17 pins. Type: R/W BIT NO. BIT NAME ...
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CR35 can only be accessed in the configuration state and after the CSR has been initialized to 34H. CR34 is GPIO Polarity Register used to select the polarity of GP20-GP24 and IO_PME pins, and select alternate function ...
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CR36 can only be accessed in the configuration state and after the CSR has been initialized to 36H. CR36 is GPIO Polarity Register 3 and is used to select the polarity of GP30-GP37 pins. Type: R/W BIT NO. BIT NAME ...
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CR38 can only be accessed in the configuration state and after the CSR has been initialized to 38H. CR38 is GPIO Polarity Register 4 and is used to select the polarity of GP40-GP47 pins. Type: R/W BIT NO. BIT NAME ...
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Logical Device Base I/O Address and Range Table 110 – I/O Base Address Configuration Register Description LOGICAL REGISTER DEVICE INDEX FDC 0x20 on 8-byte boundaries Parallel 0x23 Port on 4-byte boundaries (EPP Not supported) on 8-byte boundaries (all modes supported, ...
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LOGICAL REGISTER DEVICE INDEX Runtime 0x30 Register Block on 16-byte boundaries Config. Port 0x12, 0x13 (Note 2) On 2-byte boundaries Note 2: The Configuration Port is at either 0x02E or 0x04E (for SYSOPT=0 or SYSOPT=1) at power up and can ...
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OPERATIONAL DESCRIPTION Maximum Guaranteed Ratings Operating Temperature Range .................................................................................................... 0 Storage Temperature Range .....................................................................................................-55 Lead Temperature Range.......................................................................... Refer to JEDEC Spec. J-STD-020 Positive Voltage on any pin, with respect to Ground ......................................................................... V Negative Voltage on any pin, with respect ...
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PARAMETER SYMBOL IO8 Type Buffer Low Output Level V High Output Level I Input Leakage Current O8 Type Buffer Low Output Level V High Output Level O12 Type Buffer Low Output Level V High Output Level IO12 Type Buffer Low ...
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PARAMETER SYMBOL IOP14 Type Buffer Low Output Level High Output Level Input Leakage Current Backdrive Protect/ChiProtect (All pins excluding LAD[3:0], nLDRQ, nLPCPD, nLFRAME) 5V Tolerant Pins (All pins excluding LAD[3:0], nLDRQ, nLPCPD, nLFRAME) Inputs and Outputs in High Impedance State ...
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TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. SER_IRQ nLAD[3:0] nWDATA nSTROBE nCLKRUN CAPACITANCE NAME TOTAL (pF nLDRQ 50 nDIR 240 nSTEP 240 nDS0-1 240 240 PD[0:7] 240 240 nALF 240 ...
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FIGURE 6 - POWER-UP TIMING NAME DESCRIPTION t1 Vcc Slew from 2. Vcc Slew from 0V to 2.7V ...
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CLOCKI FIGURE 7 - INPUT CLOCK TIMING NAME DESCRIPTION t1 Clock Cycle Time for 14.318MHZ t2 Clock High Time/Low Time for 14.318MHz t1 Clock Cycle Time for 32KHZ t2 Clock High Time/Low Time for 32KHz Clock Rise Time/Fall Time (not ...
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CLK Output Delay Tri-State Output FIGURE 10 – OUTPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 CLK to Signal Valid Delay – Bused Signals t2 Float to Active Delay t3 Active to Float Delay CLK Input FIGURE 11 – ...
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PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 Address Data TAR FIGURE 12 – I/O WRITE Address TAR Sync=0110 FIGURE 13 – I/O READ 178 Sync=0110 ...
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PCI_CLK nLDRQ Start FIGURE 14 – DMA REQUEST ASSERTION THROUGH nLDRQ PCI_CLK nLFRAME nLAD[3:0] Start C+D CHL Size Note: L1=Sync of 0000 FIGURE 15 – DMA WRITE (FIRST BYTE) PCI_CLK nLFRAME nLAD[3:0] Start C+D CHL Size Note: L1=Sync of 0000 ...
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FIGURE 17 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP t4 nSTEP ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Asserted (Note 1) t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWAIT Asserted to PDATA Invalid ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 19 – EPP 1.9 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Deasserted t2 nWAIT Asserted to nWRITE Modified (Notes 1,2) t3 nWAIT Asserted to PDATA Hi-Z (Note ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 Command Deasserted to nWRITE Change t2 Command Deasserted to PDATA Invalid t3 PDATA Valid to Command Asserted t4 nWRITE to Command t5 ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 21 – EPP 1.7 DATA OR ADDRESS READ CYCLE NAME DESCRIPTION t1 Command Asserted to PDATA Valid t2 Command Deasserted to PDATA Hi-Z t3 Command Deasserted to nWAIT Deasserted t1 t2 MIN TYP 0 ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direc- tion using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. ...
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible ...
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PD<0:7> nSTROBE BUSY FIGURE 22 – PARALLEL PORT FIFO TIMING NAME DESCRIPTION t1 PDATA Valid to nSTROBE Active t2 nSTROBE Active Pulse Width t3 PDATA Hold from nSTROBE Inactive (Note 1) t4 nSTROBE Active to BUSY Active t5 BUSY Inactive ...
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PD<7:0> nSTROBE t6 BUSY FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PD<7:0> nACK t4 nALF FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Deasserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted ...
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DATA IRRX n IRRX Pa rame ter t1 Pulse Width at 1 15kba ud t1 Pul se Wid th at 57.6kba ud t1 Pul se Wid th at 38.4kba ud t1 Pul ...
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DAT IRT X n IRT X Parameter t1 Pulse Width at 115kbaud t1 Pulse Widt h at 57.6kbaud t1 Pulse Widt h at 38.4kbaud t1 Pulse Widt h at 19.2kbaud t1 Pulse ...
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DAT IRRX n IRRX IRRX IRRX Pa ramet odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu lated Outp ...
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DAT IRT X n IRT MIRT MIRT X Pa ramet odu lated Out put Bit T ime t2 Off Bit T ime t3 ...
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PCI_CLK SER_IRQ FIGURE 29 – SETUP AND HOLD TIME NAME DESCRIPTION t1 SER_IRQ Setup Time to PCI_CLK Rising t2 SER_IRQ Hold Time to PCI_CLK Rising Data Start TXD1, 2 FIGURE 30 – SERIAL PORT DATA NAME DESCRIPTION t1 Serial Port ...
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... The LPC47N227 is available in two packages: 100 Pin TQFP and 100 Pin STQFP 100 Pin TQFP FIGURE 31 – 100 PIN TQFP PACKAGE OUTLINE MIN NOMINAL 0. 1.35 1.40 D 15.80 16.00 D/2 7.90 8.00 D1 13.90 14.00 E 15.80 16.00 E/2 7.90 8.00 E1 13.90 14. 0.45 0. 1.00 e 0.50 Basic % 0. 0. 0.20 PACKAGE OUTLINE MAX REMARK 1.60 Overall Package Height ~ 1.45 Body Thickness 16 ...
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MIN NOMINAL ccc ~ ~ ccc ~ ~ Notes: 1 Controlling Unit: millimeter 2 Tolerance on the position of the leads is ± 0.04 mm maximum. 3 Package body dimensions D1 and E1 do not include the mold protrusion. Maximum ...
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Pin STQFP FIGURE 32 – 100 PIN STQFP PACKAGE OUTLINE MIN NOMINAL 0. 1.35 1.40 D 13.80 14.00 D/2 6.90 7.00 D1 11.80 12.00 E 13.80 14.00 E/2 6.90 7.00 E1 11.80 12.00 ...
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Notes: 1 Controlling Unit: millimeter 2 Minimum space between protrusion and an adjacent lead is .007 mm. 3 Details of pin 1 identifier are optional but must be located within the zone indicated. 4 Dimension for foot length L measured ...
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... PAGE(S) SECTION/FIGURE/ENTRY 2 Features 4 Pin Configuration 5, 8, Description of Pin Functions 11,12 195, 197 Package Outline LPC47N227 REVISIONS CORRECTION STQFP has been added See italicized text See italicized text Figure 31 and 32. Also see italicized text. 199 DATE REVISED 02/14/00 02/14/00 02/14/00 02/14/00 ...
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... CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. LPC47N227 Rev. 03/29/2000 200 ...