SMC91C94 Standard Microsystems, SMC91C94 Datasheet
SMC91C94
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SMC91C94 Summary of contents
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... Four Direct Driven LEDs for Status/ Diagnostics Software Drivers Uses Certified SMC9000 Drivers Which Operate with Every Major Network Operating System Software Driver Compatible with SMC91C92 and SMC91C100 (100 Mbps) Controllers in ISA Mode Software Driver Utilizes Full Capability of 32 Bit Microprocessor SMC91C94 PRELIMINARY ...
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FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PIN CONFIGURATION AVDD COLN COLP RECN RECP TPERXN TPERXP AVSS AVSS ...
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... To complement this flexible architecture, high all ISA bus interface functions are incorporated in the SMC91C94, as well as a 4608 byte packet RAM and serial EEPROM-based setup. The user can select or modify configuration choices. The SMC91C94 integrates most of the 802.3 functionality, incorporating the MAC layer protocol, the physical layer encoding and decoding functions with the ability to handle the AUI interface ...
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... PCMCIA I/O ignores address lines A4-A15 and relies on the PCMCIA host, decoding for the slot. nROM/nPCMCIA, on SMC91C94, is left open with a pullup for ISA mode. This pin is sampled at the end of RESET. If found low, the SMC91C94 is configured for PCMCIA mode. 5 remove undesired release memory ...
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ISA vs. PCMCIA PIN GROUPS FUNCTION SYSTEM ADDRESS BUS SYSTEM DATA BUS SYSTEM CONTROL BUS SERIAL EEPROM CRYSTAL OSC. POWER GROUND 10BASE-T interface ISA PCMCIA A0-9 A0-9 A10 nFWE A11 nFCS A12-14 A15 A15 A16-18 A19 nCE1 AEN nREG D0-15 ...
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... TYPE DESCRIPTION I/O4 with This pin is sampled at the end of RESET. pullup W hen sampled low, the SMC91C94 is configured for PCMCIA operation and all pin definitions correspond to the PCMCIA mode. For ISA operation, this pin is left open and is used as a ROM chip select output. It turns active when MEMR* is low and the address bus contains a valid ROM address ...
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... ISA - Output - Optionally used by the pullup SMC91C94 to extend host cycles PCMCIA - Output - Optionally used by the SMC91C94 to extend host cycles I/O24 Bidirectional - 16 bit data bus to access the SMC91C94 internal registers. The data bus has weak internal pullups. Supports direct connection to the system bus without external buffering 8 ...
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PIN NUMBER NAME SYMBOL QFP TQFP 67 65 Reset RESET 27 25 Address BALE/nWE Latch 19 17 Interrupt INTR0/ nIREQ 20 18 INTR1/ nINPACK 22,23 20,21 Interrupt INTR2-3 BUFFER TYPE DESCRIPTION IS with Input - Active high Reset. This input ...
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... AEN is low and A4-A15 decode to the SMC91C94 address programmed into the high byte of the Base Address Register PCMCIA - Active low output asserted whenever the SMC91C94 bit mode, COR0 bit is high, and REG* is low IS with Input - Active low read strobe to access pullup ...
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... EEPROM to be read or written by the SMC91C94. Internally pulled up. Must be connected to ground if no serial EEPROM is used I with pullup Input - When low the SMC91C94 is configured for 16 bit bus operation. If left open the SMC91C94 works in 8 bit bus mode. 16 bit configuration can also be programmed ...
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... EXTERNAL ENDEC - Transmit clock input from external ENDEC. Analog A 22kohm 1% resistor should be Input connected between this pin and analog ground I with pullup W hen tied low, the SMC91C94 is configured for EXTERNAL ENDEC. W hen tied high or left open, the SMC91C94 uses encoder/decoder 12 its ...
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PIN NUMBER NAME SYMBOL QFP TQFP 13,21 11,19 40,50 48,59 61,100 98,138 73,81 71,79 Analog AVDD 91 89 Power 2,8 100,6 Ground 18,24 18,22 31,566 29,54 6,94 64,92 80,88 78,86 Analog AGND 89 87 Ground O4 Output buffer with 2mA ...
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A0 8 BIT MODE 0 ((nEN16=1) (16BIT=0 BIT MODE 0 0 otherwise BIT MODE 0 1 ((IOis8= (nEN16=1).(16BIT=0)) 16 BIT MODE 0 0 otherwise 16BIT: CONFIGURATION REGISTER bit 7 ...
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FIGURE 1 - SYSTEM DIAGRAM FOR ISA BUS WITH BOOT PROM 15 ...
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... FIGURE 2 - SMC91C94 INTERNAL BLOCK DIAGRAM 16 ...
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... SMC91C94 PCMCIA 10BASE-T/AUI SCHEMATIC TO BE SCANNED IN HERE 17 ...
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... SMC91C94 ISA 10BASE-T/COAX SCHEMATIC TO BE SCANNED IN HERE 18 ...
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... Both interfaces are 16 bits wide. The control path provides a set of registers used to configure and control the block. These registers are accessible by the CPU through the SMC91C94 I/O space. The data path is of sequential access nature and typically works in one direction at any given time. ...
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... The SMC91C94 provides a 16-bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. memory is managed by the MMU. Byte and word accesses to the RAM are supported. If the system to SRAM bandwidth is insufficient the SMC91C94 will automatically use its IOCHRDY line for flow control ...
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FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA 21 ...
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FIGURE 5 - TRANSMIT QUEUES AND MAPPING 22 ...
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FIGURE 6 - RECEIVE QUEUE AND MAPPING 23 ...
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... FIGURE 8 - LOGICAL ADDRESS GENERATION AND RELEVANT REGISTERS FIGURE 7 - SMC91C94 INTERNAL BLOCK DIAGRAM WITH DATA PATH 24 ...
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25 ...
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PACKET FORMAT IN BUFFER MEMORY The packet format in memory is similar for the TRANSMIT and RECEIVE areas. The first word is reserved for the status word, the next word FIGURE 9 - DATA PACKET FORMAT STATUS WORD Written by ...
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... The SMC91C94 does not insert its own source address. On receive, all bytes are provided by the CSMA side. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the SMC91C94 treated transparently as data for both transmit and receive operations. by ...
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RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory not available as a register. ALGN BROD HIGH BYTE ERR CAST LOW BYTE 5 ALGNERR Frame had alignment error. BRODCAST Receive ...
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29 ...
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... This register is used to enable the PCMCIA card, allow programming of the external attribute memory, and to generate soft reset. SRESET 0 SRESET - This bit, when set will reset the SMC91C94 valid in PCMCIA mode only. The bit does not sample the ISA/PCMCIA mode. The bit is cleared writing it low hardware reset. It does not preserve any register. It resembles a hardware reset, including the PWRDWN gating ...
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... NAME 8002 CONFIGURATION/STATUS REGISTER 0 0 IOis8 - This bit when set, indicates to the SMC91C94 that the host is limited to 8 bit interface. In PCMCIA mode the SMC91C94 will operate in 8 bit mode whenever ((IOis8 (nEN16 = 1) . (16BIT = 0)). Otherwise the SMC91C94 operates in 16 bit mode. TYPE ...
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... X X two eight bit registers, in that case the offset of each one is independently specified. Regardless of the functional description, when the SMC91C94 bit mode, all registers can be accessed as words or bytes. The default bit values upon hard reset are highlighted below each register. 32 ...
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Table 3 - Internal I/O Space Mapping BANK0 BANK1 0 TCR CONFIG 2 EPH STATUS BASE 4 RCR IA0-1 6 COUNTER IA2-3 8 MIR IA4-5 A MCR GENERAL PURPOSE C RESERVED (0) CONTROL E BANK SELECT BANK SELECT BANK2 BANK3 ...
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... SMC91C94. BS2 TYPE READ/WRITE The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2. The SMC91C94 implements only 4 banks, therefore accesses to non-existing banks (BS2=1) are ignored. presently in use. BS1 BS0 ...
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... This bit is set and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the FORCOL bit is set, the SMC91C94 will transmit a preamble pattern the next time a carrier is seen on the line packet is queued, a preamble and SFD will be transmitted ...
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... TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the SMC91C94 will complete the current transmission before stopping. When stopping due to an error, this bit is automatically cleared. LOOPS AT X EPH Block 1 ENDEC 1 Cable 1 10BASE-T Driver ...
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I/O SPACE - BANK0 OFFSET NAME 2 EPH STATUS REGISTER This register stores the status of the last transmitted frame. This register value, upon individual transmit packet completion, is stored as the first word in the memory area allocated to ...
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FORCOL in TCR was set the CPU. When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting TXENA in TCR. TX_DEFR - Transmit Deferred. When set, carrier ...
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... SOFT_RST - Software activated Reset. Active high. Valid for ISA and PCMCIA. Initiated by writing this bit high and terminated by writing the bit low. SMC91C94 configuration is not preserved, except for Configuration, Base, IA0-5, COR, and CSR Registers. EEPROM is not reloaded after software reset. ...
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I/O SPACE - BANK0 OFFSET 6 COUNTER REGISTER Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared when reading the register and do no wrap around beyond 15. HIGH NUMBER ...
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... I/O SPACE - BANK0 OFFSET 8 MEMORY INFORMATION REGISTER For software compatibility with other SMC9000 parts all memory-related information is represented in 256 x M byte units, where the multiplier M is determined by the MCR upper byte. M equals 1 for the SMC91C94. HIGH FREE MEMORY AVAILABLE (in bytes x 256 x M) BYTE 0 ...
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I/O SPACE - BANK0 OFFSET NAME A MEMORY CONFIGURATION REGISTER HIGH BYTE 0 0 LOW MEMORY RESERVED FOR TRANSMIT (in bytes x 256 x M) BYTE 0 0 MEMORY RESERVED Programming this value allows the host CPU to reserve memory ...
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... When low the link test functions are enabled. If the link status indicates FAIL, the EPHSR LINK_OK bit will be low, while transmit packets enqueued will be processed by the SMC91C94, transmit data will not be sent out to the cable. INT SEL1-0 - Used to select one out of four interrupt pins ...
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INTERRUPT INT SEL1 INT SEL0 PIN USED 0 0 INTR0 0 1 INTR1 1 0 INTR2 1 1 INTR3 44 ...
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... ISA mode against the I/O address on the bus to determine the IOBASE for SMC91C94 registers. The 64k I/O space is fully decoded by the SMC91C94 down location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros. ROM SIZE - Determines the ROM decode area in ...
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A15 A14 A13 ...
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I/O SPACE - BANK1 OFFSET 4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The registers can be modified by the software driver, but a ...
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... EEPROM, that is normally protected from accidental Store operations. This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of the SMC91C94. 48 SYMBOL GPR 0 0 ...
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... PWRDN - Active high bit used to enter power down mode. Cleared by a write to any register in the SMC91C94 I/O space or by hardware reset. AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case ...
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... During this time attempted read/write operations, other than polling the EEPROM status, will NOT have any effect on the internal registers. The CPU can resume accesses to the SMC91C94 after both bits are low. A worst case RELOAD operation initiated by RESET or by software takes less than 750usec ...
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I/O SPACE - BANK2 OFFSET 0 MMU COMMAND REGISTER This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three command bits determine the command issued as described below: HIGH ...
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RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted frames, after reading their completion status. Can be ...
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I/O SPACE - BANK2 OFFSET 2 PACKET NUMBER REGISTER PACKET NUMBER AT TX AREA The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number I/O ...
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I/O SPACE - BANK2 OFFSET 4 FIFO PORTS REGISTER This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from ...
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I/O SPACE - BANK2 OFFSET 6 POINTER REGISTER HIGH AUTO RCV READ BYTE INCR LOW BYTE 0 0 POINTER REGISTER The value of this register determines the address to be accessed within the transmit or receive areas. It ...
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... This register is mapped into two uni-directional FIFOs that allow moving words to and from the SMC91C94 regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory, and is pre-fetched from memory into the read FIFO. If byte accesses are used, the ...
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I/O SPACE - BANK2 OFFSET C INTERRUPT STATUS REGISTER ERCV INT EPH INT OFFSET C INTERRUPT ACKNOWLEDGE REGISTER ERCV INT OFFSET D INTERRUPT MASK REGISTER ERCV INT EPH INT This register can be read ...
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Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The possible sources are: LINK_OK transition. CTR_ROL - Statistics counter roll over. TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. ...
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FIGURE 11 - INTERRUPT STRUCTURE 59 ...
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I/O SPACE - BANK 3 OFFSET 0 THROUGH 7 MULTICAST TABLE LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 HIGH BYTE 0 0 LOW BYTE 0 0 NAME ...
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HIGH BYTE The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of the CRC of the destination addresses. determine the register to be used ...
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I/O SPACE - BANK3 OFFSET 8 MANAGEMENT INTERFACE This register contains status bits and control bits for management of different transceivers modules. Some of the pins are shared with the serial EEPROM interface. Management is software controlled, and does not ...
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... CHIP BYTE 0 1 CHIP - Chip ID. Can be used by software drivers to identify the device used. CHIP ID VALUE REV - Revision ID. Incremented for each revision of a given device. NAME TYPE READ ONLY DEVICE 3 SMC91C90/91C92 4 SMC91C94 5 SMC91C95 7 SMC91C100 63 SYMBOL REV 1 1 REV 0 0 ...
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I/O SPACE - BANK3 OFFSET C EARLY RCV REGISTER HIGH BYTE 0 0 LOW RCV BYTE DISCRD 0 0 RCV DISCRD - Set to discard a packet being received. This bit can be used in conjuntion with ERCV THRESHOLD and ...
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... Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a block move operation. Multiple upper layer support - The SMC91C94 memory facilitates interfacing to multiple upper layer protocols because of the receive packet processing flexibility. A receive lookahead ...
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S/W DRIVER 1 ISSUE ALLOCATE MEMORY FOR BYTES - the MMU attempts to allocate N bytes of RAM. 2 WAIT FOR SUCCESSFUL COMPLETION CODE - Poll until the ALLOC INT bit is set or enable its mask ...
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TYPICAL FLOW OF EVENTS FOR RECEIVE S/W DRIVER 1 ENABLE RECEPTION - By setting the RXEN bit SERVICE INTERRUPT - Read the Interrupt Status Register and determine if RCV INT is set. The next receive packet ...
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FIGURE 12 - INTERRUPT SERVICE ROUTINE 68 ...
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FIGURE INTR 69 ...
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FIGURE INTR 70 ...
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FIGURE 15 - TXEMPTY INTR (Assumes Auto Release Option Selected) 71 ...
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FIGURE 16 - DRIVER SEND AND ALLOCATE ROUTINES 72 ...
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... If the value is kept at zero, memory allocation is handled on first-come first-served basis for the entire memory capacity. Note that with the memory management built into the SMC91C94, the CPU can dynamically program this parameter. For instance, when the driver does not need ...
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... Packet Number Register. Therefore restoring the PNR is also required from interrupt service routines. POWER DOWN The SMC91C94 can enter power down mode by means of the PWRDWN pin (pin 68) or the PWRDN bit (Control Register, bit 13). The power down current is 8 mA. When in power ...
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75 ...
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... PIN PWRDN PIN PWRDN BIT 0 Normal external ENDEC operation 0 Normal internal ENDEC operation 0 Powerdown - Normal mode restored by PWRDWN pin going low 1 Powerdown - Bit is cleared by a write access to any SMC91C94 register or by hardware reset 76 ...
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FIGURE 17 - INTERRUPT GENERATION FOR TRANSMIT; RECEIVE, MMU 77 ...
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FUNCTIONAL DESCRIPTION OF THE BLOCKS MEMORY MANAGEMENT UNIT The MMU interfaces the on-chip RAM on one side and the arbiter on the other for address and data flow purposes. For allocation and de- allocation, it interfaces the arbiter only. The ...
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... The bus interface handles the data, address and control interfaces as a superset of the ISA and PCMCIA specifications and allows bit adapters to be designed with the SMC91C94 with no glue to interface the ISA or PCMCIA bus. The functions done in this block are address ...
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... For example ISA system the cycle time bit transfer will be at least 2 clocks for the I/O access to the SMC91C94 + one clock for the memory cycle clocks. In absolute time it means 375ns for a 8MHz bus, and 240ns for a 12.5 MHz bus. The cycle time will not increase when ...
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... The width of each FIFO is 5 bits per packet number. The depth of each FIFO equals the number of packets the SMC91C94 can handle (18). The guideline is software transparency; the software driver should not be aware of different devices or FIFO depths ...
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FIGURE 18 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS 82 ...
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CSMA BLOCK The CSMA/CD block is first interfaced via its control registers in order to define its operational configuration. From then on, the DMA interface between the CSMA/CD block and memory is used to transfer data to and from its ...
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... CSMA/CD block. A packet will be received if the destination address is broadcast addressed to the individual address of the SMC91C94 multicast address and ALMUL bit is set multicast address matching one of the multicast table entries. If the PRMS bit is set, all packets are received. ...
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... Link_loss_timer Link_test_min_timer Link_count Link_test_max_timer The state of the link is reflected in the EPHSR. AUI The SMC91C94 also provides a standard 6 wire AUI interface to a coax transceiver. PHYSICAL INTERFACE The internal physical interface (PHY) consists of an encoder/decoder (ENDEC) and an internal 10BASE-T transceiver. ...
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Receive Functions Receive Drivers Differential signals received off the twisted-pair network or AUI cable are directed to the internal clock recovery circuit prior to being decoded for the MAC. Manchester Decoder and Clock Recovery The PHY performs timing recovery and ...
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Reverse Polarity Function In the 10BASE-T mode, the PHY monitors for receiver polarity reversal due to crossed wires and corrects by reversing the signal internally. Collision Detection Function In the 10BASE-T mode, a collision state is indicated when there are ...
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... IOS jumpers. In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can be written using the SMC91C94. One of the IOS combination is associated with a fixed default value for the key parameters (I/O BASE, ...
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... When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the SMC91C94 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads. ...
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FIGURE SERIAL EEPROM MAP 90 ...
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For example odd pointer value is loaded, first a byte is pre-fetched into the FIFO, and immediately a full word is pre-fetched completing three bytes into the FIFO. If the CPU reads a word, one byte will be ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers except pins with pullups/pulldowns) Low Input Leakage High Input Leakage I IP Type Buffers Input Current ID Type Buffers Input Current I I/O4 Type Buffer Low Output Level V High Output ...
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PARAMETER SYMBOL OD16 Type Buffer Low Output Level Output Leakage OD162 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby I CAPACITANCE ...
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PARAMETER Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range Transmitter Output: Voltage Source Resistance Transmitter Output DC Offset Transmitter Backswing Voltage to Idle Differential Input Voltage Receiver Threshold Voltage Receiver Squelch Receiver Common Mode Range $ $ Transmitter Output ...
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W $ $ YDOLG W Q5(* W Q&( W Q2( ' YDOLG 3DUDPHWHU FIGURE 20 - CARD CONFIGURATION REGISTERS-READ/WRITE-PCMCIA MODE (A15=1) TIMING DIAGRAMS W W YDOLG W W W PLQ W\S 96 W YDOLG PD[ XQLWV ...
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PLQ FIGURE 21 - ISA CONSECUTIVE READ CYCLES 97 W\S PD[ XQLWV ...
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FIGURE 22 - PCMCIA CONSECUTIVE READ CYCLES 98 PLQ W\S PD[ XQLWV ...
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FIGURE 23 - ISA CONSECUTIVE WRITE CYCLES 99 PLQ W\S PD[ XQLWV ...
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W $ $ YDOLG W Q5(* W Q&(Q&( W Q,2:5 YDOLG ' 3DUDPHWHU FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES W W W W W PLQ W\S 100 PD[ XQLWV ...
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FIGURE 25 - ISA CONSECUTIVE READ AND WRITE CYCLES 101 PLQ W\S PD[ XQLWV ...
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FIGURE 26 - DATA REGISTER SPECIAL READ ACCESS 102 PLQ W\S PD[ XQLWV ...
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W 3DUDPHWHU PLQ W\S FIGURE 27 - DATA REGISTER SPECIAL WRITE ACCESS 103 PD[ XQLWV ...
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PLQ 3DUDPHWHU PLQ FIGURE 29 - EXTERNAL ROM READ ACCESS 104 W\S PD[ XQLWV W\S PD[ XQLWV ...
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FIGURE 30 - ISA REGISTER ACCESS WHEN USING BALE 105 PLQ W\S PD[ XQLWV ...
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FIGURE 31 - EXTERNAL ROM READ ACCESS USING BALE 106 PLQ W\S PD[ XQLWV ...
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PLQ FIGURE 32 - EEPROM READ 107 W\S PD[ XQLWV ...
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PLQ FIGURE 33 - EEPROM WRITE 108 W\S PD[ XQLWV ...
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YDOLG Q5(* Q&( W W W Q)&6 Q:( W Q):( Q2( 3DUDPHWHU W Q:(WRQ):('HOD\ W $GGUHVVQ5(*Q&('HOD\WRQ)&6 FIGURE 34 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) YDOLG W W W W W W W PLQ W\S PD ...
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FIGURE 36 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BY FALLING RXCLK) 110 PLQ W\S PD[ XQLWV PLQ W\S PD[ XQLWV ...
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FIGURE 37 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND AUI) PLQ W\S PD[ 111 XQLWV ...
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FIGURE 38 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T) PLQ W\S PD[ 112 XQLWV ...
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FIGURE 39 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) PLQ W\S PD[ 113 XQLWV ...
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FIGURE 40 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T) PLQ W\S PD[ 114 XQLWV ...
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PLQ FIGURE 41 - COLLISION TIMING (AUI) 115 W\S PD[ XQLWV ...
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PLQ 3DUDPHWHU PLQ FIGURE 43 - MEMORY WRITE TIMING 116 W\S PD[ XQLWV W\S PD[ XQLWV ...
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FIGURE 44 - 100 PIN QFP 117 ...
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FIGURE 45 - 100 PIN TQFP 118 ...
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... SMC91C94 ERRATA SHEET PAGE SECTION/FIGURE/ENTRY 1 Software Drivers and following text 4 General Description 4 Overview CORRECTION Changed from "Software Compatibility" See Italicized Text See Italicized Text See Italicized Text 119 DATE REVISED 04/27/95 04/27/95 04/27/95 ...