HD6417708STF60 HITACHI, HD6417708STF60 Datasheet
HD6417708STF60
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HD6417708STF60 Summary of contents
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... SH7708 Series SH7708, SH7708S, SH7708R ADE-602-105E Rev.6.0 5/5/99 Hitachi, Ltd. Hardware Manual ...
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... Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...
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... DRAM, DRAM, and pseudo-SRAM without the need for glue logic. This hardware manual describes the hardware of the SH7708 Series. Details of instructions can be found in the programming manual. Related Manuals SH7708Series instructions SH-3/SH-3E/SH3-DSP Programming Manual Please consult your Hitachi sales representative for details of development environment system. Preface ...
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Section 1 Overview and Pin Functions............................................... 1 1.1 SH7708 Series Features ........................................................................................1 1.2 Block Diagram ....................................................................................................6 1.3 Pin Description ...................................................................................................7 1.3.1 Pin Arrangement ......................................................................................7 1.3.2 SH7708 Series Pin Functions.....................................................................8 Section 2 CPU .......................................................................... 13 2.1 Register Configuration..........................................................................................13 2.1.1 Privileged Mode ...
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MMU Functions .................................................................................................66 3.4.1 MMU Hardware Management.....................................................................66 3.4.2 MMU Software Management .....................................................................66 3.4.3 MMU Instruction (LDLTB) ....................................................................... 67 3.4.4 Avoiding Synonym Problems ....................................................................68 3.5 MMU Exceptions................................................................................................ 70 3.5.1 TLB Miss Exception ................................................................................70 3.5.2 TLB Protection Violation Exception............................................................71 3.5.3 TLB ...
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Cache Structure........................................................................................97 5.1.3 Register Configuration ..............................................................................99 5.2 Register Description .............................................................................................99 5.2.1 Cache Control Register (CCR) ...................................................................99 5.3 Cache Operation ..................................................................................................100 5.3.1 Searching the Cache..................................................................................100 5.3.2 Read Access ............................................................................................102 5.3.3 Write Access ...........................................................................................102 5.3.4 Write-Back Buffer.....................................................................................102 5.3.5 Coherency of Cache ...
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UBC Register Functions .......................................................................................126 7.2.1 Break Address Register A (BARA)...............................................................126 7.2.2 Break Address Register B (BARB) ...............................................................126 7.2.3 Break ASID Register A (BASRA)...............................................................127 7.2.4 Break ASID Register B (BASRB)................................................................ 127 7.2.5 Break Address Mask Register A (BAMRA) ................................................... 127 ...
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Canceling Hardware Standby Mode ..............................................................154 8.7.3 Hardware Standby Mode Timing..................................................................154 Section 9 On-Chip Oscillation Circuits............................................... 157 9.1 Overview........................................................................................................... .157 9.1.1 Features..................................................................................................157 9.2 Overview of the CPG ...........................................................................................158 9.2.1 CPG Block Diagram .................................................................................158 9.2.2 CPG Pin Configuration.............................................................................161 9.2.3 CPG Register ...
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Area Overview.......................................................................................193 10.1.6 PCMCIA Support ..................................................................................196 10.2 BSC Registers...................................................................................................200 10.2.1 Bus Control Register 1 (BCR1) ................................................................ 200 10.2.2 Bus Control Register 2 (BCR2) ................................................................ 203 10.2.3 Wait State Control Register 1 (WCR1) ......................................................204 10.2.4 Wait State Control Register 2 ...
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Basic Functions......................................................................................308 11.4 Interrupts......................................................................................................... .312 11.4.1 Status Flag Set Timing ...........................................................................312 11.4.2 Status Flag Clear Timing.........................................................................313 11.4.3 Interrupt Sources and Priorities..................................................................313 11.5 Usage Notes......................................................................................................314 11.5.1 Writing to Registers................................................................................314 11.5.2 Reading Registers ...................................................................................314 11.5.3 Clearing UNF in the TCR Register............................................................314 ...
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Overview.......................................................................................................... 335 13.1.1 Features................................................................................................ 335 13.1.2 Block Diagram.......................................................................................336 13.1.3 Pin Configuration ..................................................................................337 13.1.4 Register Configuration ............................................................................ 337 13.2 Register Descriptions.......................................................................................... 338 13.2.1 Receive Shift Register (SCRSR)...............................................................338 13.2.2 Receive Data Register (SCRDR)...............................................................338 13.2.3 Transmit Shift Register (SCTSR) .............................................................338 13.2.4 Transmit ...
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Section 15 I/O Ports .................................................................... 417 15.1 Overview......................................................................................................... .417 15.1.1 Features................................................................................................417 15.1.2 Block Diagram .......................................................................................417 15.1.3 Pin Configuration...................................................................................420 15.1.4 Register Configuration ............................................................................421 15.2 Register Descriptions ..........................................................................................421 15.2.1 Port Control Register (PCTR) ..................................................................421 15.2.2 Port Data Register (PDTR).......................................................................422 15.2.3 Serial Port ...
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Appendix A Pin Functions.............................................................551 A.1 Pin States.......................................................................................................... 551 A.2 Pin Specifications ............................................................................................... 554 A.3 Handling of Unused Pins......................................................................................557 A.4 Pin States in Access to Each Address Space .............................................................558 Appendix B Control Registers.........................................................594 B.1 Register Address Map...........................................................................................594 B.2 Register Bit List ...
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Section 1 Overview and Pin Functions SH7708 Series Features The SH7708, SH7708S, and SH7708R(SH7708 Series) are 32-bit RISC (reduced instruction set computer) microcomputers, featuring object code upward-compatibility with SH-1 and SH-2 microcomputers. The SH7708R is completely pin ...
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... Table 1.1 SH7708 Series Features CPU Original Hitachi SuperH RISC engine architecture 32-bit internal data bus General-register machine Sixteen 32-bit general registers (eight 32-bit bank registers) Five 32-bit control registers Four 32-bit system registers RISC-type instruction set (upward compatibility with the SH-1 and SH-2 ...
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Table 1.1 SH7708 Series Features (cont Memory 4 Gbytes of address space, 256 address spaces (8-bit ASID) management Supports single virtual memory mode and multiple virtual memory mode ...
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Table 1.1 SH7708 Series Features (cont Bus state Supports external memory access controller 32/16/8-bit external data bus (BSC) Physical address space divided into seven areas, each a maximum ...
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... Table 1.1 SH7708 Series Features (cont Product Line-up Product Number SH7708 SH7708S SH7708R On-chip Operation Model Voltage Frequency 3.3V 0.3 60MHz HD6417708F60 V 3.3V 0.3 60MHz HD6417708SF60 V HD6417708STF60 3.15-3.6V 100MHz HD6417708RF100 (typ.) Package 144-pin Plastic LQFP (FP-144F) 144-pin Plastic TQFP (TFP-144) 144-pin Plastic L-QFP (FP-144F) 5 ...
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Block Diagram Figure 1.1 shows a block diagram of the SH7708 Series. Multiplier MMU (memory management unit) Mixed instruction/ data TLB Cache controller Mixed instruction/ data cache memory External bus interface Figure 1.1 6 CPU Interrupt controller ...
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Pin Description Pin Arrangement CS5/CE1A CS4 CS3 CS2 CS1 CS0 Vss Vcc WE3/DQMUU/ICIOWR WE2/DQMUL/ICIORD CASHH/CAS2H CASHL/CAS2L 120 Vss Vcc WE1/DQMLU WE0/DQMLL CASLH CASLL/CAS/OE Vss Vcc RAS/CE MD5/RAS2 130 CKE WAIT Vss TCLK ...
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SH7708 Series Pin Functions Table 1.2 SH7708 Series Pin Functions Terminal 1 D27 2 D26 3 D25 4 D24 5 D23/Port7 D22/Port6 9 D21/Port5 10 ...
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Table 1.2 SH7708 Series Pin Functions (cont Terminal ...
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Table 1.2 SH7708 Series Pin Functions (cont Terminal 61 A16 62 A17 63 A18 64 A19 65 A20 66 A21 67 A22 A23 71 A24 72 A25 ...
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Table 1.2 SH7708 Series Pin Functions (cont Terminal IRL2 91 IRL1 92 IRL0 93 IOIS16 94 IRQOUT 95 BACK 96 97 STATUS1 98 STATUS0 99 NC 100 V SS 101 CKIO 102 V CC 103 MD4/CE2B 104 ...
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Table 1.2 SH7708 Series Pin Functions (cont Terminal 122 V CC WE1 /DQMLU 123 WE0 /DQMLL 124 CASLH 125 CASLL/CAS/OE 126 127 V SS 128 V CC RAS/CE 129 130 MD5/RAS2 131 CKE WAIT 132 133 V ...
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Register Configuration Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7708 Series normally operates in user mode, and enters privileged mode when an ...
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User mode register configuration Notes functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. 2. Banked register Figure 2 BANK0 BANK0* ...
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R0_BANK1* R0_BANK0* 2 R1_BANK1* R1_BANK0* 2 R2_BANK1* R2_BANK0* 2 R3_BANK1* R3_BANK0* 2 R4_BANK1* R4_BANK0* 2 R5_BANK1* R5_BANK0* 2 R6_BANK1* R6_BANK0* 2 R7_BANK1* R7_BANK0 R10 R11 R12 R13 R14 R15 SR SSR ...
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Register values after a reset are shown in table 2.1. Table 2.1 Initial Register Values Registers General registers R0 to R15 Control registers SR GBR, SSR, SPC VBR System registers MACH, MACL Note: Initialized ...
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System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents ...
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SSR 31 SPC 31 GBR 31 VBR 0––––––––––––––––––––––––––––0 MD: Processor operation mode bit: Indicates the processor operation mode as follows: MD =1: Privileged mode User mode MD ...
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Data Formats Data Format in Registers Register operands are always longwords (32 bits, figure 2.6). When a memory operand is only a byte (8 bits word (16 bits ...
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Address Address Address A Address Address A Byte0 Byte1 Byte2 Byte3 Address Word0 Address Longword Big-endian mode Figure 2 Instruction ...
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T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the ...
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Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Modes and Effective Addresses Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula Register direct Rn ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula Register @(disp:4, Effective address is register Rn contents indirect with Rn) with 4-bit displacement disp added. After displacement disp is zero-extended, ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula PC-relative @(disp:8, Effective address is register PC contents with PC) with 8-bit displacement disp added. After displacement disp is zero-extended, it ...
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Table 2.2 Addressing Modes and Effective Addresses (cont) Addressing Instructio Mode n Format Effective Address Calculation Method Calculation Formula PC-relative Rn Effective address is sum of register PC and Rn contents. Immediate #imm:8 8-bit immediate data imm of TST, AND, ...
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Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: Operation code mmmm: Source ...
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Table 2.3 Instruction Formats (cont) Instruction Format nm format 15 xxxx nnnn mmmm 15 md format xxxx xxxx mmmm 15 nd4 format xxxx xxxx nnnn Destination Operand Operand 0 mmmm: register nnnn: register direct direct xxxx ...
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Table 2.3 Instruction Formats (cont) Instruction Format nmd format 15 xxxx nnnn mmmm d format 15 xxxx xxxx dddd 15 d12 format xxxx dddd dddd nd8 format 15 xxxx nnnn dddd 15 i format xxxx xxxx ...
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Instruction Set Instruction Set Classified by Function The SH7708 Series instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operatio Classificati ...
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Table 2.4 Classification of Instructions (cont) Operatio Classificati Code o n Arithmetic 21 MUL operations MULS (cont) MULU NEG NEGC SUB SUBC SUBV Logic 6 AND operations NOT OR TAS TST XOR Shift 12 ...
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Table 2.4 Classification of Instructions (cont) Operatio Classificati Code Branch BRA BRAF BSR BSRF JMP JSR RTS System 15 CLRT control CLRMAC CLRS LDC LDS LDTLB NOP PREF RTE ...
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Table 2.5 Instruction Code Format Format Instruction OP.Sz SRC,DEST mnemonic Instruction MSB LSB code Operation , (xx) M/Q/T & <<n, >>n Privileged mode Execution cycles T bit Note: Scaling ( ...
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Table 2.6 lists the SH7708 Series data transfer instructions Table 2.6 Data Transfer Instructions Instruction Operation imm MOV #imm,Rn Rn (disp 2 + PC) MOV.W @(disp,PC),Rn extension (disp MOV.L @(disp,PC), MOV Rm,Rn Rm MOV.B Rm,@Rn Rm MOV.W Rm,@Rn ...
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Table 2.6 Data Transfer Instructions (cont) Instruction Operation Rm (R0 + Rn) MOV.L Rm,@(R0,Rn) (R0 + Rm) MOV.B @(R0,Rm),Rn Rn (R0 + Rm) MOV.W @(R0,Rm),Rn Rn (R0 + Rm) MOV.L @(R0,Rm),Rn R0,@(disp,GBR) R0 (disp + GBR) MOV.B R0,@(disp,GBR) R0 (disp ...
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Table 2.7 lists the SH7708 Series arithmetic instructions. Table 2.7 Arithmetic Instructions Instruction Operation ADD Rm, imm ADD #imm, ADDC Rm,Rn Carry Rn, ADDV Rm,Rn ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation Signed operation of DMULS.L Rm, MACH, MACL 32 32 Unsigned operation of DMULU.L Rm, MACH, MACL – ...
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Table 2.7 Arithmetic Instructions (cont) Instruction Operation 0–Rm Rn NEG Rm,Rn 0–Rm–T Rn, NEGC Rm,Rn Borrow T Rn–Rm Rn SUB Rm,Rn Rn–Rm–T SUBC Rm,Rn Borrow T Rn–Rm Rn, SUBV Rm,Rn Underflow Note: The normal number of execution cycles is shown. ...
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Table 2.8 lists the SH7708 Series logic operation instructions. Table 2.8 Logic Operation Instructions Instruction Operation Rn & Rm AND Rm,Rn R0 & imm AND #imm,R0 (R0 + GBR) & imm AND.B #imm,@(R0,GBR) (R0 + GBR) ~Rm NOT Rm,Rn Rn ...
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Table 2.9 lists the SH7708 Series shift instructions. Table 2.9 Shift Instructions Instruction Operation T Rn MSB ROTL Rn LSB Rn ROTR ROTCL ROTCR << Rm SHAD Rm,Rn ...
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Table 2.10 lists the SH7708 Series branch instructions. Table 2.10Branch Instructions Instruction Operation disp Æ PC; BF label nop (where label is disp + PC) Delayed branch ...
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Table 2.11 lists the SH7708 Series system control instructions. Table 2.11System Control Instructions Instruction Operation 0 MACH, MACL CLRMAC 0 S CLRS 0 T CLRT Rm SR LDC Rm,SR Rm GBR LDC Rm,GBR Rm VBR LDC Rm,VBR Rm SSR LDC ...
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Table 2.11System Control Instructions (cont) Instruction Operation (Rm) R4_BANK, LDC.L @Rm R4_BANK (Rm) R5_BANK, LDC.L @Rm R5_BANK (Rm) R6_BANK, LDC.L @Rm R6_BANK (Rm) R7_BANK, LDC.L @Rm ...
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Table 2.11System Control Instructions (cont) Instruction Operation R4_BANK Rn STC R4_BANK,Rn R5_BANK Rn STC R5_BANK,Rn R6_BANK Rn STC R6_BANK,Rn R7_BANK Rn STC R7_BANK,Rn Rn–4 Rn, SR STC.L SR,@–Rn Rn–4 Rn, GBR STC.L GBR,@–Rn Rn–4 Rn, VBR STC.L VBR,@–Rn Rn–4 Rn, ...
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Notes: 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the following: • When there is contention between an instruction fetch and data access • When ...
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Instruction Code Map Table 2.12 shows the instruction code map. Table 2.12 Instruction Code Map Instruction Code Fx: 0000 MD: 00 MSB LSB 0000 Rn Fx 0000 0000 Rn Fx 0001 0000 Rn 00MD 0010 ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 0100 Rn Fx 0000 SHLL Rn 0100 Rn Fx 0001 SHLR Rn 0100 Rn Fx 0010 STS.L MACH,@-Rn 0100 Rn 00MD 0011 STC.L SR,@-Rn 0100 Rn ...
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Table 2.12 Instruction Code Map (cont) Instruction Code Fx: 0000 MD: 00 MSB LSB 1000 00MD Rn disp MOV.B R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 1000 10MD imm/disp CMP/EQ #imm:8,R0 1000 11MD imm/disp 1001 Rn disp MOV.W @(DISP:8,PC),RN 1010 ...
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Processor States and Processor Modes Processor States The SH7708 Series has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state ...
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From any state except hardware standby mode when RESET = 0 and BREQ = 1 Power-on reset state Interrupt Bus-released state Bus Bus request request clearance Sleep mode RESET = 0, BREQ = 1 Note: Driving the ...
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50 ...
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Section 3 Memory Management Unit (MMU Overview Features The SH7708 Series has an on-chip memory management unit (MMU) that implements address translation. The SH7708 Series features a resident translation lookaside buffer (TLB) ...
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MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed ...
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SH7708 Series MMU Virtual Address Map: The SH7708 Series uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In ...
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H'00000000 2 Gbyte virtual space, cacheable (write-back/write-through) H'7F000000 On-chip RAM space H'80000000 0.5 Gbyte fixed physical space, cacheable (write-through: SH7708) (write-back/write-through: SH7708S, SH7708R) H'A0000000 0.5 Gbyte fixed physical space, non-cacheable H'C0000000 0.5 Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5 Gbyte ...
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Physical Address Space: The SH7708 Series supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 10, Bus State Controller, for details. Single Address Translation: When the MMU is ...
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Address Space Identifier (ASID): When multiple processes run in parallel sharing the same virtual address space and the processes have unique address translation tables, the virtual space can be multiplexed. The ASID is 8 bits in length and is held ...
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Register Description There are five registers for MMU processing. These are all peripheral module registers, so they are located in address space area P4 and can only be accessed from privileged mode by specifying the address. These ...
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The MMU registers are shown in figure 3. PPN 31 31 Virtual address causing TLB-related or address error exception 31 0: Reserved bits (except MMUCR): Always read as 0. Writing is ignored. (MMUCR) :Except bit 3 is read ...
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TLB Functions Configuration of the TLB The TLB caches address translation table information located in external memory. The address translation table stores the physical page number translated from the virtual page number ...
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Virtual address (1-kbyte page) 31 VPN Virtual address (4-kbyte page) (15) (2) VPN (31–17) VPN (11–10) ASID VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of ...
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TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits are used as the index number regardless of the page size. The index ...
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Virtual address Index 0 VPN(31–17) VPN(11–10) 31 Address array Figure 3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. ...
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The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes ( but not when there is sharing (SH = 1). When ...
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Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the ...
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MMU Functions MMU Hardware Management MMU hardware management is of the following two kinds. 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the ...
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MMU Instruction (LDLTB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the ...
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MMUCR Index PTEH register VPN VPN Write VPN(31–17) VPN(11–10 Address array Figure 3 Avoiding Synonym Problems When ...
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For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Virtual address 1 H'00000000 Virtual address 2 H'00000400 Virtual address 1 is recorded in cache entry ...
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When using a 4-kbyte page Virtual address VPN Physical address PPN When using a 1-kbyte page Virtual address 31 10 VPN Physical address 31 10 PPN Figure 3.10 0 Offset Virtual address ...
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MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write TLB Miss Exception A TLB miss results when the virtual address and the address ...
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If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return ...
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TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit ...
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Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the ...
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No VPNs match? Yes TLB miss exception User mode PR check 00/ R/W? R TLB protection violation exception No (noncacheable) Initial page write exception Memory access Figure 3.11 74 Start and (MMUCR. ...
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Processing Flow in Event of MMU Exception (Same Processing Flow for Address Error) Figure 3.12 shows the MMU exception signals in instruction fetch mode. MMU exception handler : Exception source stage IF = Instruction fetch ...
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Figure 3.13 shows the MMU exception signals in data access mode MMU exception handler : Exception source stage : Stage cancellation for instruction that has begun execution IF = Instruction ...
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Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in privileged mode using the MOV instruction. The TLB is assigned to the P4 area in virtual ...
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Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. These are ...
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TLB Address Array Access Read access 31 24 Address field 11110010 31 Data field VPN Write access 31 24 Address field 11110010 31 Data field VPN VPN: Virtual page number V: Valid bit A: Association bit Way (00: Way ...
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Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the VPN and ASID specified by the write data is ...
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Section 4 Exception Handling Overview Features Exceptions are deviations from normal program execution that require special handling. The processor responds to an exception by aborting execution of the current instruction (execution is ...
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A basic exception processing sequence consists of the following operations: The contents of the PC and SR are saved in the SPC and SSR, respectively. The block (BL) bit set to 1, masking any subsequent exceptions. The ...
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Table 4.2 Vectored Exception Events Exception Current Instructio Exception Event Priority* n Reset Aborted Power-on Manual reset General Aborted Address error exception and retried (instruction access) events TLB miss (instruction access) TLB invalid (instruction access) TLB ...
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Table 4.2 Vectored Exception Events (cont) Exception Current Instructio Exception Event Priority* n General Completed Nonmaskable interrupt interrupt requests External hardware interrupt Peripheral module interrupt Notes: 1. Priorities are indicated from high to low, 1 being ...
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Pipeline Sequence: Instruction n IF Instruction Instruction Detection Order: TLB miss (instruction n+1) TLB miss (instruction n) and RIE (instruction simultaneous detection Handling Order: TLB miss (instruction n) Re-execution of ...
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Exception Codes Table 4.3 lists the exception codes written to bits 11–0 of the ...
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Table 4.3 Exception Codes (cont) Exception Type Exception Event General interrupt requests External hardware interrupts (cont): (cont) Peripheral module interrupt: Note: Exception codes H'120, H'140, and H'3E0 are reserved Exception Request Masks When the BL ...
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If a general interrupt occurs when the request is masked (held pending) and not accepted until the BL bit is cleared software. For reentrant exception handling, the SPC and SSR must be saved and ...
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Exception Handler Operation Reset The reset sequence is used to power up or restart the SH7708 Series from the initialization state. The RESET signal is sampled every clock cycle, and in the ...
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The RB bit set encoded value identifying the exception event is written to bits 11–0 of the EXPEVT register. Instruction execution jumps to the vector location designated by either the sum of the vector ...
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General Exceptions TLB miss exception Conditions: Comparison of TLB addresses shows no address match Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 ...
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TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR Privileged mode 00 Only read enabled 01 Read/write enabled 10 Only read enabled 11 Read/write enabled Operations: The virtual address (32 bits) ...
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Reserved instruction exception Conditions: a. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instructions: H'Fxxx(SH7708, SH7708S), H'FxxF(SH7708R) b. When a privileged instruction not in ...
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Interrupts NMI Conditions: NMI pin edge detection Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC and SSR, respectively. H'01C0 is set in INTEVT. The BL, MD, ...
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Cautions Return from exception handling Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit before restoring them. Issue an ...
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96 ...
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Overview Features The cache specifications are listed in table 5.1. Table 5.1 Cache Specifications Parameter Specification Capacity Selectable: Normal mode: 8 kbytes Structure Instruction/data mixed, 4-way set associative (2-way set associative in ...
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Address array (ways 0–3) Entry Address Entry 1 • • • • Entry 127 22) bits Figure 5.1 Address Array: The V bit indicates whether the entry data is valid. When the ...
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In RAM mode, two ways are used as cache (way 0 and way 1). Bit 5 of the LRU bits indicates which way replaced. When bit way replaced. When bit ...
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RA: RAM bit. Indicates the cache operation mode kbytes cache/4 kbytes cache (RAM mode kbytes cache (normal mode) 0: Always set to 0 when setting the register. ...
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Virtual address Entry selection Ways 0– Address MMU 1 127 Physical address CMP0 CMP1 CMP2 CMP3 Hit signal 1 CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison ...
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Read Access Read Hit read access, instructions and data are transferred from the cache to the CPU. The transfer unit is 32 bits. The LRU is updated. Read Miss: An external bus cycle ...
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PA (31–4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31–4): Physical address written to external memory Longword 0–3: The line of cache data to be written to external memory Figure 5 Coherency of ...
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In the address field, specify the entry address for selecting the entry (bits 10–4), W for selecting the way (bits 12–11 way way way way 3 in normal mode ...
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RAM mode), and H'F1 to indicate data array access (bits 31–24). Both reading and writing use ...
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Usage Examples Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry’s V bit. When the A bit is 1, the address tag specified by the write ...
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Section 6 Interrupt Controller (INTC Overview The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user ...
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Block Diagram Figure 6.1 shows a block diagram of the INTC. IRQOUT NMI Input control IRL3–IRL0 4 (Interrupt request) TMU (Interrupt request) RTC (Interrupt request) SCI (Interrupt request) WDT (Interrupt request/ REF refresh request) ICR ...
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Pin Configuration Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Nonmaskable interrupt input pin Interrupt input pins Bus request output pin Register Configuration The INTC has ...
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NMI Interrupts The NMI interrupt has the highest priority level of 16 always accepted unless the BL bit in the status register in the CPU is set to 1, and is edge-detected. In ...
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Table 6.3 IRL3–IRL0 Pins and Interrupt Levels IRL3 IRL2 IRL1 IRL0 ...
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On-Chip Supporting Module Interrupts On-chip supporting module interrupts are generated by the following five modules: Timer unit (TMU) Realtime clock (RTC) Serial communication interface (SCI) Bus state controller (BSC) Watchdog timer (WDT) Not every interrupt ...
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When the priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they are handled according to the default order listed in table 6.4. Updating of interrupt priority level setting ...
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Table 6.4 Interrupt Exception Vectors and Rankings (cont Interrupt Interrupt Source Code Priority (Initial RTC ATI* H'480 0–15 (0) 4 RTC PRI* H'4A0 0–15 (0) 5 RTC ...
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INTC Registers Interrupt Priority Registers A and B (IPRA–IPRB) Interrupt priority registers A and B (IPRA and IPRB) are 16-bit read/write registers that set priority levels from for on-chip ...
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Interrupt Control Register (ICR) ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register ...
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INTC Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6 flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt ...
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Program execution state Interrupt No generated? Yes (SR (sleep or standby mode)? Yes No NMI? Yes Level 15 interrupt? Yes I3–I0 level 14 or lower? IRQOUT = low Set interrupt cause in INTEVT Save SR ...
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Multiple Interrupts When handling multiple interrupts, an interrupt handler should include the following procedures: 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT. The code in INTEVT can be used ...
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Interrupt Response Time The time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table ...
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Table 6.6 Interrupt Response Time (cont Response Total (5 time + 0.5 Bcyc + 0.5 Pcyc Minimum 6.5 2 case* Maximum case* Icyc: Duration of one cycle ...
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Interrupt acceptance 0.5 Icyc + 0.5 Bcyc + 2 Pcyc IRL Instruction (instruction replaced by interrupt IF exception handling) Overrun fetch First instruction of interrupt handler IF: Instruction fetch ... Instruction is fetched from memory in which program is stored. ...
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Section 7 User Break Controller (UBC Overview The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling programs to be debugged in the chip ...
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Access control BBRA: Break bus cycle register A BARA: Break address register A BASRA: Break ASID register A BAMRA: Break address mask register A BBRB: Break bus cycle register B BARB: Break address register B BASRB: Break ASID register B ...
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Register Configuration Table 7.1 shows the user break controller registers. Table 7.1 UBC Registers Channel Register Initial Value* A BARA Undefined BASRA Undefined BAMRA Undefined BBRA H'0000* B BARB Undefined BAMRB Undefined BASRB Undefined BBRB ...
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Sequential use of channels A and B is set in the SEQ bit of the BRCR. When sequential use is designated, a user break occurs when the channel B conditions are matched after matching of channel A conditions. 6. ...
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Break ASID Register A (BASRA) Bit: 7 Bit name: BASA7 BASA6 Initial value: — — R/W: R/W R/W Break ASID register A (BASRA) specifies the ASID that serves as the break condition for channel A. ...
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Bits 1 and 0—Break Address Mask A1 and A0 (BAMA1 and BAMA0): These bits indicate which of the channel A break address bits 31–0 (BAA31–BAA0) set in BARA are masked. Bit 1: BAMA1 Bit 0: BAMA0 ...
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Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether to break channel A on instruction fetch and/or data access cycles. Bit 5: IDA1 Bit 4: IDA0 Bits 3 ...
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Break Data Register B (BDRB) Bit Bit name: BDB31 BDB30 Initial value: — — R/W: R/W R/W Bit Bit name: BDB23 BDB22 Initial value: — — R/W: R/W R/W Bit: 15 ...
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Break Data Mask Register B (BDMRB) Bit Bit name: BDM31 BDM30 Initial value: — — R/W: R/W R/W Bit Bit name: BDM23 BDM22 Initial value: — — R/W: R/W R/W ...
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Break Control Register (BRCR) Bit Bit name: CMFA CMFB Initial value: 0 R/W: R/W R/W Bit: 7 Bit name: DBEB PCBB Initial value: 0 R/W: R/W R/W The break control register (BRCR) ...
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Bit 10—PC Break Select A (PCBA): Selects whether to place the channel A instruction fetch cycle break before or after instruction execution. Bit 10: PCBA Description 0 Places the channel A PC break before instruction execution. value) 1 Places the ...
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Bits 2 to 0—Reserved: These bits always read 0. The write value should always UBC Operation User Break Operation Flow The flow from break condition setting to user break trap ...
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Instruction Fetch Cycle Break 1. Making an instruction fetch/read/word setting made in the break bus cycle register (BBRA/BBRB) enables an instruction fetch cycle to be set as a break condition. In this case, pre- or ...
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Data Access Cycle Break 1. In the case of a data access cycle break, the bits used for comparison with the address bus depend on the break bus cycle register (BBRA/BBRB) operand size specification, as ...
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Saved Program Counter (PC) Value 1. When instruction fetch (pre-execution) is set as break condition The program counter (PC) value saved in the SPC in user break interrupt handling is the address of the instruction ...
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BAMRB = H'02: BBRB = H'0014: BDRB = H'00000000: BDMRB = H'00000000: Data mask H'00000000 A user break is generated after execution of the instruction at address H'00000404 with ASID= H'80, or before execution of instructions at addresses H'00008000 to ...
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For channel A, a user break trap occurs when ASID = H'80 and a longword read is performed at address H'00123454, a word read is performed at address H'00123456 byte read is performed at address H'00123456. For channel ...
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If data access (address + data) is set as a break condition, and the instruction following that at which that break condition was matched is a SLEEP instruction, the condition match flag will be set but a break will ...
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Section 8 Power-Down Modes Overview In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption Power-Down Modes The SH7708 Series have the following power-down ...
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Table 8.1 Power-Down Modes Transition Mode Conditions Sleep Execute SLEEP Runs Halts mode instruction with STBY bit cleared STBCR Standby Execute SLEEP Halts Halts mode instruction ...
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Pin Configuration Table 8.3 lists the pins used for the power-down modes. Table 8.3 Pin Configuration Processing Status 1 Pin (STATUS1) High Low Note: The “normal operation” status applies during refresh cycles even in sleep ...
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Bit 2—Module Standby 2 (MSTP2): Specifies halting the clock supply to the timer unit TMU (an on-chip supporting module). When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted. Bit 2: MSTP2 ...
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Sleep Mode Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU ...
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Table 8.4 Register States in Standby Mode Module Interrupt controller Break controller Bus state controller On-chip clock pulse generator Timer unit Realtime clock The procedure for moving to standby mode is as follows: 1. Clear the TME bit in the ...
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Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual). Keep the RESET pin low until the clock oscillation settles. The internal clock will continue to be output to the CKIO pin ...
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Clearing the Module Standby Function The module standby function can be cleared by clearing the MSTP2–MSTP0 bits power-on reset or manual reset Timing of STATUS Pin Changes ...
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Power-On Reset (Clock Modes 3 and 4): CKIO RESET Normal STATUS Bcyc Figure 8.2 Power-On Reset (Clock Mode 3 and 4) STATUS Output Manual Reset: CKIO RESET Normal STATUS 0 Bcyc or more* Note: During manual reset, ...
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Timing for Canceling Standbys Standby to Interrupt: Oscillation stops CKIO Normal STATUS Figure 8.4 Standby to Power-On Reset: Oscillation stops CKIO RESET* STATUS Normal Note: When standby mode is cleared with a power-on reset, the ...
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Standby to Manual Reset: Oscillation stops CKIO RESET* STATUS Normal Note: When standby mode is cleared with a manual reset, the WDT does not count. Keep RESET low during the PLL’s oscillation settling time. Figure 8.6 Standby to Manual Reset ...
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Sleep to Power-On Reset: CKIO RESET* STATUS Normal Note: When the PLL1’s multiplication ratio is changed by a power-on reset, keep RESET low during the PLL’s oscillation settling time. *: Undefined Figure 8.8 Sleep to Power-On Reset STATUS Output Sleep ...
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Hardware Standby Mode The hardware standby mode is provided only in the SH7708S and SH7708R. This mode is not supported in emulator Transition to Hardware Standby Mode Driving the CA pin low ...
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Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESET pin is low and the BREQ pin is high, clock ...
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CKIO CA RESET STATUS Standby Normal WDT operation 2 Rcyc or more Figure 8.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) Standby Reset Undefined Bcyc 155 ...
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Section 9 On-Chip Oscillation Circuits Overview The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. The watchdog timer (WDT single-channel timer that counts the clock settling time and ...
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Overview of the CPG CPG Block Diagram A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S) and figure 9.2(SH7708R). CAP1 CKIO Cycle = Bcyc CAP2 Crystal ...
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CAP1 CKIO Cycle = Bcyc CAP2 Crystal XTAL oscillator EXTAL Clock frequency MD2 control circuit MD1 MD0 FRQCR: Frequency control register Figure 9.2 Block Diagram of Clock Pulse Generator(SH7708R) The clock pulse generator blocks function as follows: 1. PLL Circuit ...
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The clock operation mode is set by pins MD0, MD1, and MD2. See table 9.3 for more information on clock operation modes. 3. Crystal Oscillator: This oscillator is used when a crystal oscillator ...
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CPG Pin Configuration Table 9.1 lists the CPG pins and their functions. Table 9.1 Clock Pulse Generator Pins and Functions Pin Name Symbol Description Mode control MD0 I pins MD1 I MD2 ...
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Clock Operating Modes Table 9.3 shows the relationship between the mode control pin (MD2–MD0) combinations and the clock operating modes. Table 9.4 shows the usable frequency ranges in the clock operating modes. Table 9.3 Clock Operating Modes ...
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As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied ...
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S) FRQCR Register Mode H'0102 H'0101 ...
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708, SH7708S) (cont) FRQCR Register Mode H'0102 OFF OFF H'0101 OFF OFF H'0100 OFF OFF ...
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Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) Clock Mode FRQCR H'0100 H'0101 H'0102 ON ( ...
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Table 9.5 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont) Clock Mode FRQCR H’81C0 H’81C1 H’C1C0 ON ...
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Table 9.4 Range of Usable Frequencies for Each Clock Operating Mode(SH7708R) (cont) Clock Mode FRQCR H'0100 OFF H'0101 OFF H'0102 OFF H'0111 ...
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Equal to the frequency of CKIO pin when PLL circuit 1 is off. Do not set the internal clock frequency lower than the CKIO pin frequency. 5. The frequency of the peripheral clock (P ) becomes: The product of the ...
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Register Descriptions Frequency Control Register (FRQCR) The frequency control register (FRQCR 16-bit read/write register used to specify whether a clock is output from the CKIO pin, the on/off state of ...
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Bit 7: PLLEN Description 0 PLL circuit 1 is not used.(Initial value) 1 PLL circuit 1 is used. Bit 6—PLL Standby (PSTBY): Specifies PLL standby. When PLL standby is active, PLL circuit 1 will be in standby mode at the ...
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Bit 1: PFC1 Bit 0: PFC0 Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin Bit: 15 ...
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Bits 13, 1 and 0—Peripheral Clock Frequency Division Ratio (PFC): These bits specify the division ratio of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO ...
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Changing the Frequency The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit changing the division rates of dividers 1 and 2. All ...
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PLL Standby Function Overview of the PLL Standby Function When operating in clock modes 3 and 4, the internal clock can be controlled by turning the PLL1 circuit on and off. A ...
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In clock modes 3 and 4, the SH7708 Series cannot go to standby mode while PLL circuit 1 is on. Always set PSTBY and PLLEN stop PLL circuit 1 before going to standby mode. 4. When ...
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Overview of the Watchdog Timer (WDT Block Diagram of the WDT Figure 9.4 shows a block diagram of the WDT. Standby Standby cancellation control Internal Reset reset control request Interrupt Interrupt request ...
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Table 9.5 Register Configuration Name Abbreviatio n Watchdog timer counter WTCNT Watchdog timer WTCSR control/status register Note: Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or longword writes are not possible. Read with ...
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Bit 7—Timer Enable (TME): Starts and stops timer operation. Clear this bit to 0 when using the WDT in standby mode or when changing the clock frequency. Bit 7: TME Description 0 Timer disabled: Count-up stops and WTCNT value is ...
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Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Division Ratio Note: If bits CKS2–CKS0 are modified when the WDT is running, the up-count may ...
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Using the WDT Canceling Standbys The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is described below. (The WDT does not run ...
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Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2–CKS0 bits, and ...
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Usage Notes WTCNT should be set as shown below when using the SH7708 WDT in watchdog timer mode or interval timer mode. (a) WTCNT setting WTCNT = No set value + 1? Yes SLEEP ...
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Notes on Board Design When Using an External Crystal Resonator: Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL and XTAL pins. To prevent induction from interfering with correct ...
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Avoid crossing signal lines V (PLL2) CC CAP2 C2 V (PLL2 (PLL1) CC CAP1 C1 V (PLL1) SS Figure 9.9 Points for Attention when Using PLL Oscillator Circuit Power supply V CC Reference values C1 = 470 pF ...
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