PHB21N06LT Philips Semiconductors, PHB21N06LT Datasheet
PHB21N06LT
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PHB21N06LT Summary of contents
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... N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:- • d.c. to d.c. converters • switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING SOT78 (TO220AB) PIN ...
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... Resistive load Measured from tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad MHz Product specification PHP21N06LT, PHB21N06LT PHD21N06LT MIN. MAX refer TYP. MAX. ...
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... Fig.3. Safe operating area f & Transient thermal impedance, Zth j-mb (K/ 0.1 0.01 1E-06 125 150 175 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT MIN. TYP. MAX. UNIT - - - - - 1 RDS(on) = VDS/ ID D.C. 100 ms 10 Drain-Source Voltage, VDS ( ˚ f single pulse; parameter t ...
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... Fig.9. Normalised drain-source on-state resistance 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 3.5 4 4.5 5 -60 -40 -20 V GS(TO) 4 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT Transconductance, gfs (S) VDS > RDS(ON Drain current Normalised On-state Resistance -40 - 100 120 140 160 180 ...
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... Fig.15. Maximum permissible non-repetitive iss oss rss avalanche current (I VDD = Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 175 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) ); conditions parameter T SDS GS ( prior to avalanche = 150 C 0.01 0.1 1 Avalanche time, t (ms) ...
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... ( scale 1.3 0.7 15.8 6.4 10.3 15.0 2.54 1.0 0.4 15.2 5.9 9.7 13.5 REFERENCES JEDEC EIAJ TO-220 6 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT SOT78 ( max. 3.30 3.8 3.0 2.6 3.0 2.79 3.6 2.7 2.2 EUROPEAN ISSUE DATE PROJECTION 97-06-11 Rev 1.500 ...
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... Epoxy meets UL94 V0 at 1/8". August 1999 transistor E mounting 2 scale max. 0.85 0.64 1.60 10.30 2.90 15.40 11 2.54 0.60 0.46 1.20 9.70 2.10 14.80 REFERENCES IEC JEDEC EIAJ 7 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 2 -PAK); 3 leads SOT404 base 2.60 2.20 EUROPEAN ISSUE DATE PROJECTION 98-12-14 99-06-25 Rev 1.500 ...
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... Philips Semiconductors N-channel TrenchMOS Logic level FET MOUNTING INSTRUCTIONS Dimensions in mm August 1999 transistor 11.5 9.0 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting . 8 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 17.5 Rev 1.500 ...
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... max. max. max. min. max. 0.89 1.1 5.36 0.4 6.22 4.81 6.73 2.285 4.57 4.0 0.71 0.9 5.26 0.2 5.98 6.47 4.45 REFERENCES IEC JEDEC EIAJ 9 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT SOT428 max. max. min. 0.7 10.4 2.95 0.2 0.2 0.5 2.55 0.5 9.6 EUROPEAN ISSUE DATE PROJECTION 98-04-07 Rev 1.500 ...
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... Philips Semiconductors N-channel TrenchMOS Logic level FET Dimensions in mm August 1999 transistor 7.0 2.15 2.5 4.57 Fig.20. SOT428 : soldering pattern for surface mounting . 10 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT 7.0 1.5 Rev 1.500 ...
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... Philips customers using or selling these products for use in such applications their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 transistor 11 Product specification PHP21N06LT, PHB21N06LT PHD21N06LT Rev 1.500 ...