MC68008P8 Motorola, MC68008P8 Datasheet

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MC68008P8

Manufacturer Part Number
MC68008P8
Description
Microprocessor, 16-/ 32-bit data and address registers, 16-Mbyte direct addressing range, memory-mapped input/output (I/O), 14 addressing modes, 8MHz
Manufacturer
Motorola
Datasheet
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
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registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
µ MOTOROLA
©MOTOROLA INC., 1993
Microprocessors User’s Manual
8-/16-/32-Bit
M68000
Ninth Edition
µ
are

MC68008P8 Summary of contents

Page 1

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...

Page 2

... Data Bus...................................................................................................... 3-4 3.3 Asynchronous Bus Control.......................................................................... 3-4 3.4 Bus Arbitration Control ................................................................................ 3-5 3.5 Interrupt Control .......................................................................................... 3-6 3.6 System Control............................................................................................ 3-7 3.7 M6800 Peripheral Control ........................................................................... 3-8 3.8 Processor Function Codes .......................................................................... 3-8 3.9 Clock ........................................................................................................... 3-9 3.10 Power Supply .............................................................................................. 3-9 3.11 Signal Summary ......................................................................................... 3-10 MOTOROLA TABLE OF CONTENTS Title Section 1 Overview Section 2 Introduction Section 3 Signal Description M68000 USER’S MANUAL Page Number vii ...

Page 3

... Synchronous Operation ............................................................................ 5-35 6.1 Privilege Modes............................................................................................ 6-1 6.1.1 Supervisor Mode ...................................................................................... 6-2 6.1.2 User Mode ................................................................................................ 6-2 6.1.3 Privilege Mode Changes .......................................................................... 6-2 6.1.4 Reference Classification........................................................................... 6-3 6.2 Exception Processing................................................................................... 6-4 6.2.1 Exception Vectors .................................................................................... 6-4 6.2.2 Kinds Of Exceptions ................................................................................. 6-5 6.2.3 Multiple Exceptions................................................................................... 6-8 viii Title Section 4 8-Bit Bus Operations Section 5 16-Bit Bus Operations Section 6 Exception Processing M68000 USER’S MANUAL Page Number MOTOROLA ...

Page 4

... Conditional Instruction Execution Times ..................................................... 7-7 7.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times............... 7-8 7.10 Multiprecision Instruction Execution Times ................................................. 7-8 7.11 Miscellaneous Instruction Execution Times ................................................ 7-9 7.12 Exception Processing Instruction Execution Times ................................... 7-10 MOTOROLA Title Section 6 Exception Processing Section 7 8-Bit Instruction Timing M68000 USER’S MANUAL Page Number ...

Page 5

... Maximum Ratings ..................................................................................... 10-1 10.2 Thermal Characteristics ............................................................................ 10-1 10.3 Power Considerations ............................................................................... 10-2 10.4 CMOS Considerations .............................................................................. 10-4 10.5 AC Electrical Specifications Definitions..................................................... 10-5 10.6 MC68000/68008/68010 DC Electrical Characteristics .............................. 10-7 10.7 DC Electrical Characteristics .................................................................... 10-8 10.8 AC Electrical Specifications—Clock Timing .............................................. 10-8 x Title Section 8 16-Bit Instruction Timing Section 9 MC68010 Instruction Timing Section 10 Electrical and Thermal Characteristics M68000 USER’S MANUAL Page Number MOTOROLA ...

Page 6

... MC68EC000 AC Electrical Specifications—Bus Arbitration .................... 10-28 Ordering Information and Mechanical Data 11.1 Pin Assignments........................................................................................ 11-1 11.2 Package Dimensions ................................................................................ 11-7 B.1 Data Transfer Operation............................................................................. B-1 B.2 Interrupt Interface Operation ...................................................................... B-4 MOTOROLA Title Section 10 Electrical and Thermal Characteristics Section 11 Appendix A MC68010 Loop Mode Operation Appendix B M6800 Peripheral Interface M68000 USER’S MANUAL ...

Page 7

... Read-Modify-Write Cycle Timing Diagram........................................................... 5-8 5-10 CPU Space Address Encoding ............................................................................ 5-9 5-11 Interrupt Acknowledge Cycle Timing Diagram ................................................... 5-10 5-12 Breakpoint Acknowledge Cycle Timing Diagram ............................................... 5-11 5-13 3-Wire Bus Arbitration Flowchart (NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-12 5-14 2-Wire Bus Arbitration Cycle Flowchart ............................................................. 5-13 xii LIST OF ILLUSTRATIONS Title M68000 USER’S MANUAL Page Number MOTOROLA ...

Page 8

... MC68000 Power Dissipation ( Ambient Temperature ( ..................... 10-3 10-2 Drive Levels and Test Points for AC Specifications ........................................... 10-6 10-3 Clock Input Timing Diagram ............................................................................... 10-9 10-4 Read Cycle Timing Diagram ............................................................................ 10-13 10-5 Write Cycle Timing Diagram............................................................................. 10-14 10-6 MC68000 to M6800 Peripheral Timing Diagram (Best Case) .......................... 10-16 MOTOROLA Title M68000 USER’S MANUAL Page Number xiii ...

Page 9

... Case 840B-01—FU Suffix................................................................................ 11-16 A-1 DBcc Loop Mode Program Example................................................................... A-1 B-1 M6800 Data Transfer Flowchart ......................................................................... B-1 B-2 Example External VMA Circuit ............................................................................ B-2 B-3 External VMA Timing .......................................................................................... B-2 B-4 M6800 Peripheral Timing—Best Case................................................................ B-3 B-5 M6800 Peripheral Timing—Worst Case ............................................................. B-3 B-6 Autovector Operation Timing Diagram................................................................ B-5 xiv Title M68000 USER’S MANUAL Page Number MOTOROLA ...

Page 10

... Miscellaneous Instruction Execution Times ....................................................... 7-10 7-14 Move Peripheral Instruction Execution Times .................................................... 7-10 7-15 Exception Processing Instruction Execution Times ........................................... 7-11 8-1 Effective Address Calculation Times.................................................................... 8-2 8-2 Move Byte Instruction Execution Times ............................................................... 8-2 8-3 Move Word Instruction Execution Times.............................................................. 8-3 8-4 Move Long Instruction Execution Times .............................................................. 8-3 MOTOROLA LIST OF TABLES Title M68000 USER’S MANUAL Page Number xv ...

Page 11

... Multiprecision Instruction Execution Times ........................................................ 9-11 9-18 Miscellaneous Instruction Execution Times ....................................................... 9-12 9-19 Exception Processing Instruction Execution Times ........................................... 9-13 10-1 Power Dissipation and Junction Temperature vs Temperature ( ........................................................................................................ 10-4 10-2 Power Dissipation and Junction Temperature vs Temperature ( ........................................................................................................ 10-4 A-1 MC68010 Loop Mode Instructions ...................................................................... A-3 xvi Title M68000 USER’S MANUAL Page Number MOTOROLA ...

Page 12

... MC68008 differs from the others in that the data bus size is eight bits, and the address range is smaller. The MC68010 has a few additional instructions and instructions that operate differently than the corresponding instructions of the other devices. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 1- 1 ...

Page 13

... The MC68010 utilizes VLSI technology and is a fully implemented 16-bit microprocessor with 32-bit registers, a rich basic instruction set, and versatile addressing modes. The vector base register (VBR) allows the vector table to be dynamically relocated 1-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL MOTOROLA ...

Page 14

... The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with 8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code density with low memory bandwidth requirements. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 1- 3 ...

Page 15

... The second set of seven registers (A0–A6) and the user stack pointer (USP) can be used as software stack pointers and base address registers. In addition, the address registers can be used for word and long-word operations. All of the 16 registers can be used as index registers. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-1 ...

Page 16

... (USP) POINTER CCR A7' (SSP CCR SR EIGHT DATA REGISTERS SEVEN ADDRESS REGISTERS USER STACK PROGRAM COUNTER STATUS REGISTER SUPERVISOR STACK POINTER STATUS REGISTER MOTOROLA ...

Page 17

... MASK 2.2 DATA TYPES AND ADDRESSING MODES The five basic data types supported are as follows: 1. Bits 2. Binary-Coded-Decimal (BCD) Digits (4 Bits) 3. Bytes (8 Bits) 4. Words (16 Bits) 5. Long Words (32 Bits) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL CCR 2 (MC68010) SYSTEM BYTE USER BYTE ...

Page 18

... Implied The register indirect addressing modes provide postincrementing, predecrementing, offsetting, and indexing capabilities. The program counter relative mode also supports indexing and offsetting. For detail information on addressing modes refer to M68000PM/AD, M68000 Programmer Reference Manual . 2-4 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA ...

Page 19

... Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word operands the low-order 16 bits, and long-word operands, the entire 32 bits. The least significant bit is addressed as bit zero; the most significant bit is addressed as bit 31. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL Mode ...

Page 20

... M68000 MPUs. The organization of data in the memory of the MC68008 is shown in Figure 2-7. 2-6 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL WORD 0 BYTE 000000 WORD 1 BYTE 000002 WORD 7FFFFF BYTE FFFFFE BYTE 000001 BYTE 000003 BYTE FFFFFE MOTOROLA ...

Page 21

... MSB = MOST SIGNIFICANT BIT LSB = LEAST SIGNIFICANT BIT MSD BCD 0 BCD 4 MSD = MOST SIGNIFICANT DIGIT LSD = LEAST SIGNIFICANT DIGIT Figure 2-6. Data Organization in Memory MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL BIT DATA 1 BYTE = 8 BITS INTEGER DATA 1 BYTE = 8 BITS ...

Page 22

... BYTE 0 BYTE 1 BYTE 2 BYTE 3 1 WORD = 2 BYTES = 16 BITS (MS BYTE) WORD 0 (LS BYTE) (MS BYTE) WORD 1 (LS BYTE) HIGH-ORDER WORD LONG WORD 0 LOW-ORDER WORD HIGH-ORDER WORD LONG WORD 1 LOW-ORDER WORD LOWER ADDRESSES HIGHER ADDRESSES LOWER ADDRESSES HIGHER ADDRESSES LOWER ADDRESSES HIGHER ADDRESSES MOTOROLA ...

Page 23

... The destination operand is subtracted from the source < — Relational test, true if source operand is less than > — Relational test, true if source operand is greater than V — Logical OR MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL (S), double (D), extended (X), or packed (P). specifies the source register) ...

Page 24

... SSP; (vector) are performed. If the condition is false and the optional "else" clause is present, the operations after "else" are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. (SSP); SSP–2 SSP; SR (SSP); PC MOTOROLA ...

Page 25

... CLR 0 Destination CMP Destination—Source CMPA Destination—Source CMPI Destination —Immediate Data CMPM Destination—Source DBcc If condition false then (Dn – –1 then MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL Operation Destination Destination Destination Destination Destination Destination Destination Destination SR Destination PC Z ...

Page 26

... EOR Dn,<ea> EORI # <data>,<ea> EORI # <data>,CCR EORI # <data>,SR EXG Dx,Dy EXG Ax,Ay EXG Dx,Ay EXG Ay,Dx EXT.W Dn extend byte to word EXT.L Dn extend word to long word ILLEGAL JMP <ea> JSR <ea> LEA <ea>,An LINK An, # <displacement> LSd 1 Dx,Dy LSd 1 # <data>,Dy LSd 1 <ea> MOVE <ea>,<ea> MOVEA <ea>,An MOVE CCR,<ea> MOVE <ea>,CCR MOVE SR,<ea> MOVE <ea>,SR MOTOROLA ...

Page 27

... RESET If supervisor state then Assert RESET Line else TRAP ROL, ROR Destination Rotated by <count> ROXL, Destination Rotated with X by <count> ROXR RTD (SP) PC MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL Operation USP Rc Rn Destination Destination Destination Destination Destination Destination Destination ...

Page 28

... SSP–2 SSP; PC Condition Codes RTE RTR RTS SBCD Dx,Dy SBCD –(Ax),–(Ay) Scc <ea> STOP # <data> SUB <ea>,Dn SUB Dn,<ea> SUBA <ea>,An SUBI # <data>,<ea> SUBQ # <data>,<ea> SUBX Dx,Dy SUBX –(Ax),–(Ay) SWAP Dn TAS <ea> TRAP # <vector> TRAPV TST <ea> UNLK An MOTOROLA ...

Page 29

... The term negate or negation is used to indicate that a signal is inactive or false. PROCESSOR STATUS MC6800 PERIPHERAL CONTROL SYSTEM CONTROL Figure 3-1. Input and Output Signals (MC68000, MC68HC000 and MC68010) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE V CC (2) ADDRESS GND(2) BUS CLK DATA BUS AS R/W ...

Page 30

... FC0 LDS FC1 MC68EC000 FC2 DTACK BR BG IPL0 BERR RESET IPL1 HALT IPL2 AVEC MODE (MC68EC000) A23–A0 D15–D0 ASYNCHRONOUS BUS CONTROL BUS ARBITRATION CONTROL INTERRUPT CONTROL A23–A0 D15–D0 ASYNCHRONOUS BUS CONTROL BUS ARBITRATION CONTROL INTERRUPT CONTROL MOTOROLA ...

Page 31

... This bus provides the address for bus operation during all cycles except interrupt acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles, address lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and address lines A23–A4 are driven to logic high. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL V CC (2) ADDRESS ...

Page 32

... When the R/W line is high, the processor reads from the data bus. When the R/W line is low, the processor drives the data bus. In 8-bit mode, UDS is always forced high and the LDS signal is used. 3-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL UDS LDS , ). MOTOROLA ...

Page 33

... In the 48-pin version of the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration scheme. All M68000 processors can use two-wire bus arbitration. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL LDS W R/ D8– ...

Page 34

... IPL0 and IPL2, which provides four interrupt priority levels: levels and 7. In all other respects, the interrupt priority levels in this version of the MC68008 are identical to those levels in the other microprocessors described in this manual. 3-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BGACK ). IPL0 IPL1 IPL2 , , ) NOTE MOTOROLA ...

Page 35

... This input should be changed only at reset and must be stable two clocks after RESET is negated. Changing this input during normal operation may produce unpredictable results. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3- 7 ...

Page 36

... PROCESSOR FUNCTION CODES (FC0, FC1, FC2) These function code outputs indicate the mode (user or supervisor) and the address space type currently being accessed, as shown in Table 3-3. The function code outputs are valid whenever AS is active. 3-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL VPA ) ) MOTOROLA ...

Page 37

... Section 10 Electrical Characteristics. 3.10 POWER SUPPLY (V Power is supplied to the processor using these connections. The positive output of the power supply is connected to the V MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL FC1 FC0 Address Space Type ...

Page 38

... CLK Input High V CC Input — GND Input — Hi-Z HALT On On Bus Relinquish Yes Yes Yes Yes No Yes No Yes No Yes No Yes — — No* No* No* No Yes Yes No No — — — — MOTOROLA ...

Page 39

... The 8-bit operation must perform two or four read cycles to access a word or long word, asserting the data strobe to read a single byte during each cycle. The address bus in 8-bit operation includes A0, which selects the appropriate byte for each read cycle. Figure 4-1 and 4-2 illustrate the byte read-cycle operation. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4- 1 ...

Page 40

... Figure 4-2. Read and Write-Cycle Timing Diagram 4-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7–D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) REMOVE DATA FROM D7–D0 2) NEGATE DTACK WRITE 2 WAIT STATE READ MOTOROLA ...

Page 41

... Figures 4-3 and 4-4 illustrate the write-cycle operation The 8-bit operation performs two write cycles for a word write operation, issuing the data strobe signal during each cycle. The address bus includes the A0 bit to select the desired byte. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE 4- 3 ...

Page 42

... DTACK D7–D0 ODD BYTE WRITE Figure 4-4. Write-Cycle Timing Diagram 4-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) STORE DATA ON D7–D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) NEGATE DTACK EVEN BYTE WRITE ODD BYTE WRITE MOTOROLA ...

Page 43

... The TAS instruction (the only instruction that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write cycles are byte operations. Figure 4-5 and 4-6 illustrate the read-modify-write cycle operation. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4- 5 ...

Page 44

... INPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7–D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) REMOVE DATA FROM D7–D0 2) NEGATE DTACK INPUT THE DATA 1) STORE DATA ON D7–D0 2) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) NEGATE DTACK MOTOROLA ...

Page 45

... DTACK or BERR at this time. STATES 8–11 The bus signals are unaltered during S8–S11, during which the arithmetic logic unit makes appropriate modifications to the data. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 INDIVISIBLE CYCLE ...

Page 46

... Refer to Section 5 16-Bit Bus Operations for information on the following items: • CPU Space Cycle • Bus Arbitration — Bus Request — Bus Grant — Bus Acknowledgment • Bus Control • Bus Errors and Halt Operations • Reset Operations • Asynchronous Operations • Synchronous Operations 4-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 47

... When the data is received, the processor internally positions the byte appropriately. The word read-cycle flowchart is shown in Figure 5-1 and the byte read-cycle flowchart is shown in Figure 5-2. The read and write cycle timing is shown in Figure 5-3 and the word and byte read-cycle timing diagram is shown in Figure 5-4. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 1 ...

Page 48

... TERMINATE THE CYCLE 1) REMOVE DATA FROM D15–D0 2) NEGATE DTACK SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7–D0 OR D15–D8 (BASED ON UDS OR LDS) 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) TERMINATE THE CYCLE 1) REMOVE DATA FROM D7–D0 OR D15–D8 2) NEGATE DTACK MOTOROLA ...

Page 49

... CLK FC2–FC0 A23– UDS LDS R/W DTACK D15–D8 D7–D0 READ *Internal Signal Only Figure 5-4. Word and Byte Read-Cycle Timing Diagram MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL WRITE 2 WAIT STATE READ WRITE READ ...

Page 50

... LDS and writes both bytes. When the instruction specifies a byte operation, the processor uses the internal A0 bit to determine which byte to write and issues the appropriate data strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is asserted. 5-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE MOTOROLA ...

Page 51

... TERMINATE OUTPUT TRANSFER 1) NEGATE UDS AND LDS 2) NEGATE AS 3) REMOVE DATA FROM D7-D0 OR D15-D8 4) SET R/W TO READ START NEXT CYCLE Figure 5-6. Byte Write-Cycle Flowchart MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) STORE DATA ON D15–D0 3) ASSERT DATA TRANSFER ACKNOWLEDGE (DTACK) ...

Page 52

... S4, the processor inserts wait states (full clock cycles) until either DTACK or BERR is asserted. STATE 5 During S5, no bus signals are altered. STATE 6 During S6, no bus signals are altered. 5-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL EVEN BYTE WRITE ODD BYTE WRITE MOTOROLA ...

Page 53

... NEGATE UDS OR LDS 2) NEGATE AS 3) REMOVE DATA FROM D7–D0 OR D15–D8 4) SET R/W TO READ START NEXT CYCLE Figure 5-8. Read-Modify-Write Cycle Flowchart MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL SLAVE INPUT THE DATA 1) DECODE ADDRESS 2) PLACE DATA ON D7–D0 OR D15–D0 3) ASSERT DATA TRANSFER ...

Page 54

... DTACK or BERR at this time. STATES 8–11 The bus signals are unaltered during S8–S11, during which the arithmetic logic unit makes appropriate modifications to the data. 5-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 INDIVISIBLE CYCLE MOTOROLA ...

Page 55

... The MC68010 defines an additional type of CPU space cycle, the breakpoint acknowledge cycle, in which A16–A19 are all low. Other configurations of A16–A19 are reserved by Motorola to define other types of CPU cycles used in other M68000 Family microprocessors. Figure 5-10 shows the encoding of CPU space addresses ...

Page 56

... Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not recognize anything on data lines D8 through D15 at this time. Figure 5-11. Interrupt Acknowledge Cycle Timing Diagram 5-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL IACK CYCLE STACK (VECTOR NUMBER PCL ACQUISITION) (SSP STACK AND VECTOR FETCH MOTOROLA ...

Page 57

... The MC68000, MC68HC000, MC68HC001, and MC68010 can do 3-wire bus arbitration. Figures 5-13 and 5-15 show 3-wire bus arbitration and Figures 5-14 and 5-16 show 2-wire bus arbitration. Bus arbitration on all microprocessors, except the 48-pin MC68008 and MC68EC000, BGACK must be pulled high for 2-wire bus arbitration. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S6 S0 ...

Page 58

... CURRENT CYCLE TO COMPLETE 3) NEXT BUS MASTER ASSERTS BUS GRANT ACKNOWLEDGE (BGACK) TO BECOME NEW MASTER 4) BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PRO- CESSOR USES RELEASE BUS MASTERSHIP 1) NEGATE BGACK MOTOROLA ...

Page 59

... D15– BGACK PROCESSOR DMA DEVICE Figure 5-15. 3-Wire Bus Arbitration Timing Diagram (Not Applicable to 48-Pin MC68008 or MC68EC000) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL REQUESTING DEVICE REQUEST THE BUS 1) ASSERT BUS REQUEST (BR) OPERATE AS BUS MASTER 1) EXTERNAL ARBITRATION DETER- MINES NEXT BUS MASTER ...

Page 60

... The bus grant acknowledge signal on all the processors except the 48-pin MC68008 and MC68EC000 helps to prevent the bus arbitration circuitry from responding to noise on the 5-14 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL PROCESSOR DMA DEVICE MOTOROLA ...

Page 61

... Section 10 Electrical Characteristic) has been met. The input asynchronous signal is sampled on the falling edge of the clock and is valid internally after the next falling edge. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 15 ...

Page 62

... When a bus request is made after the MPU has begun a bus cycle and before AS has been asserted (S0), the special sequence shown in Figure 5-21 applies. Instead of being asserted on the next rising edge of clock delayed until the second rising edge following its internal assertion. 5-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL CLK 47 MOTOROLA ...

Page 63

... G = Bus Grant T = Three-state Control to Bus Control Logic X = Don't Care Figure 5-18. Bus Arbitration Unit State Diagrams Figures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures 5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

Page 64

... Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active 5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED ALTERNATE BUS MASTER PROCESSOR MOTOROLA ...

Page 65

... BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-20. 3-Wire Bus Arbitration Timing Diagram—Bus Inactive MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS INACTIVE ALTERNATE BUS MASTER PROCESSOR 5- 19 ...

Page 66

... D15–D0 PROCESSOR Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case 5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BGACK NEGATED INTERNAL BGACK SAMPLED BGACK NEGATED S4 S6 ALTERNATE BUS MASTER PROCESSOR MOTOROLA ...

Page 67

... AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE BR NEGATED INTERNAL BR SAMPLED BR NEGATED ALTERNATE BUS MASTER ...

Page 68

... BR SAMPLED BR ASSERTED CLK BGACK FC2–FC0 A23–A1 AS UDS LDS R/W DTACK D15–D0 PROCESSOR Figure 5-23. 2-Wire Bus Arbitration Timing Diagram—Bus Inactive 5-22 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS ALTERNATE BUS MASTER INACTIVE PROCESSOR MOTOROLA ...

Page 69

... The MC68010 pushes enough information on the stack to be able to resume execution of the instruction following return from the bus error exception handler. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL BUS RELEASED FROM THREE STATE AND ...

Page 70

... MC68010 late bus error CLK FC2–FC0 A23–A1 AS LDS/UDS R/W DTACK D15–D0 BERR HALT INITIATE READ Figure 5-25. Bus Error Timing Diagram 5-24 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL RESPONSE BUS ERROR FAILURE DETECTION INITIATE BUS ERROR STACKING MOTOROLA ...

Page 71

... After the processor has placed the required information on the stack, the bus error exception vector is read from vector table entry 2 (offset $08) and placed in the program counter. The processor resumes execution at the address in the vector, which is the first instruction in the bus error handler routine. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S4 S6 ...

Page 72

... HALT is asserted by an external device. Figure 5-28 shows the timing of the delayed operation CLK FC2-FC0 A23–A1 AS LDS/UDS R/W DTACK D15–D0 BERR HALT READ Figure 5-27. Retry Bus Cycle Timing Diagram 5-26 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE CLOCK PERIOD HALT RETRY MOTOROLA ...

Page 73

... HALT is asserted. HALT) 5.4.3 Halt Operation ( HALT performs a halt/run/single-step operation similar to the halt operation of an MC68000. When HALT is asserted by an external device, the processor halts and remains halted as long as the signal remains asserted, as shown in Figure 5-29. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S6 HALT NOTE S0 ...

Page 74

... A retry operation does not initiate exception processing; a bus error during a retry operation does not cause a double bus fault. The processor can continue to retry a bus cycle indefinitely if external hardware requests. 5-28 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S6 HALT RETRY MOTOROLA ...

Page 75

... For the initial reset, RESET and HALT must be asserted for at least 100 ms. For a subsequent external reset, asserting these signals for 10 clock cycles or longer resets the processor. However, an external reset signal that is asserted while the processor is MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL T ...

Page 76

... HALT are asserted following DTACK (case 6). BERR is negated coincident with or after DTACK. HALT must be held at least one cycle after BERR. Table 5-1 shows the details of the resulting bus cycle termination in the M68000 microprocessors for various combinations of signal sequences. 5-30 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL DTACK BERR HALT , , AND MOTOROLA ...

Page 77

... Delay DTACK until the data is verified. If data is invalid, return BERR at the same time as DTACK (case 3). 3. For an MC68010, return DTACK before data verification. If data is invalid, assert BERR and HALT to retry the error cycle (case 6). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL DTACK BERR ...

Page 78

... Takes bus error trap. • or • • or • Illegal sequence; usually traps to vector number 0. • • Reruns the bus cycle. • • May lengthen next cycle. • or • • If next cycle is started, it will be terminated as a bus • or none error. Results—Next Cycle MOTOROLA ...

Page 79

... No maximum time is specified from the assertion the assertion of DTACK. During this unlimited time, the processor inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 5-33 shows the important timing parameters for a pseudo-asynchronous read cycle. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 33 ...

Page 80

... If DTACK remains asserted past the time specified by parameter #28, the processor may recognize it as being asserted early in the next bus cycle and may terminate that cycle prematurely. Figure 5-34 shows the important timing specifications for a pseudo-asynchronous write cycle. 5-34 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 81

... Also, the R/W signal is driven high; parameter #18 defines the delay from the same rising edge to the transition of R/W . The minimum value for parameter #18 applies to a read cycle preceded by a write cycle; this value MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 11 20A ...

Page 82

... The hold time for data relative to the negation of AS and UDS, LDS, and/ specified by parameter #29. For a write cycle, only AS and UDS, LDS, and/or DS are negated; timing parameter #12 also applies. 5-36 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 83

... Figure 5-35 shows a synchronous read cycle and the important timing parameters that apply. The timing for a synchronous read cycle, including relevant timing parameters, is shown in Figure 5-36. S0 CLOCK 6 ADDR AS UDS/LDS 18 R/W DTACK DATA Figure 5-35. Synchronous Read Cycle MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

Page 84

... The high-gain characteristics of the devices comprising the latches quickly resolve a marginal signal into a valid state. EXT SIGNAL CLK CLK 5-38 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Figure 5-37. Input Synchronizers INT D Q SIGNAL G MOTOROLA ...

Page 85

... The late BERR in an MC68010 that is operating in a synchronous mode must meet setup time parameter #27A. That is, when BERR is asserted after DTACK, BERR must be asserted before the falling edge of the clock, one clock cycle after DTACK is recognized. Violating this requirement may cause the MC68010 to operate erratically. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5- 39 ...

Page 86

... The privilege mode determines which operations are legal. The mode is optionally used by an external memory management device to control and translate accesses. The mode is also used to choose between the supervisor stack pointer (SSP) and the user stack pointer (USP) in instruction references. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6- 1 ...

Page 87

... Once the processor is in the user mode and executing instructions, only exception processing can change the privilege mode. During exception processing, the current state of the S bit of the status register is saved, and the S bit is set, putting the processor in the 6-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE MOTOROLA ...

Page 88

... Table 6-1. Reference Classification Function Code Output FC2 *Address space 3 is reserved for user definition, while 0 and 4 are reserved for future use by Motorola. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL NOTE FC1 FC0 Address Space 0 0 (Undefined, Reserved ...

Page 89

... MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 until the VBR is changed via the move control register MOVEC instruction. WORD 0 WORD 1 Figure 6-1. Exception Vector Format 6-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE EVEN BYTE (A0=0) NEW PROGRAM COUNTER (HIGH) NEW PROGRAM COUNTER (LOW) EVEN BYTE (A0=0) A1=0 A1=1 MOTOROLA ...

Page 90

... Kinds of Exceptions Exceptions can be generated by either internal or external causes. The externally generated exceptions are the interrupts, the bus error, and reset. The interrupts are MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL D8 D7 ...

Page 91

... In addition, illegal instructions, word fetches from odd addresses, and privilege violations cause exceptions. Tracing is similar to a very high priority, internally generated interrupt following each instruction. 6-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 92

... NOTES: 1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future enhancements by Motorola. No user peripheral devices should be assigned these numbers. 2. Reset vector (0) requires four words, unlike the other vectors which only require two words, and is located in the supervisor program space. ...

Page 93

... This rule does not apply to the reset exception; its handler is executed first even though it has the highest priority, because the reset operation clears all other exceptions. 6-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 94

... Although some formats are specific to a particular M68000 Family processor, the format 0000 is always legal and indicates that just the first four words of the frame are present. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Processing Exception Processing Begins within Two Clock Cycles ...

Page 95

... M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL EVEN BYTE ODD BYTE 0 7 STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW VECTOR OFFSET OTHER INFORMATION DEPENDING ON EXCEPTION Figure 6-6. MC68010 Stack Frame 0 0 HIGHER ADDRESS 0 HIGHER ADDRESS MOTOROLA ...

Page 96

... Any processing in progress at the time of the reset is aborted and cannot be recovered. The processor is forced into the supervisor state, and the trace state is forced off. The MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Table 6-4. MC68010 Format Codes ...

Page 97

... If external logic indicates a bus error, the interrupt is considered spurious, and the generated vector number references the spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the format/offset word (MC68010 only), program counter, and status 6-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE MOTOROLA ...

Page 98

... The TRAPV and CHK instructions force an exception if the user program detects a run-time error, which may be an arithmetic overflow or a subscript out of bounds. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6- 13 ...

Page 99

... M68000-Family-compatible microprocessors. The patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer use (as the take illegal instruction trap (ILLEGAL) instruction). ...

Page 100

... As an extreme illustration of these rules, consider the arrival of an interrupt during the execution of a TRAP instruction while tracing is enabled. First, the trap exception is processed, then the trace exception, and finally the interrupt exception. Instruction execution resumes in the interrupt handler routine. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL MOVE USP OR Immediate to SR ...

Page 101

... If a bus error occurs during the exception processing for a bus error, an address error reset, the processor halts and all processing ceases. This halt simplifies the detection of a catastrophic system failure, since the processor removes itself from the system to 6-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 102

... This additional information describes the internal state of the processor at the time of the bus error and is reloaded by the RTE instruction to continue the instruction that caused the error. Figure 6-8 shows the order of the stacked information. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 12 11 ...

Page 103

... NOTE: The stack pointer is decremented by 29 words, although only 26 words of information are actually written to memory. The three additional words are reserved for future use by Motorola. . Figure 6-8. Exception Stack Order (Bus and Address Error) The value of the saved program counter does not necessarily point to the instruction that was executing when the bus error occurred, but may be advanced by as many as five words ...

Page 104

... Read/write flag; 0=write, 1=read FC — The function code used during the faulted access * — These bits are reserved for future use by Motorola and will be zero when written by the MC68010. Figure 6-9. Special Status Word Format 6.3.10 Address Error An address error exception occurs when the processor attempts to access a word or long- word operand or an instruction at an odd address ...

Page 105

... After this read, the processor must be able to load the remaining data without receiving a bus error; therefore bus error occurs on any of the remaining stack reads, the error becomes a double bus fault, and the MC68010 enters the halted state. 6-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 106

... The totals include fetching any extension words, computing the address, and fetching the memory operand. The total number of clock periods, the number of read cycles, and the number of write cycles (zero for all effective address calculations) are shown in the previously described format. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL n(r/w) NOTE ...

Page 107

... An) 20(5/0) 20(5/ An, Xn)* 22(5/0) 22(5/0) (xxx).W 20(5/0) 20(5/0) (xxx).L 28(7/0) 28(7/ PC) 20(5/0) 20(5/ PC, Xn)* 22(5/0) 22(5/0) #<data> 16(4/0) 16(4/0) *The size of the index register (Xn) does not affect execution time. 7-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Register Memory Destination (An) (An)+ –(An An) 12(2/1) 12(2/1) 12(2/1) 20(4/1) 12(2/1) 12(2/1) 12(2/1) 20(4/1) 16(3/1) 16(3/1) 16(3/1) 24(5/1) 16(3/1) 16(3/1) 16(3/1) 24(5/1) 18(3/1) 18(3/1) 18(3/1) 26(5/1) 24(5/1) 24(5/1) 24(5/1) 32(7/1) 26(5/1) 26(5/1) 26(5/1) 34(7/1) 24(5/1) 24(5/1) 24(5/1) 32(7/1) 32(7/1) 32(7/1) 32(7/1) 40(9/1) 24(5/1) 24(5/1) 24(5/1) 32(7/1) 26(5/1) 26(5/1) 26(5/1) 34(7/1) 20(4/1) 20(4/1) 20(4/1) 28(6/1) Byte Word Long 0(0/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 0(0/0) 4(1/0) 8(2/0) 16(4/0) 4(1/0) 8(2/0) 16(4/0) 6(1/0) 10(2/0) 18(4/0) 12(3/0) 16(4/0) 24(6/0) 14(3/0) 18(4/0) 26(6/0) 12(3/0) 16(4/0) 24(6/0) 20(5/0) 24(6/0) 32(8/0) 12(3/0) 16(3/0) 24(6/0) 14(3/0) 18(4/0) 26(6/0) 8(2/0) 8(2/0) 16(4/ An, Xn)* (xxx).W 22(4/1) 20(4/1) 22(4/1) 20(4/1) 26(5/1) 24(5/1) 26(5/1) 24(5/1) 28(5/1) 26(5/1) 34(7/1) 32(7/1) 36(7/1) 34(7/1) 34(7/1) 32(7/1) 42(9/1) 40(9/1) 34(7/1) 32(7/1) 36(7/1) 34(7/1) 30(6/1) 28(6/1) MOTOROLA (xxx).L 28(6/1) 28(6/1) 32(7/1) 32(7/1) 34(7/1) 40(9/1) 42(9/1) 40(9/1) 48(11/1) 40(9/1) 42(9/1) 36(8/1) ...

Page 108

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Destination (An) (An)+ – ...

Page 109

... Long — Byte — Word 10(2/0)+ Long 10(2/0)+ — — — — Byte, — Word, — Long — — — — — Byte, — Word — Long — Byte, Word 12(2/0)+ Long 10(2/0)+** op<ea> Dn, <M> 8(2/0)+ 12(2/1)+ 8(2/0)+ 16(2/2)+ 10(2/0)+** 24(2/4)+ 8(2/0)+ 12(2/1)+ 8(2/0)+ 16(2/2)+ 10(2/0)+** 24(2/4)+ 8(2/0)+ — 8(2/0)+ — 10(2/0)+ — 162(2/0)+* — 144(2/0)+* — 8(2/0)+*** 12(2/1)+ 8(2/0)+*** 16(2/2)+ 12(2/0)+*** 24(2/4)+ 74(2/0)+* — 74(2/0)+* — 8(2/0)+ 12(2/1)+ 8(2/0)+ 16(2/2)+ 10(2/0)+** 24(2/4)+ 8(2/0)+ 12(2/1)+ 8(2/0)+ 16(2/2)+ 10(2/0)+** 24(2/4)+ MOTOROLA ...

Page 110

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Size ...

Page 111

... Word 8(2/0) Long 10(2/0) Byte 8(2/0) Word 8(2/0) Long 10(2/0) Byte 8(2/0) Word 8(2/0) Long 10(2/0) Byte, False 8(2/0) Byte, True 10(2/0) Byte 8(2/0) Byte 8(2/0) Word 8(2/0) Long 8(2/0) Size Register Byte 10+2n (2/0) Word 10+2n (2/0) Long 12+n2 (2/0) Byte 10+2n (2/0) Word 10+2n (2/0) Long 12+n2 (2/0) Byte 10+2n (2/0) Word 10+2n (2/0) Long 12+n2 (2/0) Byte 10+2n (2/0) Word 10+2n (2/0) Long 12+n2 (2/0) Memory 12(2/1)+ 16(2/2)+ 24(2/4)+ 12(2/1)+ 12(2/1)+ 16(2/2)+ 24(2/4)+ 12(2/1)+ 16(2/2)+ 24(2/4)+ 12(2/1)+ 16(2/2)+ 24(2/4)+ 12(2/1)+ 12(2/1)+ 14(2/1)+ 8(2/0)+ 8(2/0)+ 8(2/0)+ Memory — 16(2/2)+ — — 16(2/2)+ — — 16(2/2)+ — — 16(2/2)+ — MOTOROLA ...

Page 112

... Table 7-10. Conditional Instruction Execution Times Instruction Bcc BRA BSR DBcc CHK TRAP TRAPV +Add effective address calculation time for word operand. * Indicates maximum base value. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Dynamic Register Memory — 12(2/1)+ 12(2/0)* — — 12(2/1)+ 14(2/0)* — ...

Page 113

... PC PC, Xn)* 24 (6/0) 18 (4/0) 22 (4/0) 40 (6/4) 34 (4/4) 32 (4/4) 24 (6/0) 16 (4/0) 20 (4/0) 40 (6/4) 32 (4/4) 36 (4/4) 40+8n 32+8n 34+8n (10+2n/0) (8+2n/0) (8+2n/0) 40+16n 32+16n 34+16n (8+4n/0) (8+4n/0) (8+4n/0) 32+8n — — (8/2n) — — 32+16n — — (6/4n) — — MOTOROLA ...

Page 114

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Execution Times Size ...

Page 115

... The number of clock 7-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Register 32(6/0) 32(6/0) 32(6/0) 32(6/0) 10(2/0) 8(2/0) 32(4/4) 18(4/0) 18(4/0) 10(2/0) 8(2/0) 8(2/0) 8(2/0) 32(6/0) 32(6/0) 136(2/0) 40(10/0) 40(10/0) 32(8/0) 4(0/0) 8(2/0) 8(2/0) 24(6/0) Size Register Memory Word 24(4/2) Long 32(4/4) Memory — — — — — — — 18(4/0)+ 18(4/0)+ 16(2/2)+ — — — — — — — — — — — — — Memory Register 24(6/0) 32(8/0) MOTOROLA ...

Page 116

... Privilege Violation RESET ** Trace TRAP Instruction TRAPV Instruction + Add effective address calculation time. ** Indicates the time from when RESET and HALT are first MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Table 7-15. Exception Processing Execution Times Exception sampled as negated to when instruction execution starts. Periods ...

Page 117

... The total includes fetching any extension words, computing the address, and fetching the memory operand. The total number of clock periods, the number of read cycles, and the number of write cycles (zero for all effective address calculations) are shown in the previously described format. MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL n(r/w) NOTE ...

Page 118

... An) 12(3/0) 12(3/ An, Xn)* 14(3/0) 14(3/0) (xxx).W 12(3/0) 12(3/0) (xxx).L 16(4/0) 16(4/ PC) 12(3/0) 12(3/ PC, Xn)* 14(3/0) 14(3/0) #<data> 8(2/0) 8(2/0) *The size of the index register (Xn) does not affect execution time. 8-2 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL Register Memory Destination (An) (An)+ –(An An) 8(1/1) 8(1/1) 8(1/1) 12(2/1) 8(1/1) 8(1/1) 8(1/1) 12(2/1) 12(2/1) 12(2/1) 12(2/1) 16(3/1) 12(2/1) 12(2/1) 12(2/1) 16(3/1) 14(2/1) 14(2/1) 14(2/1) 18(3/1) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 18(3/1) 18(3/1) 18(3/1) 22(4/1) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 20(4/1) 20(4/1) 20(4/1) 24(5/1) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 18(3/1) 18(3/1) 18(3/1) 22(4/1) 12(2/1) 12(2/1) 12(2/1) 16(3/1) Byte, Word Long 0(0/0) 0(0/0) 0(0/0) 0(0/0) 4(1/0) 8(2/0) 4(1/0) 8(2/0) 6(1/0) 10(2/0) 8(2/0) 12(3/0) 10(2/0) 14(3/0) 8(2/0) 12(3/0) 12(3/0) 16(4/0) 8(2/0) 12(3/0) 10(2/0) 14(3/0) 4(1/0) 8(2/ An, Xn)* (xxx).W (xxx).L 14(2/1) 12(2/1) 16(3/1) 14(2/1) 12(2/1) 16(3/1) 18(3/1) 16(3/1) 20(4/1) 18(3/1) 16(3/1) 20(4/1) 20(3/1) 18(3/1) 22(4/1) 22(4/1) 20(4/1) 24(5/1) 24(4/1) 22(4/1) 26(5/1) 22(4/1) 20(4/1) 24(5/1) 28(6/1) 26(5/1) 24(5/1) 24(5/1) 22(4/1) 20(4/1) 24(4/1) 22(4/1) 26(5/1) 18(3/1) 16(3/1) 20(4/1) MOTOROLA ...

Page 119

... In Table 8-4, the following notation applies: An — Address register operand Dn — Data register operand ea — An operand specified by an effective address M — Memory effective address operand MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL Destination (An) (An)+ –(An An) ...

Page 120

... An — Address register operand M — Memory operand 8-4 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL Size op<ea>, An† 8(1/0)+ Long 6(1/0)+** — Long — 6(1/0)+ Long 6(1/0)+ — — — — — Long — — — — — — Long — 8(1/0)+ Long 6(1/0)+** op<ea> Dn, <M> 4(1/0)+ 8(1/1)+ 6(1/0)+** 12(1/2)+ 4(1/0)+ 8(1/1)+ 6(1/0)+** 12(1/2)+ 4(1/0)+ — 6(1/0)+ — 158(1/0)+* — 140(1/0)+* — 4(1/0)*** 8(1/1)+ 8(1/0)*** 12(1/2)+ 70(1/0)+* — 70(1/0)+* — 4(1/0)+ 8(1/1)+ 6(1/0)+** 12(1/2)+ 4(1/0)+ 8(1/1)+ 6(1/0)+** 12(1/2)+ MOTOROLA ...

Page 121

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL Size ...

Page 122

... Byte, Word 4(1/0) Long 6(1/0) Byte 6(1/0) Byte, Word 4(1/0) Long 6(1/0) Byte, Word 4(1/0) Long 6(1/0) Byte, Word 4(1/0) Long 6(1/0) Byte, False 4(1/0) Byte, True 6(1/0) Byte 4(1/0) Byte, Word 4(1/0) Long 4(1/0) Size Register Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Memory 8(1/1)+ 12(1/2)+ 8(1/1)+ 8(1/1)+ 12(1/2)+ 8(1/1)+ 12(1/2)+ 8(1/1)+ 12(1/2)+ 8(1/1)+ 8(1/1)+ 14(2/1)+ 4(1/0)+ 4(1/0)+ Memory 8(1/1)+ — 8(1/1)+ — 8(1/1)+ — 8(1/1)+ — MOTOROLA ...

Page 123

... Table 8-9. Conditional Instruction Execution Times Instruction Bcc BRA BSR DBcc cc false, Count Not Expired MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL Dynamic Register Memory — 8(1/1)+ 8(1/0)* — ...

Page 124

... Dn — Data register operand M — Memory operand 8-8 MC68000 8-/16-/32-MICROPROCESSORS UISER'S MANUAL –(An ,An ,An,Xn)+ (xxx).W — 10 (2/0) 14 (3/0) 10 (2/0) — 18 (2/2) 22 (2/2) 18 (2/2) — 8(2/0) 12 (2/0) 8(2/0) — 16 (2/2) 20 (2/2) 16 (2/2) — 16+4n 18+4n 16+4n (4+n/0) (4+n/0) (4+n/0) — 16+8n 18+8n 16+8n (4+2n/0) (4+2n/0) (4+2n/0) 8+4n 12+4n 14+4n 12+4n (2/n) (3/n) (3/n) (3/n) 8+8n 12+8n 14+8n 12+8n (2/2n) (3/2n) (3/2n) (3/2n) (xxx). PC PC, Xn)* 12 (3/0) 10 (2/0) 14 (3/0) 20 (3/2) 18 (2/2) 22 (2/2) 12 (3/0) 8(2/0) 12 (2/0) 20 (3/2) 16 (2/2) 20 (2/2) 20+4n 16+4n 18+4n (4+n/0) (5+n/0) (4n/0) 20+8n 16+8n 18+8n (5+2n/0) (4+2n/0) (4+2n/0) 16+4n — — (4/n) — — 16+8n — — (4/2n) — — MOTOROLA ...

Page 125

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL Execution Times Size ...

Page 126

... Size Register Memory Word 16(2/2) Long 24(2/4) Memory — — — — — — — 8(1/1)+ 12(1/0)+ 12(2/0)+ — — — — — — — — — — — — — — — Memory Register 16(4/0) 24(6/0) MOTOROLA ...

Page 127

... Trace TRAP Instruction TRAPV Instruction + Add effective address calculation time. * The interrupt acknowledge cycle is assumed to take ** Indicates the time from when RESET and HALT are first MOTOROLA MC68000 8-/16-/32-MICROPROCESSORS USER’S MANUAL Table 8-14. Exception Processing Execution Times Exception four clock periods. ...

Page 128

... The bus is idle for two clock periods during which the processor completes the internal operations required for the instructions. The total number of clock periods (n) includes instruction fetch and all applicable operand fetches and stores. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL n(r/w) NOTE ...

Page 129

... M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Fetch Register 0(0/0) 0(0/0) Memory 4(1/0) 4(1/0) 6(1/0) 8(2/0) 10(2/0) 8(2/0) 12(3/0) 8(2/0) 10(2/0) 4(1/0) Byte, Word Long No Fetch Fetch No Fetch — 0(0/0) — 0(0/0) 2(0/0) 8(2/0) 4(0/0) 8(2/0) 4(0/0) 10(2/0) 4(0/0) 12(3/0) 8(1/0) 14(3/0) 4(1/0) 12(3/0) 8(2/0) 16(4/0) — 12(3/0) — 14(3/0) — 8(2/0) MOTOROLA — — 2(0/0) 4(0/0) 4(0/0) 4(1/0) 8(1/0) 4(1/0) 8(2/0) — — — ...

Page 130

... Table 9-3. Move Byte and Word Instruction Loop Mode Execution Times Loop Continued Valid Count, cc False Source (An) (An)+ Dn 10(0/1) 10(0/1) An* 10(0/1) 10(0/1) (An) 14(1/1) 14(1/1) (An)+ 14(1/1) 14(1/1) –(An) 16(1/1) 16(1/1) *Word only. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Destination (An) (An)+ –(An An) 8(1/1) 8(1/1) 8(1/1) 12(2/1) 8(1/1) 8(1/1) 8(1/1) 12(2/1) 12(2/1) 12(2/1) 12(2/1) 16(3/1) 12(2/1) 12(2/1) 12(2/1) 16(3/1) ...

Page 131

... An operand specified by an effective address M — Memory effective address operand 9-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Destination (An) (An)+ –(An An) 12(1/2) 12(1/2) 14(1/2) 16(2/2) 12(1/2) 12(1/2) 14(1/2) 16(2/2) 20(3/2) 20(3/2) 20(3/2) 24(4/2) 20(3/2) 20(3/2) 20(3/2) 24(4/2) 22(3/2) 22(3/2) 22(3/2) 26(4/2) 24(4/2) 24(4/2) 24(4/2) 28(5/2) 26(4/2) 26(4/2) 26(4/2) 30(5/2) 28(5/2) 24(4/2) 24(4/2) 24(4/2) 28(5/2) 28(5/2) 28(5/2) 32(6/2) 24(4/2) 24(4/2) 24(4/2) 28(5/2) 26(4/2) 26(4/2) 26(4/2) 30(5/2) 20(3/2) 20(3/2) 20(3/2) 24(4/2) Valid count, cc True Destination –(An) (An) (An)+ — 20(2/2) 20(2/2) — 20(2/2) 20(2/2) 24(2/2) 28(4/2) 28(4/2) 24(2/2) 28(4/2) 28(4/2) 26(2/2) 30(4/2) 30(4/ An, Xn)* (xxx).W (xxx).L 18(2/2) 16(2/2) 20(3/2) 18(2/2) 16(2/2) 20(3/2) 26(4/2) 24(4/2) 28(5/2) 26(4/2) 24(4/2) 28(5/2) 28(4/2) 26(4/2) 30(5/2) 30(5/2) 28(5/2) 32(6/2) 32(5/2) 30(5/2) 34(6/2) 30(5/2) 28(5/2) 32(6/2) 34(6/2) 32(6/2) 36(7/2) 30(5/2) 28(5/2) 32(5/2) 32(5/2) 30(5/2) 34(6/2) 26(4/2) 24(4/2) 28(5/2) Loop Terminated Expired Count –(An) (An) (An)+ –(An) — 18(2/2) 18(2/2) — 18(2/2) 18(2/2) 30(4/2) 24(4/2) 24(4/2) 26(4/2) 30(4/2) 24(4/2) 24(4/2) 26(4/2) 32(4/2) 26(4/2) 26(4/2) 28(4/2) MOTOROLA — — ...

Page 132

... Byte, — Word Long — SUB Byte, 18(1/0) Word Long 22(2/0) *Word or long word only. <ea> may be (An), (An)+, or –(An) only. Add two clock periods to the table value if <ea> is –(An). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Size op<ea>, An*** 8(1/0)+ Long 6(1/0)+ — Long — 6(1/0)+ Long 6(1/0)+ — ...

Page 133

... M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Size 8(2/0) Long 14(3/0) 4(1/0) Long 8(1/0) 8(2/0) Long 14(3/0) 8(2/0) Long 12(3/0) 8(2/0) Long 14(3/0) Long 4(1/0) 8(2/0) Long 14(3/0) 8(2/0) Long 14(3/0) 4(1/0) Long 8(1/ — 12(2/1)+ — 20(3/2)+ 4(1/0)* 8(1/2)+ 8(1/1) 12(1/2)+ — 12(2/1)+ — 20(3/1)+ — 8(2/0)+ — 12(3/0)+ — 12(2/1)+ — 20(3/2)+ — — — 12(2/1)+ — 20(3/2)+ — 12(2/1)+ — 20(3/2)+ 4(1/0)* 8(1/1)+ 8(1/0) 12(1/2)+ MOTOROLA ...

Page 134

... Table 9-10. Clear Instruction Execution Times Size Dn CLR Byte, Word 4(1/0) Long 6(1/0) *The size of the index register (Xn) does not affect execution time. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Execution Times Size Register Byte 6(1/0) Byte, Word 4(1/0) Long ...

Page 135

... Word only. 9-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Valid Count, cc True (An)+ –(An) (An) (An)+ 10(0/1) 12(0/1) 18(2/1) 18(2/1) 14(0/2) 16(0/2) 22(2/2) 22(2/2) 18(1/1) 20(1/1) 24(3/1) 24(3/1) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 16(1/1) 18(2/2) 22(3/1) 22(3/1) 24(2/2) 26(2/2) 30(4/2) 30(4/2) 12(1/0) 14(1/0) 18(3/0) 18(3/0) 18(2/0) 20(2/0) 24(4/0) 24(4/0) Size Register Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Byte, Word 6+2n (1/0) Long 8+2n (1/0) Loop Terminated Expired Count –(An) (An) (An)+ –(An) 20(2/0) 16(2/1) 16(2/1) 18(2/1) 24(2/2) 20(2/2) 20(2/2) 22(2/2) 26(3/1) 22(3/1) 22(3/1) 24(3/1) 24(3/1) 20(3/1) 20(3/1) 22(3/1) 32(4/2) 28(4/2) 28(4/2) 30(4/2) 24(3/1) 20(3/1) 20(3/1) 22(3/1) 32(4/2) 28(4/2) 28(4/2) 30(4/2) 24(3/1) 20(3/1) 20(3/1) 22(3/1) 32(4/2) 28(4/2) 28(4/2) 30(4/2) 20(3/0) 16(3/0) 16(3/0) 18(3/0) 26(4/0) 20(4/0) 20(4/0) 22(4/0) Memory* 8(1/1)+ — 8(1/1)+ — 8(1/1)+ — 8(1/1)+ — MOTOROLA ...

Page 136

... CONDITIONAL INSTRUCTION EXECUTION TIMES Table 9-15 lists the timing data for the conditional instructions. The total number of clock periods, the number of read cycles, and the number of write cycles are shown in the previously described format. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Valid Count cc True (An)+ – ...

Page 137

... Branch Not Taken 6(1/0) 10(2/0) — — — — 10(2/0) 16(3/0) (xxx) W (xxx). PC PC, Xn)* 10 (2/0) 12 (3/0) 10 (2/0) 14 (3/0) 18 (2/2) 20 (3/2) 18 (2/2) 22 (2/2) 8(2/0) 12 (3/0) 8(2/0) 12 (2/0) 16 (2/2) 20 (3/2) 16 (2/2) 20 (2/2) 16+4n 20+4n 16+4n 18+4n (4+n/0) (5+n/0) (4+n/0) (4+n/0) 16+8n 20+8n 16+8n 18+8n (4+2n/0) (5+2n/0) (4+2n/0) (4+2n/0) 12+4n 16+4n — (3/n) (4/n) — 12+8n 16+8n — (3/2n) (4/2n) — 20 (4/0) 24 (5/0) 24 (5/0) 28 (6/0) 20 (3/1) 24 (4/1) 24 (3/2) 28 (4/2) MOTOROLA — — — — ...

Page 138

... The number of clock periods, the number of read cycles, and the number of write cycles, respectively, must be added to those of the effective address calculation where indicated by a plus sign (+). MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Nonlooped Valid Count, ...

Page 139

... MOTOROLA ...

Page 140

... TRAPV Instruction + Add effective address calculation time. * The interrupt acknowledge and breakpoint cycles ** Indicates maximum value. *** Indicates the time from when RESET and HALT MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Table 9-19. Exception Processing Execution Times Exception are assumed to take four clock periods. ...

Page 141

... Commerical Extended "C" Grade Commerical Extended "I" Grade Storage Temperature 10.2 THERMAL CHARACTERISTICS Characteristic Symbol Thermal Resistance Ceramic, Type L/LC Ceramic, Type R/RC Plastic, Type P Plastic, Type FN *Estimated MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL Symbol Value Unit V CC –0 –0 ...

Page 142

... Thus, good thermal management on the part of the user can significantly reduce Substitution for equation 1 results in a lower semiconductor junction temperature. 10-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL that J A approximately equals ; (1) (2) (3) (4) MOTOROLA ...

Page 143

... Figure 10-1. MC68000 Power Dissipation ( Ambient Temperature ( (Not Applicable to MC68HC000/68HC001/68EC000) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL NOTE Therefore, maximum power AMBIENT TEMPERATURE ( 110 125 10-3 ...

Page 144

... Does not apply to the MC68HC000, MC68HC001, and MC68EC000. Values for thermal resistance presented in this manual, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843 “Thermal Resistance Measurement Method for MC68XXX Microcomponent Devices”’ and are provided for design purposes only ...

Page 145

... The measurement of the AC specifications is defined by the waveforms shown in Figure 10-2. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times, and are measured as shown ...

Page 146

... E. Mode select setup time to RESET negated. F. Mode select hold time from RESET negated. Figure 10-2. Drive Levels and Test Points for AC Specifications 10-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL DRIVE TO 2.4 V 1 2.0 V 2.0 VALID V OUTPUT 0 2.0 V 2.4 V VALID INPUT 0.8 V 0 2.0 V 0.8 V 2.0 V 0.8 V MOTOROLA ...

Page 147

... Load Capacitance *With external pullup resistor of 1.1 . **Capacitance is periodically sampled rather than 100% tested. ***During normal operation, instantaneous V CC current requirements may be as high as 1.5 A. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL HALT, RESET AS , A1—A23, D0—D15, FC0—FC2, LDS , R/ W, UDS, VMA AS , A1– ...

Page 148

... P D — 0.13 0.16 0.19 0.26 0. — 20 — 70 — 130 ( See Figure 10-3) 16.67 MHz ** 16 MHz 20 MHZ 12F Min Max Min Max Min Max 8.0 16.7 8.0 16.7 8.0 20.0 60 125 60 125 50 125 27 62.5 27 62.5 21 62.5 27 62.5 27 62.5 21 62.5 — 5 — 5 — 4 — 5 — 5 — 4 MOTOROLA Unit MHz ...

Page 149

... V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 V and 2 Figure 10-3. Clock Input Timing Diagram MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 8 MHz* 10 MHz* Unit ...

Page 150

... MOTOROLA Unit ...

Page 151

... E Output Rise and Fall Time 43 VMA Asserted to E High 44 AS, DS Negated to VPA Negated 45 E Low to Control, Address Bus Invalid (Address Hold Time) 46 BGACK Width Low MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 8 MHz* 10 MHz* 12.5 MHz* Min Max Min Max Min Max 40 — ...

Page 152

... MOTOROLA Unit clks clks clks clks clks ...

Page 153

... The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 V and 2.0 V. Figure 10-4. Read Cycle Timing Diagram (A pplies rocessors E xcept The MC68EC 000) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL S1 S2 ...

Page 154

... S2 (specification #20A). Figure 10-5. Write Cycle Timing Diagram (A pplies Processors E xcept The MC68EC 000) 10-14 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 11A 20A 14A 21A MOTOROLA ...

Page 155

... Either of these events can occur first, depending upon the loading on each signal. Specificaton #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of the E clock. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL = 5.0 Vdc 5%; GND=0 Vdc; T ...

Page 156

... NOTE: This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the best case possible attainable Figure 10-6. MC68000 to M6800 Peripheral Timing Diagram (Best Case) (A pplies Processors E xcept The MC68EC 000) 10-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

Page 157

... The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 5. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 8 MHz* 10 MHz* 12.5 MHz* ...

Page 158

... NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BGACK, BR, DTACK, IPL2-IPL0, and VPA guarantees their recognition at the next falling edge of the clock. Figure 10-7. Bus Arbitration Timing (A pplies Processors E xcept The MC68EC 000) 10-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 37A MOTOROLA ...

Page 159

... FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-8. Bus Arbitration Timing (A pplies rocessors E xcept The MC68EC 000) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 37A 37 ...

Page 160

... NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-9. Bus Arbitration Timing — Idle Bus Case (A pplies Processors E xcept The MC68EC 000) 10-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 37A 57A MOTOROLA ...

Page 161

... NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version Only. Figure 10-10. Bus Arbitration Timing — Active Bus Case (A pplies rocessors E xcept The MC68EC 000) MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 34 47 ...

Page 162

... NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0 MC68008 52-Pin Version only. Figure 10-11. Bus Arbitration Timing — Multiple Bus Request (A pplies Processors E xcept The MC68EC 000) 10-22 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 57A MOTOROLA ...

Page 163

... Power Dissipation Capacitance (Vin=0 V, TA=25 C, Frequency=1 MHz)** Load Capacitance * Currents listed are with no loading. ** Capacitance is periodically sampled rather than 100% tested. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ) H MODE, HALT , RESET AS , A23–A0, D15–D0, FC2–FC0, LDS , R/ W, UDS AS , A23–A0, BG, D15–D0, FC2– ...

Page 164

... MOTOROLA Unit ...

Page 165

... When AS and R/W are equally loaded ( 20;pc), subtract 5 ns from the values given in these columns. 7. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted used in this specification to indicate UDS and LDS . MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 8 MHz 10 MHz 12 ...

Page 166

... The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 V and 2.0 V. Figure 10-12. MC68EC000 Read Cycle Timing Diagram 10-26 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 11A MOTOROLA ...

Page 167

... The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 V and 2 Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A). Figure 10-13. MC68EC000 Write Cycle Timing Diagram MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

Page 168

... MHz 20 MHz Unit Max Min Max Min Max 55 — 50 — — 50 — 3.5 1.5 3.5 1.5 3.5 Clks 3.5 1.5 3.5 1.5 3.5 Clks 55 — 50 — 42 — 1.5 — 1.5 — Clks — 5 — 5 — — 1.5 — 1.5 — Clks — 1 — 1 — Clks MOTOROLA ...

Page 169

... CLK R/W FC2-FC0 A19-A0 D7-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. Figure 10-14. MC68EC000 Bus Arbitration Timing Diagram MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 58A 10-29 ...

Page 170

... This section provides pin assignments and package dimensions for the devices described in this manual. 11.1 PIN ASSIGNMENTS Package 64-Pin Dual-In-Line 68-Terminal Pin Grid Array 64-Lead Quad Pack 68-Lead Quad Flat Pack 52-Lead Quad 48-Pin Dual-In-Line MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 68000 68008 68010 68HC000 68HC001 68EC000 11-1 ...

Page 171

... Figure 11-1. 64-Pin Dual In Line D10 58 D11 57 D12 56 D13 55 D14 54 D15 53 GND 52 A23 51 A22 50 A21 A20 47 A19 46 A18 45 A17 44 A16 43 A15 42 A14 41 A13 40 A12 39 A11 38 A10 MOTOROLA ...

Page 172

... C BGACK BG R/W B DTACK LDS UDS Figure 11-2. 68-Lead Pin Grid Array MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL K MODE BERR IPL0 A8 A10 A11 A14 H E A13 A12 A16 G VMA A15 A17 F HALT A18 ...

Page 173

... MC68EC000 D13 D14 D15 GND GND A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 44 A13 D13 D14 D15 GND A23 A22 A21 V CC A20 52 A19 A18 A17 A16 A15 A14 A13 44 A12 43 MOTOROLA ...

Page 174

... VPA BERR IPL2 IPL1 Figure 11-3. 68-Lead Quad Pack ( A10 A11 A12 A13 A 21 A14 CC V A15 GND A16 A17 A18 MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MC68HC001 MC68008 20 21 Figure 11-4. 52-Lead Quad Pack 61 ...

Page 175

... MC68008 Figure 11-5. 48-Pin Dual In Line FC0 FC1 FC2 IPL2/IPL0 IPL1 BERR VPA E RESET HALT GND CLK BR BG DTACK R MOTOROLA ...

Page 176

... Figure 11-6. 64-Lead Quad Flat Pack 11.2 PACKAGE DIMENSIONS Case Package 740-03 L Suffix 767-02 P Suffix 746-01 LC Suffix 754-01 R and P Suffix 765A-05 RC Suffix 778-02 FN Suffix 779-02 FN Suffix 779-01 FN Suffix 847-01 FC Suffix 840B-01 FU Suffix MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 64 1 MC68EC000 16 17 68000 68008 68010 49 D12 48 ...

Page 177

... C 3.05 4.32 0.120 0.160 D 3.81 0.533 0.015 0.021 .762 1.397 0.030 0.055 F G 2.54 BSC 0.204 0.330 0.008 0.013 J K 2.54 4.19 0.100 0.165 L 15.24 BSC 1.016 1.524 0.040 0.060 N L SUFFIX 746- INCHES MIN MAX 0.100 BSC 0.600 BSC 0 10 MOTOROLA M ...

Page 178

... DIMENSION "A" AND "B" DOES NOT INCLUDE MOLD FLASH, MAXIMUM MOLD FLASH 0.25 (0.010). 4. DIMENSION "L" CENTER OF LEADS WHEN FORMED PARALLEL. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1982. 6. CONTROLLING DIMENSION: INCH. Figure 11-8. Case 767-02—P Suffix MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL ...

Page 179

... T G MILLIMETERS DIM MIN MAX A 80.52 82.04 3.170 3.230 B 22.25 22.96 0.876 0.904 C 3.05 4.32 D 0.38 0.53 .76 F 1.40 G 2.54 BSC J 0.20 0.33 K 2.54 4.19 L 22.61 23.11 0.890 1.02 1. SUFFIX 746- INCHES MIN MAX 0.120 0.160 0.015 0.021 0.030 0.055 0.100 BSC 0.008 0.013 0.100 0.165 0.910 0 10 0.040 0.060 MOTOROLA M ...

Page 180

... DIMENSION B DOES NOT INCLUDEMOLD FLASH. 5. DIMENSION CENTER OF LEADS WHEN FORMED PARALLEL. 6. DIMENSIONING AND TOLERANCING PER ANSI Y14.5, 1982. Figure 11-10. Case 754-01—R and P Suffix MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MILLIMETERS DIM MIN MAX MIN 81 ...

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... Figure 11-11. Case 765A-05—RC Suffix 11-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA ...

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... The last two instructions, a MOVE and a test equal, decrement, and branch (DBEQ), form the loop that moves the block of data. The bus activity required to execute these instructions consists of the following cycles: MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL SOURCE, A0 Load A Pointer To Source Data ...

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... Table A-1 lists the loop mode instructions of the MC68010. Only one-word versions of these instructions can operate in the loop mode. One-word instructions use the three address register indirect modes: (An), (An)+, and –(An). A-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL MOTOROLA ...

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... ASL [W] ASR [W] LSL [W] LSR [W] ROL [W] ROR [W] ROXL [W] ROXR NOTE: [ indicate an operand size of byte, word, or long word. MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL Applicable Addressing Modes (Ay) to (Ax) (Ay) to (Ax)+ (Ay) to –(Ax) (Ay)+ to (Ax) (Ay)+ to –(Ax) –(Ay) to (Ax) –(Ay) to (Ax)+ – ...

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