CY37128 Cypress Semiconductor Corporation., CY37128 Datasheet

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CY37128

Manufacturer Part Number
CY37128
Description
CY371285V, 3.3V, ISR High-Performance CPLDs
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-03007 Rev. *C
Features
Note:
1.
• In-System Reprogrammable™ (ISR™) CMOS CPLDs
• High density
• Simple timing model
• 3.3V and 5V versions
• PCI-compatible
• Programmable bus-hold capabilities on all I/Os
• Intelligent product term allocator provides:
• Flexible clocking
• Consistent package/pinout offering across all densities
• Packages
— JTAG interface for reconfigurability
— Design changes do not cause pinout changes
— Design changes do not cause timing changes
— 32 to 512 macrocells
— 32 to 264 I/O pins
— Five dedicated inputs including four clock pins
— No fanout delays
— No expander delays
— No dedicated vs. I/O pin delays
— No additional delay through PIM
— No penalty for using full 16 product terms
— No delay for steering or sharing product terms
— 0 to 16 product terms to any macrocell
— Product term steering on an individual basis
— Product term sharing among local macrocells
— Four synchronous clocks per device
— Product term clocking
— Clock polarity control per logic block
— Simplifies design migration
— Same pinout for 3.3V and 5.0V devices
— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,
Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V
BGA, and Fine-Pitch BGA packages
[1]
5V, 3.3V, ISR™ High-Performance CPLDs
3901 North First Street
General Description
The Ultra37000™ family of CMOS CPLDs provides a range of
high-density programmable logic solutions with unparalleled
system performance. The Ultra37000 family is designed to
bring the flexibility, ease of use, and performance of the 22V10
to high-density CPLDs. The architecture is based on a number
of logic blocks that are connected by a Programmable Inter-
connect Matrix (PIM). Each logic block features its own
product term array, product term allocator, and 16 macrocells.
The PIM distributes signals from the logic block outputs and all
input pins to the logic block inputs.
All of the Ultra37000 devices are electrically erasable and In-
System Reprogrammable (ISR), which simplifies both design
and manufacturing flows, thereby reducing costs. The ISR
feature provides the ability to reconfigure the devices without
having design changes cause pinout or timing changes. The
Cypress ISR function is implemented through a JTAG-
compliant serial interface. Data is shifted in and out through
the TDI and TDO pins, respectively. Because of the superior
routability and simple timing model of the Ultra37000 devices,
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The
Ultra37000 family features user programmable bus-hold
capabilities on all I/Os.
Ultra37000 5.0V Devices
The Ultra37000 devices operate with a 5V supply and can
support 5V or 3.3V I/O levels. V
capability of interfacing to either a 5V or 3.3V bus. By
connecting the V
on the outputs. If V
meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.
These devices require 5V ISR programming.
Ultra37000V 3.3V Devices
Devices operating with a 3.3V supply require 3.3V on all V
pins, reducing the device’s power consumption. These
devices support 3.3V JEDEC standard CMOS output levels,
and are 5V-tolerant. These devices allow 3.3V ISR
programming.
CC
, PCI V
IH
= 2V.
San Jose
CCO
CCO
pins to 5V the user insures 5V TTL levels
Ultra37000 CPLD Family
is connected to 3.3V the output levels
,
CA 95134
CCO
connections provide the
Revised July 7, 2003
408-943-2600
CCO

Related parts for CY37128

CY37128 Summary of contents

Page 1

Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 512 macrocells — 264 ...

Page 2

... Lead Lead TQFP PLCC CY37032 37 37 CY37064 37 37 CY37128 CY37192 CY37256 CY37384 CY37512 3.3V Selection Guide General Information Device Macrocells CY37032V 32 CY37064V 64 CY37128V 128 CY37192V 192 CY37256V 256 CY37384V 384 CY37512V 512 Document #: 38-03007 Rev. *C Dedicated Inputs I/O Pins 32/64 5 64/128 5 120 5 ...

Page 3

... Device-Package Offering & I/O Count Device CY37032V 37 37 CY37064V CY37128V CY37192V CY37256V CY37384V CY37512V Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations ...

Page 4

FROM PIM PRODUCT TERM ARRAY TO PIM Low-Power Option Each logic block can operate in high-speed mode for critical path performance low-power mode for power conser- vation. The logic block mode is set by ...

Page 5

The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried ...

Page 6

FROM PTM 0 16 PRODUCT TERMS FROM PTM 0 16 PRODUCT TERMS ASYNCHRONOUS BLOCK RESET 4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3) ASYNCHRONOUS 1 ASYNCHRONOUS CLOCK(PTCLK) BLOCK PRESET FROM CLOCK POLARITY MUXES Document #: 38-03007 Rev. *C I/O MACROCELL 0 1 C25 ...

Page 7

... ALL INPUT MACROCELLS C13, C14, C15 OR C16 O TO PIM CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUT COMBINATORIAL SIGNAL REGISTERED SIGNAL D,T,L O Figure 5. Timing Model for CY37128 TO CLOCK MUX IN EACH LOGIC BLOCK OUTPUT OUTPUT Page ...

Page 8

IEEE 1149.1-compliant JTAG The Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR. Boundary Scan The Ultra37000 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure ...

Page 9

Logic Block Diagrams CY37032/CY37032V 16 I/Os I/O I CY37064/CY37064V (100-Lead TQFP) 16 I/Os I/O -I I/Os I/O -I TDI JTAG Tap TCK TDO Controller TMS Document #: 38-03007 Rev. *C Clock/ Input Input ...

Page 10

... Logic Block Diagrams (continued) CY37128/CY37128V (160-lead TQFP) 16 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I CY37192/CY37192V (160-lead TQFP) 10 I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I I/Os I/O –I TDI JTAG Tap TCK TDO Controller TMS Document #: 38-03007 Rev. *C CLOCK ...

Page 11

Logic Block Diagrams (continued) CY37256/CY37256V (256-lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O ...

Page 12

Logic Block Diagrams (continued) CY37384/CY37384V (256-Lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O ...

Page 13

Logic Block Diagrams (continued) CY37512/CY37512V (352-Lead BGA) 12 I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O I I/Os I/O ...

Page 14

Device Characteristics Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature .................................–65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to ...

Page 15

Inductance Parameter Description Conditions L Maximum Pin V IN Inductance MHz [5] Capacitance Parameter Description C Input/Output Capacitance I/O C Clock Signal Capacitance CLK C Dual Function Pins DP [5] Endurance Characteristics Parameter Description N ...

Page 16

Device Electrical Characteristics Parameter Description I Input Bus-Hold HIGH Sustaining BHH Current I Input Bus-Hold LOW Overdrive BHLO Current I Input Bus-Hold HIGH Overdrive BHHO Current [5] Inductance Parameter Description Conditions L Maximum Pin V = 3.3V IN Inductance ...

Page 17

AC Characteristics 3.3V AC Test Loads and Waveforms 295 (COM’L) 393 (MIL) 3.3V OUTPUT 340 (COM’ 453 (MIL) INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT 158 (COM’L) 270 (MIL) OUTPUT [11] Parameter ...

Page 18

Switching Characteristics Over the Operating Range Parameter t Clock or Latch Enable Input HIGH Time WH t Input Register or Latch Set-up Time IS t Input Register or Latch Hold Time IH [13, 14, 15] t Input Register Clock or ...

Page 19

Switching Characteristics Over the Operating Range Parameter JTAG Timing Parameters t Set-up Time from TDI and TMS to TCK S JTAG t Hold Time on TDI and TMS H JTAG t Falling Edge of TCK to TDO CO JTAG f ...

Page 20

Switching Characteristics Over the Operating Range 200 MHz 167 MHz 154 MHz Parameter Operating Frequency Parameters f 200 167 MAX1 f 200 200 MAX2 f 125 125 MAX3 f 167 167 MAX4 Reset/Preset Parameters [13] t ...

Page 21

Switching Waveforms (continued) Registered Output with Synchronous Clocking INPUT SYNCHRONOUS CLOCK REGISTERED OUTPUT REGISTERED OUTPUT SYNCHRONOUS CLOCK Registered Output with Product Term Clocking Input Going Through the Array INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Registered Output with Product Term Clocking ...

Page 22

Switching Waveforms (continued) Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock INPUT REGISTER CLOCK OUTPUT REGISTER CLOCK Document #: 38-03007 Rev PDL ...

Page 23

Switching Waveforms (continued) Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document #: 38-03007 Rev PDL ...

Page 24

Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Document #: 38-03007 Rev. *C Ultra37000 CPLD Family ...

Page 25

Power Consumption Typical 5.0V Power Consumption CY37032 The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37064 ...

Page 26

... Typical 5.0V Power Consumption (continued) CY37128 The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37192 The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. ...

Page 27

Typical 5.0V Power Consumption (continued) CY37256 The typical pattern is a 16-bit up counter, per logic block, with outputs ...

Page 28

Typical 5.0V Power Consumption (continued) CY37512 Typical 3.3V Power Consumption CY37032V ...

Page 29

... The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37128V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. ...

Page 30

Typical 3.3V Power Consumption (continued) CY37192V The typical pattern is a 16-bit up counter, per logic block, with outputs disabled. CY37256V ...

Page 31

Typical 3.3V Power Consumption (continued) CY37384V The typical pattern is ...

Page 32

Pin Configurations I/O JTAG CLK Note: 20. For 3.3V versions (Ultra37000V CCO Document #: 38-03007 Rev. *C 44-pin TQFP (A44) Top View /TCK 5 I/O 2 ...

Page 33

Pin Configurations (continued /TCK I I I CLK / CCO GND 22 ...

Page 34

Pin Configurations (continued) 100 99 98 TCK 1 GND CLK / ...

Page 35

... GND GND CLK I/O I/O I/O I/O I TMS V I/O NC I/O I I/O I/O NC I/O I/O I I/O I/O I/O I/O I/O I 100-ball Fine-Pitch BGA (BB100) for CY37128V Top View I/O I/O I/O I/O I/O I I/O I/O I/O I/O I I/O V I/O I/O I/O I TCK NC I/O I/O I/O I/O ...

Page 36

... CCO Document #: 38-03007 Rev. *C 160-Lead TQFP (A160) / CQFP (U162) for CY37128(V) and CY37256(V) Top View Ultra37000 CPLD Family 120 V CCO 119 I/O 111 118 I/O 110 117 I/O 109 116 I/O /TDI 108 115 I/O 107 114 I/O 106 113 ...

Page 37

Pin Configurations (continued) GND I I TCK 6 I I GND I ...

Page 38

Pin Configurations (continued) GND I/O 24 TCK 7 8 I GND ...

Page 39

Pin Configurations (continued GND I/O NC I/O I/O I I/O I/O I/O I/O I/O I I/O NC I/O I ...

Page 40

Pin Configurations (continued GND GND I/O I GND I/O I/O I I/O I I/O I/O I I/O I/O I/O I/O 35 ...

Page 41

Pin Configurations (continued GND GND I/O I/O I/O I/O I GND NC I/O I/O I/O I/O I I/O I/O ...

Page 42

Pin Configurations (continued) A GND GND NC I/O I GND GND GND NC I GND GND GND I I/O NC GND I/O I I/O I/O I/O I/O ...

Page 43

Ordering Information Cypress Semiconductor ID Family Type 37 = Ultra37000 Family Macrocell Density Macrocells 256 = 256 Macrocells 64 ...

Page 44

... CY37064P44-125JI CY37064P84-125JI CY37064P100-125AI 5962-9951901QYA 128 167 CY37128P84-167JC CY37128P100-167AC CY37128P160-167AC 125 CY37128P84-125JC CY37128P100-125AC CY37128P160-125AC CY37128P84-125JI CY37128P100-125AI CY37128P160-125AI 5962-9952102QYA 100 CY37128P84-100JC CY37128P100-100AC CY37128P160-100AC CY37128P84-100JI CY37128P100-100AI CY37128P160-100AI 5962-9952101QYA 192 154 CY37192P160-154AC 125 CY37192P160-125AC CY37192P160-125AI 83 CY37192P160-83AC CY37192P160-83AI Document #: 38-03007 Rev. *C Ultra37000 CPLD Family Package Name ...

Page 45

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 256 154 CY37256P160-154AC CY37256P208-154NC CY37256P256-154BGC 125 CY37256P160-125AC CY37256P208-125NC CY37256P256-125BGC CY37256P160-125AI CY37256P208-125NI CY37256P256-125BGI 5962-9952302QZC 83 CY37256P160-83AC CY37256P208-83NC CY37256P256-83BGC CY37256P160-83AI CY37256P208-83NI CY37256P256-83BGI 5962-9952301QZC 384 125 CY37384P208-125NC CY37384P256-125BGC 83 CY37384P208-83NC CY37384P256-83BGC CY37384P208-83NI CY37384P256-83BGI ...

Page 46

... CY37064VP48-100BAC CY37064VP100-100AC CY37064VP100-100BBC CY37064VP44-100AI CY37064VP48-100BAI CY37064VP100-100BBI CY37064VP100-100AI 5962-9952001QYA 128 125 CY37128VP100-125AC CY37128VP100-125BBC CY37128VP160-125AC 83 CY37128VP100-83AC CY37128VP100-83BBC CY37128VP160-83AC CY37128VP100-83AI CY37128VP100-83BBI CY37128VP160-83AI 5962-9952201QYA 192 100 CY37192VP160-100AC 66 CY37192VP160-66AC CY37192VP160-66AI Document #: 38-03007 Rev. *C Ultra37000 CPLD Family Package Name Package Type A44 44-Lead Thin Quad Flat Pack ...

Page 47

Ordering Information (continued) Macro- Speed cells (MHz) Ordering Code 256 100 CY37256VP160-100AC CY37256VP208-100NC CY37256VP256-100BGC CY37256VP256-100BBC 66 CY37256VP160-66AC CY37256VP208-66NC CY37256VP256-66BGC CY37256VP256-66BBC CY37256VP160-66AI CY37256VP256-66BGI CY37256VP256-66BBI 5962-9952401QZC 384 83 CY37384VP208-83NC CY37384VP256-83BGC 66 CY37384VP208-66NC CY37384VP256-66BGC CY37384VP208-66NI CY37384VP256-66BGI 512 83 CY37512VP208-83NC CY37512VP256-83BGC CY37512VP352-83BGC CY37512VP400-83BBC ...

Page 48

Package Diagrams Document #: 38-03007 Rev. *C 44-lead Thin Plastic Quad Flat Pack A44 44-Lead Plastic Leaded Chip Carrier J67 Ultra37000 CPLD Family 51-85064-*B 51-85003-*A Page ...

Page 49

Package Diagrams (continued) Document #: 38-03007 Rev. *C 44-Pin Ceramic Leaded Chip Carrier Y67 Ultra37000 CPLD Family 51-80014-** Page ...

Page 50

Package Diagrams (continued) 48-Ball (7 7 1.2 mm, 0.80 pitch) Thin BGA BA48D Document #: 38-03007 Rev. *C 84-Lead Plastic Leaded Chip Carrier J83 Ultra37000 CPLD Family 51-85109-*C 51-85006-*A Page ...

Page 51

Package Diagrams (continued) Document #: 38-03007 Rev. *C 84-Pin Ceramic Leaded Chip Carrier Y84 Ultra37000 CPLD Family 51-80095-*A Page ...

Page 52

Package Diagrams (continued) Document #: 38-03007 Rev. *C 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Ultra37000 CPLD Family 51-85048-*B Page ...

Page 53

Package Diagrams (continued) 100-Ball Thin Ball Grid Array ( 1.4 mm) BB100 Document #: 38-03007 Rev. *C Ultra37000 CPLD Family 51-8 510 7-*B Page ...

Page 54

Package Diagrams (continued) 160-Pin Thin Plastic Quad Flat Pack ( 1.4 mm) (TQFP) A160 Document #: 38-03007 Rev. *C Ultra37000 CPLD Family 51-85049-*B Page ...

Page 55

Package Diagrams (continued) Document #: 38-03007 Rev. *C 160-Lead Ceramic Quad Flatpack (Cavity Up) U162 Ultra37000 CPLD Family 51-80106-** Page ...

Page 56

Package Diagrams (continued) Document #: 38-03007 Rev. *C 208-Lead Plastic Quad Flatpack N208 Ultra37000 CPLD Family 51-85069-*B Page ...

Page 57

Package Diagrams (continued) 208-Lead Ceramic Quad Flatpack (Cavity Up) U208 Document #: 38-03007 Rev. *C Ultra37000 CPLD Family 51-80105-*A Page ...

Page 58

Package Diagrams (continued) Document #: 38-03007 Rev. *C 256-Ball FBGA ( mm) BB256 Ultra37000 CPLD Family 5 1-85 108 -*C Page ...

Page 59

Package Diagrams (continued) Document #: 38-03007 Rev. *C 388-Lead PBGA ( 2.33 mm) BG388 Ultra37000 CPLD Family 5 1-85 103 -*C Page ...

Page 60

Package Diagrams (continued) Warp is a registered trademark, and In-System Reprogrammable, ISR, Warp Professional, Warp Enterprise, and Ultra37000 are trademarks, of Cypress Semiconductor.ViewDraw and SpeedWave are trademarks of ViewLogic. Windows is a registered trade- mark of Microsoft Corporation. All product ...

Page 61

Addendum 3.3V Operating Range (CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143B Range Commercial Document #: 38-03007 Rev. *C © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of ...

Page 62

... Document #: 38-03007 Rev. *C Orig. of Change SZV Change from Spec number: 38-00475 to 38-03007 OOR Updated 3.3V V requirements for –144 speeds CC Added an Addendum TEH Changed pinout for CY37128V BB100 package HOM Obsoleted following 3.3V PLCC packaged devices: CY37032VP44-143JC CY37032VP44-100JC CY37032VP44-100JI CY37064VP44-143JC CY37064VP84-143JC CY37064VP44-100JC CY37064VP84-100JC CY37064VP44-100JI ...

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