AM79C973 Advanced Micro Devices, AM79C973 Datasheet

no-image

AM79C973

Manufacturer Part Number
AM79C973
Description
AM79C973PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
Manufacturer
Advanced Micro Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM79C973AKC/W
Manufacturer:
AMD
Quantity:
180
Part Number:
AM79C973AVC
Manufacturer:
AMD
Quantity:
8 000
Part Number:
AM79C973BKC
Manufacturer:
AMD
Quantity:
120
Part Number:
AM79C973BKC
Manufacturer:
AMD
Quantity:
1 000
Part Number:
AM79C973BKC
Manufacturer:
AMD
Quantity:
1 000
Part Number:
AM79C973BKC
Manufacturer:
AMD
Quantity:
1 000
Part Number:
AM79C973BKCW
Manufacturer:
AMD
Quantity:
2 144
Part Number:
AM79C973BKCW
Manufacturer:
AMD
Quantity:
1 000
Part Number:
AM79C973BKD
Manufacturer:
AD
Quantity:
101
Part Number:
AM79C973BKD/W
Manufacturer:
TI
Quantity:
3 400
Company:
Part Number:
AM79C973BVC
Manufacturer:
AMD
Quantity:
695
Am79C973/Am79C975
PCnet™-FAST III
Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
DISTINCTIVE CHARACTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Single-chip PCI-to-Wire Fast Ethernet controller
— 32-bit glueless PCI host interface
— Supports PCI clock frequency from DC to
— Supports network operation with PCI clock
— High performance bus mastering
— PCI specification revision 2.2 compliant
— Supports PCI Subsystem/Subvendor ID/
— Supports both PCI 5.0 V and 3.3 V signaling
— Plug and Play compatible
— Big endian and little endian byte alignments
Fully Integrated 10/100 Mbps Physical Layer
Interface (PHY)
— Conforms to IEEE 802.3 standard for
— Integrated 10BASE-T transceiver with on-
— Fully integrated MLT-3 encoder/decoder for
— Provides a PECL interface for 100BASE-FX
— Full-duplex capability for 10BASE-T and
— IEEE 802.3u Auto-Negotiation between 10
Dual-speed CSMA/CD (10 Mbps and 100 Mbps)
Media Access Controller (MAC) compliant with
IEEE/ANSI 802.3 and Blue Book Ethernet
standards
33 MHz independent of network clock
from 15 MHz to 33 MHz
architecture with integrated Direct Memory
Access (DMA) Buffer Management Unit for
low CPU and bus utilization
Vendor ID programming through the
EEPROM interface
environments
supported
10BASE-T, 100BASE-TX, and 100BASE-FX
interfaces
chip filtering
100BASE-TX
fiber implementations
100BASE-TX
Mbps and 100 Mbps, half- and full-duplex op-
eration
PRELIMINARY
R f
t AMD’ W b it (
d
) f
Supports PC98/PC99 and Wired for
Management baseline specifications
— Full OnNow support including pattern
— Implements AMD’s patented Magic Packet™
— Magic Packet mode and the physical address
— Supports PCI Bus Power Management
— Supports Advanced Configuration and
— Supports Network Device Class Power
Serial Management Interface enables remote
alerting of system management events
— Inter-IC (I
— System Management Bus (SMBus)
— Optional interrupt pin simplifies software
Large independent internal TX and RX FIFOs
— Programmable FIFO watermarks for both TX
— RX frame queuing for high latency PCI bus
— Programmable allocation of buffer space
EEPROM interface supports jumperless design
and provides through-chip programming
— Supports extensive programmability of
Supports up to 1 megabyte (Mbyte) optional
Boot PROM and Flash for diskless node
application
Extensive programmable internal/external
loopback capabilities
Extensive programmable LED status support
th l t t i f
matching and link status wake-up events
technology for remote wake-up & power-on
loaded from EEPROM at power up without
requiring PCI clock
Interface Specification Revision 1.1
Power Interface (ACPI) Specification Version
1.0
Management Specification Version 1.0a
compliant signaling interface and register
access protocol
interface
and RX operations
host operation
between RX and TX queues
device operation through EEPROM mapping
2
C) compliant electrical interface
Publication# 21510
Issue Date: August 2000
ti
Rev: E Amendment/0

Related parts for AM79C973

AM79C973 Summary of contents

Page 1

... PRELIMINARY Am79C973/Am79C975 PCnet™-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY DISTINCTIVE CHARACTERISTICS Single-chip PCI-to-Wire Fast Ethernet controller — 32-bit glueless PCI host interface — Supports PCI clock frequency from MHz independent of network clock — Supports network operation with PCI clock from 15 MHz to 33 MHz — ...

Page 2

... Transmit FIFO and a large Receive FIFO, and an IEEE 802.3-compliant 10/100 Mbps PHY. The integrated 10/100 PHY unit of the Am79C973 and Am79C975 controllers implement the complete physi- cal layer for 10BASE-T and the Physical Coding Sub- ...

Page 3

... PCnet-FAST+™ (Am79C972). The Buffer Management Unit supports the LANCE and PCnet descriptor software models. The Am79C973 and Am79C975 controllers are ideally suited for LAN on the motherboard, network adapter card, and embedded designs available in a 160- pin Plastic Quad Flat Pack (PQFP) package and also in a 176-pin Thin Quad Flat Pack (TQFP) package for form factor sensitive designs ...

Page 4

... FIFO Network Port Manager Serial OnNow Management Power Interface Unit Management Unit MCLOCK PME MDATA PG RWU MIRQ WUMI Am79C973/Am79C975 MIIRXFRTGE MIIRXFRTGD SFBD EAR RXD[3:0],TXD[3:0] MDIO MDC XTAL1 XTAL2 Clock Reference 10/100 PHY Core Transmit MLT3 Block (100 BASE-TX) MII Interface ...

Page 5

... BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RELATED AMD PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CONNECTION DIAGRAM (PQR160) - AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CONNECTION DIAGRAM (PQL176) AM79C973 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CONNECTION DIAGRAM (PQR160) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CONNECTION DIAGRAM (PQL176) - AM79C975 . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PIN DESIGNATIONS (PQR160) (Am79C973/Am79C975 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PIN DESIGNATIONS (PQL176) (Am79C973/Am79C975 Listed By Pin Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PIN DESIGNATIONS (PQR160, PQL176) ...

Page 6

... Miscellaneous Loopback Features Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Full-Duplex Link Status LED Support 10/100 PHY Unit Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 100BASE-TX Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 100BASE-FX (Fiber Interface 10BASE-T Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 PHY/MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Receive Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Internal PHY Loopback Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C973/Am79C975 ...

Page 7

... Power on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Software Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PCI Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PCI Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PCI Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 PCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Am79C973/Am79C975 7 ...

Page 8

... PCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 RAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 RAP: Register Address Port 123 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 CSR0: Am79C973/Am79C975 Controller Status and Control Register . . . . . . 123 CSR1: Initialization Block Address 126 CSR2: Initialization Block Address 126 CSR3: Interrupt Masks and Deferral Control . . . . . . . . . . . . . . . . . . . . . . . . . . 126 CSR4: Test and Features Control ...

Page 9

... CSR84: DMA Address Register Lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CSR85: DMA Address Register Upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CSR86: Buffer Byte Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 CSR88: Chip ID Register Lower 152 CSR89: Chip ID Register Upper 153 CSR92: Ring Length Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 CSR100: Bus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 CSR112: Missed Frame Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Am79C973/Am79C975 9 ...

Page 10

... BCR44: PCI DATA Register Seven (DATA7) Alias Register . . . . . . . . . . . . . . 191 BCR45: OnNow Pattern Matching Register 191 BCR46: OnNow Pattern Matching Register 191 BCR47: OnNow Pattern Matching Register 192 BCR48-BCR55: Reserved Locations for Am79C975 . . . . . . . . . . . . . . . . . . . . 192 PHY Management Registers (ANRs 192 Am79C973/Am79C975 ...

Page 11

... Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 PHY Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 PROGRAMMABLE REGISTER SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Am79C973/Am79C975 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . 220 Am79C973/Am79C975 Bus Configuration Registers . . . . . . . . . . . . . . . . . . . . . . 222 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SWITCHING CHARACTERISTICS: BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . 227 SWITCHING CHARACTERISTICS: EXTERNAL ADDRESS DETECTION INTERFACE ...

Page 12

... Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Outline of LAPP Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 LAPP Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 LAPP Rules for Parsing Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Some Examples of LAPP Descriptor Interaction . . . . . . . . . . . . . . . . . . . . . . . . . 289 Buffer Size Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 An Alternative LAPP Flow: Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . 291 INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Am79C973/Am79C975 ...

Page 13

... Figure 44. Flash Read from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 45. Flash Write from Expansion Bus Data Port . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 46. Block Diagram No SRAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 47. Block Diagram Low Latency Receive Configuration . . . . . . . . . . . . . . . . . . 97 Figure 48. LED Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Am79C973/Am79C975 ...

Page 14

... Figure 87. Receive Frame Tag Timing with Media Independent Interface . . . . . . . . . 282 Figure 88. LAPP Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 89. LAPP 3 Buffer Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 90. LAPP Timeline for Two-Interrupt Method . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Figure 91. LAPP 3 Buffer Grouping for Two-interrupt Method . . . . . . . . . . . . . . . . . . 293 Am79C973/Am79C975 240 249 250 268 281 ...

Page 15

... Table 25. Software Styles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 26. Receive Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Table 27. Transmit Start Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 28. Transmit Watermark Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 29. BCR Registers (Am79C973 159 Table 30. BCR Registers (Am79C975 161 Table 31. ROMTNG Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 32. Interface Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Table 33. Software Styles 179 Table 34 ...

Page 16

... Table 72. MII Management Status Register (Register 275 Table 73. Auto-Negotiation Advertisement Register (Register 276 Table 74. Technology Ability Field Bit Assignments 276 Table 75. Auto-Negotiation Link Partner Ability Register (Register 5) - Base Page Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Table 76. Registers for Alternative Initialization Method (Note 283 Am79C973/Am79C975 ...

Page 17

... Am79C982 Basic Integrated Multiport Repeater (bIMR) Am79C983 Integrated Multiport Repeater 2 (IMR2™) Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™) Am79C987 Hardware Implemented Management Information Base (HIMIB™ Am79C973/Am79C975 17 ...

Page 18

... AD15 32 VSS 33 AD14 34 AD13 35 VSSB 36 AD12 37 AD11 38 VDD_PCI 39 AD10 40 AD9 Pin 1 is marked for orientation Am79C973 Am79C973 PQR160 Am79C973/Am79C975 120 EEDO/LED3/MIIRXFRTGD 119 DVSSP 118 DVDDP 117 RX- 116 DVDDRX 115 RX+ 114 SDI- 113 DVSSX 112 SDI+ ...

Page 19

... AD13 37 VSSB 38 AD12 39 AD11 40 VDD_PCI 41 AD10 42 AD9 Pin 1 is marked for orientation Am79C973 Am79C973 PQL176 Am79C973/Am79C975 NC 132 NC 131 EEDO/LED3/MIIRXFRTGD 130 DVSSP 129 DVDDP 128 RX- 127 DVDDRX 126 RX+ 125 SDI- 124 DVSSX 123 SDI+ 122 ...

Page 20

... AD14 34 AD13 35 VSSB 36 AD12 37 AD11 38 VDD_PCI 39 AD10 40 AD9 Pin 1 is marked for orientation Am79C975 Am79C975 PQR160 Am79C973/Am79C975 120 EEDO/LED3/MIIRXFRTGD 119 DVSSP 118 DVDDP 117 RX- 116 DVDDRX 115 RX+ 114 SDI- 113 DVSSX 112 SDI+ 111 TX- ...

Page 21

... AD13 37 VSSB 38 AD12 39 AD11 40 VDD_PCI 41 AD10 42 AD9 Pin 1 is marked for orientation Am79C975 Am79C975 PQL176 Am79C973/Am79C975 NC 132 NC 131 130 EEDO/LED3/MIIRXFRTGD DVSSP 129 DVDDP 128 RX- 127 DVDDRX 126 RX+ 125 SDI- 124 DVSSX 123 SDI+ 122 ...

Page 22

... VSSB 75 EBDA9/TXD1 36 AD12 76 EBDA10/TXD2 37 AD11 77 VDDB 38 VDD_PCI 78 EBDA11/TXD3 39 AD10 79 EBDA12/TX_EN 40 AD9 80 EBDA13/MDIO Note: For the Am79C973 controller, pins 96, 98, and 100 are no connects (NC Pin Pin No. Name 81 EBDA14/CRS 82 EBDA15/COL 83 EBD7/TX_CLK 84 VSSB 85 EBD6/RX_ER 86 EBD5/RX_CLK 87 EBD4/RX_DV 88 VDDB 89 EBD3/RXD3 ...

Page 23

... AD11 83 VDDB 40 VDD_PCI 84 EBDA11/TXD3 41 AD10 85 EBDA12/TX_EN 42 AD9 86 EBDA13/MDIO Note: For the Am79C973 controller, pins 106, 108, and 110 are no connects (NC Pin Pin No. Name EBDA14/CRS 92 EBDA15/COL 93 EBD7/TX_CLK 94 VSSB 95 EBD6/RX_ER 96 EBD5/RX_CLK 97 ...

Page 24

... Type Am79C973/Am79C975 Driver No. of Pins TS3 32 TS3 STS6 1 STS6 OD6 1 STS6 1 TS3 1 STS6 1 TS3 OD6 1 STS6 1 STS6 1 LED 1 LED ...

Page 25

... Type I I/O I/O O Am79C973/Am79C975 Driver No. of Pins OD6 1 OD6 TS6 LED ...

Page 26

... Crystal Oscillator Power Notes: 1. Not including test features. 2. PHY power and ground pins require careful decoupling to ensure proper device performance Type Am79C973/Am79C975 Driver No. of Pins ...

Page 27

... PIN DESIGNATIONS Listed By Driver Type The following table describes the various types of out- put drivers used in the Am79C973/Am79C975 control- ler. All I and I values shown in the table apply to 3 signaling. Name Type LED LED OMII1 Totem Pole OMII2 Totem Pole O6 Totem Pole ...

Page 28

... DEVICE NUMBER/DESCRIPTION Am79C973/Am79C975 Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Valid Combinations list configurations planned to be supported in volume for this device. Consult the local KC\W, AMD sales office to confirm availability of specific VC\W valid combinations and to check on newly released combinations. Am79C973/Am79C975 Valid Combinations ...

Page 29

... When RST is active, GNT is an input for NAND tree test- ing. IDSEL Initialization Device Select This signal is used as a chip select for the Am79C973/ Input Am79C975 controller during configuration read and write transactions. When RST is active, IDSEL is an input for NAND tree testing ...

Page 30

... IRDY and TRDY are asserted simultaneously. A data phase is completed on any clock when both IRDY and TRDY are asserted. When the Am79C973/Am79C975 controller is a bus master, it asserts IRDY during all write data phases to indicate that valid data is present on AD[31:0]. During all read data phases, the device asserts IRDY to indi- cate that it is ready to accept the data ...

Page 31

... TRDY to deter- Input mine if the target is ready to accept the data. When the Am79C973/Am79C975 controller is the tar- get of a transaction, it asserts TRDY during all read data phases to indicate that valid data is present on AD[31:0]. During all write data phases, the device as- serts TRDY to indicate that it is ready to accept the data ...

Page 32

... SFBD pins. The LED1 pin is also used during EEPROM Auto- Detection to determine whether or not an EEPROM is present at the Am79C973/Am79C975 controller inter- face. At the last rising edge of CLK while RST is active LOW, LED1 is sampled to determine the value of the EEDET bit in BCR19 important to maintain ade- quate hold time around the rising edge of the CLK at this time to ensure a correctly sampled value ...

Page 33

... EEPROM that uses the 93C46 EEPROM interface pro- tocol. EEDO is connected to the EEPROM’s data out- put pin controlled by either the Am79C973 Am79C975 controller during command portions of a ...

Page 34

... Transmit Clock Input/Output TX_CLK is a continuous clock input that provides the timing reference for the transfer of the TX_EN, TXD[3:0], and TX_ER signals out of the Am79C973/ Am79C975 device. TX_CLK must provide a nibble rate clock (25% of the network data rate). Hence, an MII with ...

Page 35

... RX_DV is an input used to indicate that valid received Input/Output data is being presented on the RXD[3:0] pins and RX_CLK is synchronous to the receive data. In order for a frame to be fully received by the Am79C973/ Am79C975 device, RX_DV must be asserted prior to the RX_CLK rising edge, when the first nibble of the Am79C973/Am79C975 5% resistor ...

Page 36

... TCK is the clock input for the boundary scan test mode operation. It can operate at a frequency MHz. TCK has an internal pull up resistor. TDI Test Data In TDI is the test data input path to the Am79C973/ Am79C975 controller. The pin has an internal pull up resistor. Output TDO ...

Page 37

... MIRQ is an asynchronous attention signal that the Am79C975 controller provides to indicate that a man- agement frame has been transmitted or received. The assertion of the MIRQ signal can be controlled by a glo- bal mask bit (MIRQEN) or individual mask bits Am79C973/Am79C975 Output Output Pin XCLK/XTAL Clock Source ...

Page 38

... PDX Ground Ground These pins are the ground connection for the Physical Data Transceiver (PDX) block. They must be directly connected to the common external ground plane. DVDDCO Crystal This pin supplies the power to the Crystal circuit. Am79C973/Am79C975 +3.3 V Power +3.3 V Power +3.3 V Power Ground Ground +3.3 V Power ...

Page 39

... Am79C973/Am79C975 controller interrupt channel. This allows for a jumperless implementation. The second portion of the software interface is the di- rect access to the I/O resources of the Am79C973/ Am79C975 controllers. The Am79C973/Am79C975 controllers occupy 32 bytes of address space that must begin on a 32-byte block boundary. The address space can be mapped into I/O or memory space (memory mapped I/O) ...

Page 40

... MEMEN (for memory mapped I/O mode) in the PCI Command register, it starts monitoring the PCI bus for access to its CSR, BCR, or APROM locations. If configured for regular I/O mode, the Am79C973/ Am79C975 controllers will look for an address that falls within its 32 bytes of I/O address space (starting from the I/O base address) ...

Page 41

... I/O resource is accessed. The typical number of wait states added to a slave I/O or memory mapped I/O read or write access on the part of the Am79C973/Am79C975 controllers are six to sev- en clock cycles, depending upon the relative phases the internal Buffer Management Unit clock and the CLK signal, since the internal Buffer Management Unit clock is a divide-by-two version of the CLK signal ...

Page 42

... Figure 3. Slave Read Using I/O Command CLK 1 2 FRAME ADDR AD 0111 C/BE PAR PAR IRDY TRDY DEVSEL STOP Figure 4. Slave Write Using Memory Command PAR DATA BE PAR Am79C973/Am79C975 DATA PAR 21510D21510D 21510D-9 ...

Page 43

... The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C973/Am79C975 controllers will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Expansion ROM Base Address register, bit 0) are set to 1 ...

Page 44

... ROM is present when it reads the ROM signa- ture 55H (byte 0) and AAH (byte 1). Slave Cycle Termination There are three scenarios besides normal completion of a transaction where the Am79C973/Am79C975 con- trollers are the target of a slave cycle and it will termi- nate the access. Disconnect When Busy ...

Page 45

... If the host is not yet ready when the Am79C973/ Am79C975 controller asserts TRDY, the device will wait for the host to assert IRDY. When the host asserts IRDY and FRAME is still asserted, the Am79C973/ Am79C975 controller will finish the first data phase by deasserting TRDY one clock later. At the same time, it will assert STOP to signal a disconnect to the host ...

Page 46

... Bus Acquisition The Am79C973/Am79C975 microcode will determine when a DMA transfer should be initiated. The first step in any Am79C973/Am79C975 bus master transfer is to acquire ownership of the bus. This task is handled by synchronous logic within the BIU. Bus ownership is re- quested with the REQ signal and ownership is granted by the arbiter through the GNT signal ...

Page 47

... Am79C973/Am79C975 controller non-burst read ac- cesses are of the PCI command type Memory Read (type 6). Note that during a non-burst read operation, all byte lanes will always be active. The Am79C973/ Am79C975 controller will internally discard unneeded bytes The Am79C973/Am79C975 controller typically per- forms more than one non-burst read transaction within a single bus mastership period ...

Page 48

... ADDR DATA ADDR 0000 0110 0110 PAR PAR Figure 12. Non-Burst Read Transfer ADDR DATA DATA 1110 0000 PAR PAR Am79C973/Am79C975 DATA 0000 PAR PAR 21510D- DATA PAR PAR 21510D-18 ...

Page 49

... DEVSEL one clock late and another wait state by also asserting TRDY one clock late. The second transaction shows a zero wait state write cycle. The target asserts DEVSEL and TRDY in the same cycle as the Am79C973/Am79C975 control- ler asserts IRDY. CLK 1 ...

Page 50

... STOP. STOP is asserted on clock 4 to start the termination se- quence. Data is still transferred during this cycle, since both IRDY and TRDY are asserted. The Am79C973/ Am79C975 controller terminates the current transfer with the deassertion of FRAME on clock 5 and of IRDY one clock later ...

Page 51

... FRAME on clock 5 and of IRDY one clock cycle later. It finally releases the bus on clock 6. Since data integrity is not guaranteed, the Am79C973/ Am79C975 controller cannot recover from a target abort event. The Am79C973/Am79C975 controller will reset all CSR locations to their STOP_RESET values. ...

Page 52

... The host can read the PCI Status register to determine the exact cause of the interrupt. Master Initiated Termination There are three scenarios besides normal completion of a transaction where the Am79C973/Am79C975 con- troller will terminate the cycles it produces on the PCI bus. Preemption During Non-Burst Transaction ...

Page 53

... DEVSEL is sampled Figure 18. Target Abort When the preemption occurs after the counter has counted down to 0, the Am79C973/Am79C975 control- ler will finish the current data phase, deassert FRAME, finish the last data phase, and release the bus. Note that it is important for the host to program the PCI La- tency Timer according to the bus bandwidth require- ment of the Am79C973/Am79C975 controller ...

Page 54

... Figure 20. Preemption During Burst Transaction ADDR DATA 0111 BE PAR PAR DEVSEL is sampled ADDR DATA DATA DATA DATA 0111 BE PAR PAR PAR PAR DEVSEL is sampled Am79C973/Am79C975 6 7 21510D- DATA PAR PAR 21510D-25 ...

Page 55

... DEVSEL REQ GNT DEVSEL is sampled Figure 21. Master Abort CLK FRAME AD ADDR 0111 C/BE PAR PAR PERR IRDY TRDY DEVSEL DEVSEL is sampled Figure 22. Master Cycle Data Parity Error Response Am79C973/Am79C975 DATA 0000 PAR DATA BE PAR 21510D-26 21510D-27 55 ...

Page 56

... The Am79C973/Am79C975 supports two transfer modes for reading the initialization block: non-burst and burst mode, with burst mode being the preferred mode when the Am79C973/Am79C975 controller is used in a PCI bus application. See Figure 23 and Figure 24. When BREADE is cleared to 0 (BCR18, bit 6), all initial- ization block read transfers will be executed in non- burst mode ...

Page 57

... Figure 23. Initialization Block Read In Non-Burst Mode CLK FRAME IADD i AD 0110 C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 24. Initialization Block Read In Burst Mode Am79C973/Am79C975 IADD i +4 DATA 0110 0000 PAR PAR PAR DATA ...

Page 58

... During descriptor read accesses, the byte enable sig- nals will indicate that all byte lanes are active. Should some of the bytes not be needed, then the Am79C973/ Am79C975 controller will internally discard the extra- neous information that was gathered during such a read ...

Page 59

... DEVSEL is sampled Figure 25. Descriptor Ring Read In Non-Burst Mode CLK FRAME AD MD1 0110 C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 26. Descriptor Ring Read In Burst Mode Am79C973/Am79C975 MD0 DATA 0110 0000 PAR PAR PAR DATA DATA ...

Page 60

... PCI bus application Non-Burst FIFO DMA Transfers In the default mode, the Am79C973/Am79C975 con- troller uses non-burst transfers to read and write data when accessing the FIFOs. Each non-burst transfer will be performed sequentially with the issue of an address ...

Page 61

... DEVSEL is sampled Figure 27. Descriptor Ring Write In Non-Burst Mode CLK FRAME MD2 AD 0110 C/BE PAR PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled Figure 28. Descriptor Ring Write In Burst Mode Am79C973/Am79C975 MD1 DATA 0111 0011 PAR PAR PAR DATA ...

Page 62

... Burst FIFO DMA Transfers Bursting is only perfor med by the Am79C973/ Am79C975 controller if the BREADE and/or BWRITE bits of BCR18 are set. These bits individually enable/ disable the ability of the Am79C973/Am79C975 con- troller to perform burst accesses during master read operations and master write operations, respectively. ...

Page 63

... Re-Initialization Am79C973/Am79C975 controller can be turned on via the initialization block (DTX, DRX, CSR15, bits 1-0). The states of the transmitter and receiver are moni- tored by the host through CSR0 (RXON, TXON bits). ...

Page 64

... See the section on Magic Packet™ technology for de- tails on how that affects suspension of the Am79C973/ Am79C975 controller. Buffer Management Buffer management is accomplished through message descriptor entries organized as ring structures in mem- ory ...

Page 65

... Am79C973/Am79C975 controller or the host. The OWN bit within the descriptor status information, either TMD or RMD, is used for this purpose. When OWN is set signifies that the Am79C973/ Am79C975 controller currently has ownership of this ring descriptor and its associated buffer. Only the owner is permitted to relinquish ownership or to write to any field in the descriptor entry ...

Page 66

... Am79C973/Am79C975 controller does not own the current RDTE and the poll time has elapsed and RXON = 1 (CSR0, bit 5 Am79C973/Am79C975 controller does not own the next RDTE and there is more than one receive de- scriptor in the ring and the poll time has elapsed and RXON = 1 ...

Page 67

... Transmit Descriptor Table Entry If, after a Transmit Descriptor Table Entry (TDTE) ac- cess, the Am79C973/Am79C975 controller finds that the OWN bit of that TDTE is not set, the Am79C973/ Am79C975 controller resumes the poll time count and re-examines the same TDTE at the next expiration of the poll time count. ...

Page 68

... TINT bit of CSR0 is set to indicate the completion of a transmission. This causes an interrupt signal if the IENA bit of CSR0 has been set and the TINTM bit of CSR3 is cleared. The Am79C973/ Am79C975 controller provides two modes to reduce the number of transmit interrupts. The interrupt of a successfully transmitted frame can be suppressed by setting TINTOKD (CSR5, bit 15 ...

Page 69

... The Am79C973/Am79C975 controller will also try to access the RDTE during normal descriptor accesses whether they are transmit or receive accesses. The host can force the Am79C973/Am79C975 controller to immediately access the RDTE by setting the RDMD (CSR 7, bit 13 Its operation is similar to the trans- mit one ...

Page 70

... If the frame terminates or suffers a collision before 64 bytes of information (after SFD) have been received, the MAC engine will automatically delete the frame from the receive FIFO, without host intervention. The Am79C973/Am79C975 controller has the ability to ac- cept runt packets for diagnostic purposes and propri- etary networks. Am79C973/Am79C975 ...

Page 71

... CSMA/CD MAC monitor the medium for traffic by watching for carrier activity. When carrier is detected, the media is considered busy, and the MAC should defer to the existing message. The ISO 8802-3 (IEEE/ANSI 802.3) standard also al- lows optionally a two-part deferral after a receive mes- sage. Am79C973/Am79C975 71 ...

Page 72

... The IPG counter will be cleared to 0 continuously until the carrier deasserts, at which point the IPG counter will resume the 9.6 ms count once again. Once the IFS1 period of 6.0 ms has elapsed, the Am79C973/ Am79C975 controller will begin timing the second part deferral (InterFrameSpacingPart2 - IFS2) of 3.4 ms. ...

Page 73

... This modified backoff algorithm is enabled when EMBA (CSR3, bit 3) is set to 1. Transmit Operation The transmit operation and features of the Am79C973/ Am79C975 controller are controlled by programmable options. The Am79C973/Am79C975 controller offers a large transmit FIFO to provide frame buffering for in- creased system latency, automatic retransmission with no FIFO reload, and automatic transmit padding ...

Page 74

... At the point that FCS appended, the transmitted frame should contain: Preamble/SFD + (Min Frame Size - FCS (512-32) = 544 bits A minimum length transmit frame from the Am79C973/ Am79C975 controller, therefore, will be 576 bits, after the FCS is appended. Transmit FCS Generation Automatic generation and transmission of FCS for a transmit frame depends on the value of DXMTFCS (CSR15, bit 3) ...

Page 75

... INTA to be activated. It will, however, set the ERR bit CSR0 Receive Operation The receive operation and features of the Am79C973/ Am79C975 controller are controlled by programmable options. The Am79C973/Am79C975 controller offers a large receive FIFO to provide frame buffering for in- ...

Page 76

... When the Am79C973/Am79C975 controller is not pro- grammed promiscuous mode, but the EADI in- terface is enabled, then when none of the three match bits is set indication that the Am79C973/ Am79C975 controller only accepted the frame because it was not rejected by driving the EAR pin LOW within 64 bytes after SFD ...

Page 77

... Figure 34. IEEE 802.3 Frame And Length Field Transmission Order Since any valid Ethernet Type field value will always be greater than a normal IEEE 802.3 Length field (Š46), the Am79C973/Am79C975 controller will not attempt to strip valid Ethernet frames. Note that for some network protocols, the value passed in the Ethernet Type and/ or IEEE 802 ...

Page 78

... FCS generator on the transmit side can still be disabled by setting DXMTFCS (CSR15, bit internal loopback operation, the Am79C973/ Am79C975 controller provides a special mode to test the collision logic. When FCOLL (CSR15, bit 4) is set collision is forced during every transmission at- tempt ...

Page 79

... PHY Control Register (ANR0) bit 8 is set Auto- Negotiation is disabled. Full-Duplex Link Status LED Support The Am79C973/Am79C975 controller provides bits in each of the LED Status registers (BCR4, BCR5, BCR6, BCR7) to display the Full-Duplex Link Status. If the FDLSE bit (bit 8) is set, a value of 1 will be sent to the associated LEDOUT bit when in Full-Duplex ...

Page 80

... The loopback option utilizes the serial loopback path from the PDX serial output to the PDX serial input and can be programmed via the LBK[1:0] bits in the PHY Control/Status Register (ANR17). For the corresponding LBK setting, refer to the descrip- tion for the PHY Control/Status Register. Am79C973/Am79C975 ...

Page 81

... Note: The 5-bit mode bypasses Encoder/Decoder and Scrambler/Descrambler logic. Figure 35. 100BASE-X Transmit and Receive Data Paths of the Internal PHY Internal MII-Compatible Interface RX_DV 5 5 Loopback Paths 5 Symbol O/P SDI Serial O/P Am79C973/Am79C975 RXD[3:0] & RX_ER DISALIGN 5B/4B Decoder Code Align DISSCR 1 0 Descrambler ...

Page 82

... Transmit Error; used to force signaling errors Am79C973/Am79C975 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 ...

Page 83

... V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined V Undefined Am79C973/Am79C975 Interpretation Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data A Data B Data C Data D Data E Data F IDLE; used as Inter-Stream fill code Start-of-Stream Delimiter, Part always used in pairs with K Start-of-Stream Delimiter, Part ...

Page 84

... PHY is connected as in Figure 37, the transmit and re- ceive signals will be compliant with IEEE 802.3u Sec- tion 25. The required signals (MLT-3) are described in detail in ANSI X3.263:1995 TP-PMD Revision 2.2 (1995). The 10/100 PHY provides on-chip filtering. External fil- ters are not required for either the transmit or receive signals. Am79C973/Am79C975 ...

Page 85

... Medium Dependent Interface The Am79C973/Am79C975 device connects directly to low cost magnetics modules for interface to twisted pair media (UTP and/or STP). The TX± and RX± pins pro- vide the interface for both 10BASE-T and 100BASE-TX allowing the use of a 1:1 ...

Page 86

... Signals appearing at the RX± differential input pair are routed to the internal decoder. The receiver function meets the propagation delays and jitter requirements specified by the 10BASE-T Standard. The receiver squelch level drops to half its threshold value after un- squelch to allow reception of minimum amplitude sig- Am79C973/Am79C975 RJ45 Connector (8) (7) RX+ (3) ...

Page 87

... Figure 38. 10BASE-T Transmit and Receive Data Paths Twisted Pair Interface Status The Am79C973/Am79C975 device will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse width/amplitude requirements of the RX± ...

Page 88

... The EADI interface can be used in conjunction with external logic to capture the packet destination ad- dress as it arrives at the Am79C973/Am79C975 con- troller, to compare the captured address with a table of stored addresses or identifiers, and then to determine whether or not the Am79C973/Am79C975 controller should accept the packet ...

Page 89

... EAR signal, assuming that the Am79C973/Am79C975 controller is not config- ured to accept runt packets. The EADI logic only sam- ples EAR from 2 bit times after SFD until 512 bit times (64 bytes) after SFD ...

Page 90

... The Am79C973/Am79C975 controller will always read four bytes for every host Expansion ROM read access. The interface to the Expansion Bus runs synchronous to the PCI bus interface clock. The Am79C973/ Am79C975 controller will start the read operation to the Expansion ROM by driving the upper 8 bits of the Ex- pansion ROM address on EBUA_EBA[7:0] ...

Page 91

... ROM, the Am79C973/Am79C975 controller will dis- connect the access at the second data phase v_A_D The host must program the Expansion ROM Base Ad- dress register in the PCI configuration space before the first access to the Expansion ROM. The Am79C973/ Am79C973/Am79C975 ) and by v_A_D ) from the time defined by s_D ...

Page 92

... BASE, PCI Expansion ROM Base Address register, bits 31-20). The address output to the Expansion ROM is the offset from the address on the PCI bus to ROM- BASE. The Am79C973/Am79C975 controller aliases all accesses to the Expansion ROM of the command types Memory Read Multiple and Memory Read Line to the basic Memory Read command ...

Page 93

... PCI Memory Mapped I/O Base Address register, before enabling access to the Expansion ROM. The host must set the PCI Memory Mapped I/O Base Ad- dress register to a value that prevents the Am79C973/ Am79C975 controller from claiming any memory cy- cles not intended for it. ...

Page 94

... EBAD- DRU. The Flash write is almost the same procedure as the read access, except that the Am79C973/Am79C975 controller will not drive AS_EBOE low. The EROMCS and EBWE are driven low for the value ROMTMG again. The write to the FLASH port is a posted write ...

Page 95

... EBWE pulse in the command se- quence and terminates when the data on EBD[ which time the Flash device returns to the read mode. Polling by the Am79C973/Am79C975 controller is not required during the erase sequence. The follow- ing FLASH programming-table excerpt (Table 12) shows the command sequence for byte programming and sector/chip erasure on an AMD Flash device ...

Page 96

... The FIFOs will op- erate the same as in the PCnet-PCI II controller. When the SRAM SIZE (BCR25, bits 7-0) value is 0, the SRAM BND (BCR26, bits 7-0) are ignored by the Am79C973/ Am79C975 controller. See Figure 46. Low Latency Receive Configuration ...

Page 97

... Bus MAC Rcv Rcv FIFO FIFO MAC Bus Xmt Xmt FIFO FIFO FIFO Control Bus MAC Rcv Rcv FIFO FIFO SRAM Bus MAC Xmt Xmt FIFO FIFO FIFO Control Am79C973/Am79C975 802.3 MAC Core 21510D-51 802.3 MAC Core 21510D-52 97 ...

Page 98

... EEPROM. If the checksum verification passes, PVALID (BCR19, bit 15) will be set the checksum verification of the EEPROM data fails, PVALID will be cleared to 0, and the Am79C973/ Am79C975 controller will force all EEPROM-program- mable BCR registers back to their H_RESET default values ...

Page 99

... When an LED circuit is directly connected to the EEDO/LED3/SRD pin, then it is not possible for most EEPROM devices to sink enough I low level on the EEDO input to the Am79C973/ Am79C975 controller. Use of buffering can be avoided if a low power LED is used. Each LED can be programmed through a BCR register ...

Page 100

... Reserved for Boot ROM usage Note: *Lowest EEPROM address. 100 Table 13. Am79C973 EEPROM Map Byte Addr. First byte of the IS0 8802-3 (IEEE/ANSI 802.3) station physical address for this node, where 00h “first byte” refers to the first byte to appear on the 802 ...

Page 101

... BCR48[7:0] N_IP_ADR[7:0] 44h BCR49[7:0] N_IP_ADR[23:16] 46h BCR50[7:0] M_IEEE_ADR[7:0] 48h BCR51[7:0] M_IEEE_ADR[23:16] 4Ah BCR52[7:0] M_IEEE_ADR[39:32] 4Ch BCR53[7:0] M_IP_ADR[7:0] 4Eh BCR54[7:0] M_IP_ADR[23:16] 50h BCR55[7:0] SMIU Slave Address 7Ch Reserved for Boot ROM usage 7Eh Reserved for Boot ROM usage Am79C973/Am79C975 Least Significant Byte 101 ...

Page 102

... Figure 48. LED Control Logic The general scheme for the Am79C973/Am79C975 power management is that when a PCI Wake-up event is detected, a signal is generated to cause hardware external to the Am79C973/Am79C975 device to put the computer into the working (S0) mode. The Am79C973/Am79C975 device supports three types of wake-up events: 1 ...

Page 103

... PMCSR register of every PCI device in the system to determine which device asserted the PME signal. When the software determines that the signal came from the Am79C973/Am79C975 controller, it writes to the device’s PMCSR to put the device into power state ...

Page 104

... PME_EN_OVR bit (CSR116, bit 10) are set, then the PME will also be asserted. OnNow Pattern Match Mode In the OnNow Pattern Match Mode, the Am79C973/ Am79C975 device compares the incoming packets with up to eight patterns stored in the Pattern Match RAM (PMR). The stored patterns can be compared with part or all of incoming packets, depending on the pattern length and the way the PMR is programmed ...

Page 105

... The Am79C973/Am79C975 controller will be placed in the Magic Packet Mode when either the PG input is deasserted or the MPEN bit is set. WUMI output will be asserted when the Am79C973/ Am79C975 controller is in the Magic Packet mode. Magic Packet mode can be disabled at any time by as- serting PG or clearing MPEN bit ...

Page 106

... CLK, it will do so after en- abling the Magic Packet mode. CAUTION: To prevent unwanted interrupts from other active parts of the Am79C973/Am79C975 controller, care must be taken to mask all likely interruptible events during Magic Packet mode. An example would be the interrupts from the Media Independent Interface, which could occur while the device is in Magic Packet mode ...

Page 107

... H_RESET Hardware Reset (H_RESET Am79C973/ Am79C975 reset operation that has been created by the proper assertion of the RST pin of the Am79C973/ Am79C975 device while the PG pin is HIGH. When the minimum pulse width timing as specified in the RST pin description has been satisfied, then an internal reset operation will be performed ...

Page 108

... PMCSR_BSE 108 specification revision 2.1. The 64-byte header includes all registers required to identify the Am79C973/ Am79C975 controller and its function. Additionally, PCI Power Management Interface registers are imple- mented at location 40h - 47h. The layout of the Am79C973/Am79C975 PCI configuration space is shown in Table 19 ...

Page 109

... Address PROM space. Reset Register A read of the Reset register creates an internal soft- ware reset (S_RESET) pulse in the Am79C973/ Am79C975 controller. The internal S_RESET pulse that is generated by this access is different from both the assertion of the hardware RST pin (H_RESET) and from the assertion of the software STOP bit ...

Page 110

... DWord operation is a write access to the RDP, which switches the device to DWord I/O mode. A read access other than listed in the table below will yield undefined data, a write operation may cause unexpected repro- gramming of the Am79C973/Am79C975 control regis- ters. Table 21 shows legal I/O accesses in Word I/O mode. Table 20. I/O Map In Word I/O Mode (DWIO = 0) No ...

Page 111

... BDP 11000 0000 0XX00 0000 10000 0000 10100 0000 11000 0000 Am79C973/Am79C975 Mode (DWIO =1) Type Comment DWord read of APROM locations 3h (MSB (LSB 4h DWord read of RDP RD DWord read of RAP DWord read of Reset ...

Page 112

... Am79C973/Am79C975 controller PCI bus interface. The following is a list of the registers that would typi- cally need to be programmed once during the initializa- tion of the Am79C973/Am79C975 controller within a system: — PCI I/O Base Address or Memory Mapped I/O Base Address register — ...

Page 113

... The following is a list of the registers that would typi- cally need to be periodically read and perhaps written during the normal running operation of the Am79C973/ Am79C975 controller within a system. Each of these registers contains control bits, or status bits, or both. RAP ...

Page 114

... AMD’s product line. The Am79C973/ Am79C975 Device ID is 2000h. Note that this Device ID is not the same as the Part number in CSR88 and CSR89. The Device ID is assigned by AMD. The De- vice ID is the same as the PCnet-PCI II (Am79C970A) and PCnet-FAST (Am79C971) devices. ...

Page 115

... Signaled SERR. SERR is set when the Am79C973/Am79C975 controller detects an address par- ity error and both SERREN and PERREN (PCI Command regis- ter, bits 8 and 6) are set. SERR is set by the Am79C973/ Am79C975 controller and cleared by writing a 1. Writing a 0 has no effect. SERR is cleared by ...

Page 116

... PCI Programming Interface Register Offset 09h The PCI Programming Interface register is an 8-bit reg- the Am79C973/ ister that identifies the programming interface of Am79C973/Am79C975 controller. PCI does not define Am79C973/Am79C975 PERR input to detect whether the target has reported a parity error. DATAPERR is set ...

Page 117

... PCI Configuration Space read only. PCI Sub-Class Register Offset 0Ah The PCI Sub-Class register is an 8-bit register that iden- tifies specifically the function of the Am79C973/ Am79C975 controller. The value of this register is 00h which identifies the Am79C973/Am79C975 device as an Ethernet controller. ...

Page 118

... I/O base address. PCI Memory Mapped I/O Base Address Register Offset 14h The PCI Memory Mapped I/O Base Address register is a 32-bit register that determines the location of the Am79C973/Am79C975 I/O resources in all of memory space located at offset 14h in the PCI Configuration Space. Bit Name Description ...

Page 119

... Offset 2Ch The PCI Subsystem Vendor ID register is a 16-bit reg- ister that together with the PCI Subsystem ID uniquely identifies the add-in card or subsystem the Am79C973/ Am79C975 controller is used in. Subsystem Vendor IDs can be obtained from the PCI SIG. A value of 0 (the default) indicates that the Am79C973/Am79C975 con- troller does not support subsystem identification ...

Page 120

... PCI MAX_LAT Register Offset 3Fh The PCI MAX_LAT register is an 8-bit register that spec- ifies the maximum arbitration latency the Am79C973/ Am79C975 controller can sustain without causing prob- lems to the network activity. The register value specifies the time in units of 1/4 µs. The MAX_LAT register is an alias of BCR22, bits 15-8 ...

Page 121

... PMIS_VER Power Management Interface PCI Power Management Control/Status Register (PMCSR) Offset 44h Bit Name 15 PME_STATUS PME Status. This bit is set when Am79C973/Am79C975 Reserved locations. Written as zeros and read as undefined. Device Specific Initialization. When this bit indicates that special initialization of the func- ...

Page 122

... RAP Register The RAP (Register Address Pointer) register is used to gain access to CSR and BCR registers on board the Am79C973/Am79C975 controller. The RAP contains the address of a CSR or BCR example of RAP use, consider a read access to CSR4. In order to access this register necessary ...

Page 123

... RDP access will depend upon the current setting of the RAP. RAP serves as a pointer into the CSR space. CSR0: Am79C973/Am79C975 Controller Status and Control Register Certain bits in CSR0 indicate the cause of an interrupt. The register is designed so that these indicator bits are cleared by writing ones to those bit locations ...

Page 124

... STOP bit. Initialization Done is set by the Am79C973/Am79C975 controller after the initialization sequence has completed. When IDON is set, the Am79C973/Am79C975 controller has read the initializa- tion block from memory. When IDON is set, INTA is as- serted if IENA is 1 and the mask bit IDONM (CSR3, bit ...

Page 125

... Am79C973/Am79C975 controller to send and receive frames, and perform buffer management op- erations. Setting STRT clears the STOP bit. If STRT and INIT are set together, the Am79C973/ Am79C975 controller initializa- tion will be performed first. Read/Write accessible always. STRT is set by writing a 1. Writing a 0 has no effect. STRT is cleared by H_RESET, S_RESET setting the STOP bit ...

Page 126

... Note that the 16-bit software structures specified SSIZE32 = 0 setting will yield only 24 bits of address for the Am79C973/Am79C975 bus mas- 126 7-0 IADR[23:16] Bits 23 through 16 of the address 8), then ...

Page 127

... The interrupt will be signaled through the RINT bit of CSR0. Setting LAPPEN also en- ables the Am79C973/Am79C975 controller to read the STP bit of receive descriptors. The Am79C973/Am79C975 controller will use the STP information to determine where it should begin writing a receive packet’ ...

Page 128

... Am79C973/Am79C975 con- troller will reset the OWN bit these entries scanned en- try indicates host ownership with STP = 0, then the Am79C973/ Am79C975 controller will not al- ter the entry, but will advance to the next entry. When the STP bit is found to be ...

Page 129

... TXDPOLL the Am79C973/ 11 APAD_XMT Auto Pad Transmit. When set, 10 ASTRP_RCV Auto Strip Receive. When set, Am79C973/Am79C975 or S_RESET and is unaffected by the STOP bit. has no effect. DMAPLUS is al- ways set to 1. Reserved Location. Written as zero and read as undefined. Disable Transmit Polling. If TXD- POLL is set, the Buffer Manage- ment Unit will disable transmit polling ...

Page 130

... Read/Write accessible always. UINT is cleared by the host by writing a 1. Writing a 0 has no ef- fect. UINT H_RESET or S_RESET or by setting the STOP bit. 5 RCVCCO Receive Collision Counter Over- flow is set by the Am79C973/ 130 the Am79C973/ has wrapped is cleared by ...

Page 131

... RES Reserved locations. Written as zeros and read as undefined. 11 SINT System Interrupt is set by the Am79C973/Am79C975 controller when it detects a system error during a bus master transfer on the PCI bus. System errors are data parity error, master abort target abort. The setting of SINT due to data parity error is ...

Page 132

... H_RESET or S_RESET and is not affected by setting the STOP bit. The Am79C973/Am79C975 con- troller will enter the Magic Packet mode when MPMODE is set to 1 and either PG is asserted or MPEN is set to 1. Read/Write accessible always. MPMODE is cleared H_RESET or S_RESET and is ...

Page 133

... In suspend mode, all of the CSR and BCR registers are accessi- ble. As long as the Am79C973/ Am79C975 controller is not reset while in suspend mode (by H_RESET, S_RESET or by set- ting the STOP bit), no re-initial- ization of the device is required after the device comes out of sus- pend mode. The Am79C973/ ...

Page 134

... Am79C973/Am79C975 RDMD is required to be set if the RXDPOLL bit in CSR7 is set. Set- ting RDMD while RXDPOLL = 0 merely hastens the Am79C973/ Am79C975 controller’s response to a receive Descriptor Ring En- try. Read/Write accessible always. RDMD is set by writing a 1. Writ- ing a 0 has no effect. RDMD will ...

Page 135

... STOP bit 9 MREINT PHY Management Read Error In- terrupt. The PHY Read Error in- terrupt is set by the Am79C973/ Am79C975 controller to indicate that the currently read register from the PHY is invalid. The con- tents of BCR34 are incorrect and that the operation should be per- formed again ...

Page 136

... Name 31-16 RES 15-0 LADRF[31:16] Logical Address Filter, LADRF- set Am79C973/Am79C975 rupt is set by the Am79C973/ Am79C975 controller whenever the MIIPD bit (BCR32, bit 14) transitions from vice ver- sa. Read/Write accessible always. MIIPDTINT is cleared by the host by writing a 1. Writing a 0 has no effect. MIIPDTINT is cleared by ...

Page 137

... RES 15-0 PADR[31:16]Physical Filter, CSR14: Physical Address Register 2 Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name Am79C973/Am79C975 Address Register, PADR[15:0]. The contents of this register are loaded from EE- PROM after H_RESET EEPROM read command (PRGAD, BCR19, bit 14). If the ...

Page 138

... STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR15: Mode This register’s fields are loaded during the Am79C973/ Am79C975 controller initialization routine with the cor- responding Initialization Block values, or when a direct register write has been performed on this register. Bit ...

Page 139

... STOP or the SPND bit is set. LOOP is cleared by H_RESET or S_RESET and is unaffected by STOP. Disable Transmit results Am79C973/Am79C975 controller not accessing the Transmit De- scriptor Ring and, therefore, no transmissions are attempted. DTX = 0, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is as- serted ...

Page 140

... Reserved locations. Written as zeros and read as undefined. Contains the lower 16 bits of the next receive buffer address to which the Am79C973/ Am79C975 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...

Page 141

... CRDAU CSR30: Base Address of Transmit Ring Lower Bit Name 31-16 RES 15-0 BADXL Am79C973/Am79C975 Reserved locations. Written as zeros and read as undefined. Contains the upper 16 bits of the next receive descriptor address pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...

Page 142

... NNRDAL CSR37: Next Next Receive Descriptor Address Upper Bit Name 31-16 RES 15-0 NNRDAU Am79C973/Am79C975 Contains the lower 16 bits of the current transmit descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. ...

Page 143

... CSR43: Current Transmit Status Bit Name 31-16 RES 15-0 CXST CSR44: Next Receive Byte Count Bit Name Am79C973/Am79C975 Description Reserved locations. Written as zeros and read as undefined. Current Receive Status. This field is a copy of bits 31-16 of RMD1 of the current receive de- scriptor. Read/Write accessible only when either the STOP or the SPND bit is set ...

Page 144

... Transmit Poll Time Counter. This counter is incremented by the Am79C973/Am79C975 controller microcode and is used to trigger the transmit descriptor ring poll- ing operation of the Am79C973/ Am79C975 controller. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...

Page 145

... BPE will be set in the descriptor associated with the buffer that was accessed when a data parity error occurred. Note that since the advanced parity er- ror handling uses an additional bit in the descriptor, SWSTYLE (bits 7-0 of this register) must be set program the Am79C973/ 145 ...

Page 146

... Am79C975 controller to use 32- bit software structures. APERREN does not affect the re- porting of address parity errors or data parity errors that occur when the Am79C973/Am79C975 con- troller is the target of the transfer. Read anytime, write accessible only when either the STOP or the SPND bit is set. APERREN is cleared by H_RESET and is not affected by S_RESET or STOP ...

Page 147

... Undefined Undefined Am79C973/Am79C975 Contains the lower 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C973/ Am79C975 controller has the ca- pability to stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...

Page 148

... Reserved locations. Written as zeros and read as undefined. 15-0 PXDAU Contains the upper 16 bits of the previous transmit descriptor ad- dress pointer. The Am79C973/ Am79C975 controller has the ca- pability to stack multiple transmit frames. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP ...

Page 149

... Receive Ring Length. Contains the two’s complement of the re- ceive descriptor ring length. This register is initialized during the Am79C973/Am79C975 controller initialization routine based on the value in the RLEN field of the ini- tialization block. However, this register can be manually altered. ...

Page 150

... Transmit FIFO, and retries will be handled auton- omously by the MAC. If the Dis- able Retry feature is enabled the network is operating in full-du- plex mode, the Am79C973/ Am79C975 controller can over- write the beginning of the frame as soon as the data is transmit- ...

Page 151

... NOUFLO bit (CSR80, bit 14) is set to 1, there is the additional restriction that the complete transmit frame must be DMA’d into the Am79C973/ Am79C975 controller and reside within a combination of the Bus Transmit FIFO, the SRAM, and the MAC Transmit FIFO. ...

Page 152

... The DMABAU register is undefined until the first Am79C973/ Am79C975 controller DMA oper- ation. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. ...

Page 153

... Read accessible only when either the STOP or the SPND bit is set. VER is read only. VER is read only. Write operations are ig- nored. Upper 12 bits of the Am79C973/ Am79C975 controller part num- ber, i.e., 0010 0110 0010b (262h). Read accessible only when either the STOP or the SPND bit is set. ...

Page 154

... LCMODE_D3C. This bit is a read/write from the H_RESET or 12 MPPEN_D3C is cleared by 11 PMAT_MODE_D3C by the Am79C973/Am79C975 RCVCCO bit of CSR4 (bit 5) will be set each time that this occurs. Read accessible always. RCC is read only, write operations are ig- nored. RCC is cleared by H_RESET or S_RESET setting the STOP bit ...

Page 155

... EMPPLBA Magic Packet Physical Logical Broadcast Accept. If both EMP- PLBA and MPPLBA (CSR5, bit 5) are at their default value of 0, the Am79C973/Am79C975 controller will only detect a Magic Packet frame if the destination address of the packet matches the con- tent of the physical address regis- ter (PADR) ...

Page 156

... CSR124: Test Register 1 This register is used to place the Am79C973/ Am79C975 controller into various test modes. The Runt Packet Accept is the only user accessible test mode. All other test modes are for AMD internal use only. ...

Page 157

... Am79C973/Am79C975 con- troller that are not related to the IEEE 8802-3 MAC functions. The BCRs are accessed by first setting the appropriate RAP value and then by performing a slave access to the BDP. See Table 29. ...

Page 158

... MSRDA Reserved H_RESET, the value in this regis- ter will be 0005h. The setting of this register has no effect on any Am79C973/Am79C975 controller function only included for software compatibility with other PCnet family devices. Read always. MSRDA is read only. Write operations have no ef- fect. ...

Page 159

... Reserved 0000h 49 Reserved 0000h 50 Reserved 0000h 51 Reserved 0000h 52 Reserved 0000h Table 29. BCR Registers (Am79C973) Name Reserved Reserved Miscellaneous Configuration Reserved LED0 Status LED1 Status LED2 Status LED3 Status Reserved Full-Duplex Control Reserved Reserved Reserved Burst and Bus Control ...

Page 160

... Reserved 0000h 54 Reserved 0000h Note: *Program only as ‘0’ value. 160 Table 29. BCR Registers (Am79C973) Reserved (for Am79C975) Reserved (for Am79C975) Am79C973/Am79C975 Yes* Yes* Yes* Yes* ...

Page 161

... PCI DATA Register Six Alias Register PCI DATA Register Seven Alias Register Pattern Matching Register 1 Pattern Matching Register 2 Pattern Matching Register 3 Node IP Address [15:0] Node IP Address [31:16] Management IEEE Address [15:0] Management IEEE Address [31:16] Management IEEE Address [47:32] Am79C973/Am79C975 Programmability User EEPROM Yes Yes ...

Page 162

... Management IP Address [15:0] Management IP Address [31:16] 12 LEDPE 11 RESET_SFEX 10 I2C_M3 writes to 9 I2C_M2 Am79C973/Am79C975 Yes Yes Yes Yes Read/Write accessible always. PHYSELEN is cleared H_RESET and is unaffected by S_RESET or by setting the STOP bit. LED Program Enable. When LEDPE is set to 1, programming of the LED0 (BCR4), LED1 ...

Page 163

... When INTLEVEL is cleared to 0, the INTA pin is configured for level-sensitive applications. In this mode, an interrupt request is signaled by a low level driven on the INTA pin by the Am79C973/ Am79C975 controller. When the interrupt is cleared, the INTA pin is tri-stated by the Am79C973/ Am79C975 controller and al- lowed to be pulled to a high level by an external pullup device ...

Page 164

... Bit Name cleared by 31-16 RES 15 LEDOUT 14 LEDPOL Am79C973/Am79C975 Description Reserved locations. Written as zeros and read as undefined. This bit indicates the current (non-stretched) value of the LED output pin. A value this bit indicates that the OR of the en- abled signals is true. The logical value of the LEDOUT ...

Page 165

... FDLSE Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C973/ Am79C975 controller is function- ing in a Link Pass state and full- duplex operation is enabled. When the Am79C975 controller is not func- ...

Page 166

... S_RESET or setting the STOP bit. 100 Mbps Enable. When this bit is set value passed to the LEDOUT bit in this register when the Am79C973/Am79C975 controller is operating at 100 Mbps mode. Read/Write accessible always. 100E is cleared by H_RESET and is not affected by S_RESET ...

Page 167

... FDLSE Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C973/ Am79C975 controller is function- ing in a Link Pass state and full- duplex operation is enabled. When the Am79C975 controller is not func- ...

Page 168

... Magic Packet frame is detected on the network. Read/Write accessible always. MPSE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C973/ ...

Page 169

... Note: Bits 15-0 in this register are programmable through the EEPROM. Bit Name 31-16 RES 15 LEDOUT Am79C973/Am79C975 Read/Write accessible always. XMTE is cleared by H_RESET and is not affected by S_RESET or setting the STOP bit. Reserved location. Written and read as zeros. Receive Status Enable. When this bit is set, a value ...

Page 170

... STOP bit. Full-Duplex Link Status Enable. Indicates the Full-Duplex Link Test Status. When this bit is set, a value passed to the LED- OUT signal when the Am79C973/ Am79C975 controller is function- ing in a Link Pass state and full- duplex operation is enabled. When ...

Page 171

... Ethernet frame length of 64 bytes. Receive DMA will not start until at least 64 bytes or a com- plete frame have been received. By default, FDRPAD is cleared to 0. The Am79C973/Am79C975 controller will accept any length frame and receive DMA will start according to the programming of the receive FIFO watermark. ...

Page 172

... ROM accesses to Flash/EPROM. ROMTMG, during read opera- tions, defines the time from when the Am79C973/Am79C975 con- troller drives the lower bits of the Expansion Bus Address bus to when the Am79C973/ Am79C975 controller latches in the data on the bits of the Expansion Bus Data inputs ...

Page 173

... Am79C973/Am79C975 controller never performs more than one burst transaction within a single bus mastership period.) In this mode, the Am79C973/ Am79C975 controller relies on the PCI latency timer to get enough bus bandwidth, in case the system arbiter also removes 173 ...

Page 174

... STOP or the SPND bit is set. EX- TREQ is cleared by H_RESET and is not affected by S_RESET or STOP. 7 DWIO Double Word I/O. When set, this bit indicates that the Am79C973/ Am79C975 controller is pro- grammed for DWord I/O (DWIO) mode. When cleared, this bit indi- cates that Am79C975 controller is pro- grammed for Word I/O (WIO) mode ...

Page 175

... STOP or the SPND bit is set. After H_RESET, the value in these bits will be 001b. The setting of these bits have no Am79C973/Am79C975 controller function. LINBC is not affected by S_RESET or STOP BCR19: EEPROM Control and Status Bit ...

Page 176

... EEPROM locations may be accessed BCR19. At the end of the read operation, the PREAD bit will automatically be reset the Am79C973/ Am79C975 PVALID will be set, provided that an EEPROM existed on the inter- face pins and that the checksum for the entire 82 bytes of EE- PROM was correct ...

Page 177

... Active From ECS 1 Bit of BCR19 0 0 Am79C973/Am79C975 Read accessible always, write accessible only when either the STOP or the SPND bit is set. EEN is set H_RESET and is unaffected by the S_RESET or STOP bit. Reserved location. Written as zero and read as undefined. EEPROM Chip Select. This bit is ...

Page 178

... Am79C973/Am79C975 that since the advanced parity er- ror handling uses an additional bit in the descriptor, SWSTYLE (bits 7-0 of this register) must be set program the Am79C973/ Am79C975 controller to use 32- bit software structures. APERREN does not affect the re- porting of address parity errors or data parity errors that occur when the Am79C973/Am79C975 con- troller is the target of the transfer ...

Page 179

... CSR space, the order of the descriptor entries and the width of the descriptors and initialization block entries. All Am79C973/Am79C975 con- troller CSR bits and all descriptor, buffer, and initialization block en- tries not cited in the Table 33 are unaffected by the Software Style ...

Page 180

... S_RESET or STOP. 7-0 MIN_GNT Minimum Grant. Specifies the minimum length of a burst period the Am79C973/Am79C975 con- troller needs to keep up with the network activity. The length of the burst period is calculated assum- ing a clock rate of 33 MHz. The register value specifies the time in units of 1/4 ms ...

Page 181

... PCnet-PCI II con- troller. Note: The minimum allowed number of pages is eight for nor- mal network Am79C973/Am79C975 controller will not operate correctly with less than the eight pages of memory. When the minimum number of pages is used, these pages must be allocated four each for trans- mit and receive ...

Page 182

... Low Latency Receive. When the LOLATRX bit is set to 1, the Am79C973/Am79C975 controller will switch to an architecture ap- plicable to cut-through switches. The Am79C973/Am79C975 con- troller will assert a receive frame DMA after only 16 bytes of the current receive frame has been received regardless of where the RCVFW (CSR80, bits 13-12) are set ...

Page 183

... BCR29: Expansion Port Address Upper (Used for Flash/EPROM Accesses) Bit Name 31-16 RES 15 FLASH 14 LAAINC Am79C973/Am79C975 ed only, EPADDRL[0] is the least significant word address bit. On any byte write accesses to the SRAM, the user will have to fol- low the read-modify-write scheme. On any byte read ac- ...

Page 184

... BCR31: Software Timer Register Bit Name 31-16 RES 15-0 STVAL Am79C973/Am79C975 port. The Flash and SRAM ac- cesses use different address phases. Incorrect configuration will result in a possible corruption of data. Flash read cycles are performed when BCR30 is read and the FLASH bit (BCR29, bit 15) is set to 1 ...

Page 185

... H_RESET, and is unaffected by S_RESET and the STOP bit Auto-Poll PHY. APEP when set to 1 the Am79C973/Am79C975 controller will poll the status regis- ter in the PHY. This feature al- lows the software driver or upper layers to see any changes in the status of the PHY. An interrupt ...

Page 186

... Read/write accessible always. DANAS is set H_RESET and is unaffected by S_RESET and the STOP bit. 6 XPHYRST PHY Reset. When XPHYRST is set, the Am79C973/Am79C975 controller after an H_RESET or S_RESET will issue manage- ment frames that will reset the 186 ...

Page 187

... PHYAD Am79C973/Am79C975 controller reads the EEPROM and uses it to communicate with the external PHY. The PHY address must be programmed into the EEPROM prior to starting the Am79C973/ Am79C975 controller. Read/Write accessible always. PHYAD is H_RESET and is unaffected by S_RESET and the STOP bit. ...

Page 188

... PCI Subsystem Vendor ID and the Vendor ID to uniquely identify the add-in board or sub- system that the Am79C973/ Am79C975 controller is used in. Note: If the operating system or the network operating sys- tem supports PCI Subsystem ...

Page 189

... DATA_SEL field set to four. Bits 15-0 in this register are programmable through the EEPROM. Bit Name Cleared by Am79C973/Am79C975 H_RESET and is not affected by S_RESET or setting the STOP bit Description Reserved locations. Written as zeros and read as undefined. DATA_SCALE field of the PMC- SR (offset Register 44 of the PCI configuration space, bits 14-13) ...

Page 190

... Name 15-10 RES 9-8 D6_SCALE These bits correspond to the 7-0 DATA6 description of always. Am79C973/Am79C975 by S_RESET or setting the STOP bit These bits correspond to the PCI DATA register (offset Register 47 of the PCI configuration space, bits 7-0). Refer to the description of DATA register for the meaning of this field. ...

Page 191

... BCR45, BCR46, or BCR47 returns all undefined bits except for PMAT_MODE. When BCR45 is written and the PMAT_MODE bit is 0, the Pattern Match logic is disabled and accesses to the PMR are possible. Bits 6-0 of BCR45 specify the ad- Am79C973/Am79C975 Description Reserved locations. Written as zeros and read as undefined. Pattern Match RAM Byte 0. This ...

Page 192

... PMR_B4 7-0 PMR_B3 BCR48-BCR55: Reserved Locations for Am79C975 These registers must be 00h for the Am79C973 con- troller. PHY Management Registers (ANRs) The Am79C973/Am79C975 device supports the MII basic register set and extended register set. Both sets of registers are accessible through the PHY Manage- ment Interface ...

Page 193

... Table 39. Am79C973/Am79C975 Internal PHY Management Register Set Register Address (in Decimal) Register Name 0 PHY Control 1 PHY Status 2-3 PHY Identifier Auto-Negotiation 4 Advertisement Auto-Negotiation Link 5 Partner Ability Auto-Negotiation 6 Expansion Auto-Negotiation Next 7 Page 8-15 Reserved Interrupt Enable and 16 Status 17 PHY Control/Status Descrambler Resynch. 18 Timer PHY Management ...

Page 194

... Auto-Negotiation disable Auto-Negotiation 1 = power down normal operation 1 = electrically isolate PHY 0 = normal operation 1 = restart Auto-Negotiation normal operation 1 = full duplex half duplex 1 = enable COL signal test disable COL signal test Write as 0, ignore on read Am79C973/Am79C975 Read/Write Default Soft (Note 1) Value Reset R/ R/W 0 ...

Page 195

... Auto-Negotiation not completed 1 = remote fault detected remote fault detected 1 = PHY able to auto-negotiate PHY not able to auto-negotiate 1 = link is up link is down 1 = jabber condition detected jabber condition detected 1 = extended register capabilities basic register set capabilities only Am79C973/Am79C975 Read/Write Default (Note 1) Value ...

Page 196

... Description Read/Write IEEE Address (bits RO 19-24) Manufacturer’s Model Number (bits RO 5-0) Revision Number (bits 3-0); Register 3, RO bit bit of PHY Identifier Am79C973/Am79C975 Default Value Soft Reset 0000000000000000 Retains original Value (0000 Hex) Default Value Soft Reset 011010 Retains original value (1A Hex) 110110 ...

Page 197

... Setting this bit advertises Half Duplex capability. Clearing this bit does not advertise Half Duplex capability. 4:0 Selector Field The Am79C973/Am79C975 device is an 802.3 compliant device register is to advertise the technology ability to the link partner device. See Table 44. ...

Page 198

... the link partner. The bit definitions represent the re- ceived link code word. This register contains either the base page or the link partner’s next pages. See Table 45 and Table 46. Description Description Am79C973/Am79C975 Read/ H/W or Soft Write Reset RO 0 ...

Page 199

... Page Able 0 = Link partner is not next page able Am79C973/Am79C975 device channel is next page able 2 Next Page Able 0 = Am79C973/Am79C975 device channel is not next page able new page has been received. 1 Page Received new page has not been received Link partner is Auto-Negotiation able. ...

Page 200

... All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared. ANR17: PHY Control/Status Register (Register 17) This register is used to control the configuration of the 10/100 PHY unit of the Am79C973/Am79C975 device. See Table 50. When configuring the device to enable/disable the ...

Related keywords