AT89C51RD2-IM ATMEL Corporation, AT89C51RD2-IM Datasheet

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AT89C51RD2-IM

Manufacturer Part Number
AT89C51RD2-IM
Description
AT89C51RD2-IM8-bit Flash Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
Features
Description
AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS sin-
gle chip 8-bit microcontroller. It contains a 64-Kbyte Flash memory block for code and
for data.
The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming voltage is internally
generated from the standard V
80C52 Compatible
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
ISP (In-System Programming) Using Standard V
2048 Bytes Boot ROM Contains Low Level Flash Programming Routines and a Default
Serial Loader
High-speed Architecture
64K Bytes On-chip Flash Program/Data Memory
On-chip 1792 bytes Expanded RAM (XRAM)
On-chip 2048 Bytes EEPROM Block for Data Storage (AT89C51ED2 Only)
Dual Data Pointer
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independent Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
16-bit Programmable Counter Array
Asynchronous Port Reset
Full-duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (Inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-off Flag
Power Control Modes: Idle Mode, Power-down Mode
Single Range Power Supply: 2.7V to 5.5V
Industrial Temperature Range (-40 to +85 C)
Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40
– 8051 Instruction Compatible
– Six 8-bit I/O Ports (64 Pins or 68 Pins Versions)
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 Bytes Scratch Pad RAM
– 9 Interrupt Sources with 4 Priority Levels
– In Standard Mode:
– In X2 mode (6 Clocks/machine cycle)
– Byte and Page (128 Bytes) Erase and Write
– 100k Write Cycles
– Software Selectable Size (0, 256, 512, 768, 1024, 1792 Bytes)
– 768 Bytes Selected at Reset for T89C51RD2 Compatibility
– 100K Write Cycles
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
20 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
CC
pin.
CC
Power Supply
8-bit Flash
Microcontroller
AT89C51RD2
AT89C51ED2
Rev. 4235E–8051–04/04
1

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AT89C51RD2-IM Summary of contents

Page 1

... Packages: PLCC44, VQFP44, PLCC68, VQFP64, PDIL40 Description AT89C51RD2/ED2 is high performance CMOS Flash version of the 80C51 CMOS sin- gle chip 8-bit microcontroller. It contains a 64-Kbyte Flash memory block for code and for data. The 64-Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software ...

Page 2

... AT89C51RD2/ED2 2 The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage. In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 Mode) ...

Page 3

... C51 CORE IB-bus CPU Parallel I/O Ports & Timer 0 INT External Bus Ctrl Timer 1 Port 0 Port 1 Port 2 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 AT89C51RD2/ED2 (1) (1) (1) (1) (1) XRAM Watch PCA Timer2 Keyboard 1792 x 8 -dog BOOT SPI ROM ...

Page 4

... SFR Mapping AT89C51RD2/ED2 4 The Special Function Registers (SFRs) of the AT89C51RD2/ED2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...

Page 5

... WDTX2 PCAX2 SIX2 - - - - ET2 PPCH PT2H PHS - PPCL PT2L PLS - - - - - - - - AT89C51RD2/ED2 RS0 GF1 GF0 PD IDL XRS1 XRS0 EXTRAM AO GF3 0 - DPS - - - - T2X2 T1X2 T0X2 SPIX2 ET1 EX1 ET0 ...

Page 6

... F9h PCA Timer/Counter High Byte CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter Mode 1 CCAPM2 DCh PCA Timer/Counter Mode 2 CCAPM3 DDh PCA Timer/Counter Mode 3 CCAPM4 DEh PCA Timer/Counter Mode 4 AT89C51RD2/ED2 TF1 TR1 TF0 TR0 GATE1 C/T1# M11 M01 - ...

Page 7

... SPEN SSDIS SPIF WCOL SSERR SPD7 SPD6 SPD5 KBLS7 KBLS6 KBLS5 KBE7 KBE6 KBE5 KBF7 KBF6 KBF5 AT89C51RD2/ED2 CCAP0H3 CCAP0H2 CCAP0H1 CCAP1H3 CCAP1H2 CCAP1H1 CCAP2H3 CCAP2H2 CCAP2H1 CCAP3H3 CCAP3H2 CCAP3H1 CCAP4H3 CCAP4H2 CCAP4H1 CCAP0L3 CCAP0L2 CCAP0L1 CCAP1L3 ...

Page 8

... TCON TMOD 88h 0000 0000 0000 0000 P0 SP 80h 0000 0111 1111 1111 0/8 1/9 AT89C51RD2/ED2 8 Table 12 shows all SFRs with their address and their reset value. Non Bit Addressable 2/A 3/B 4/C CCAP0H CCAP1H CCAP2H XXXX XXXX XXXX XXXX XXXX XXXX CCAP0L ...

Page 9

... AT89C51RD2/ED2 39 P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 NIC* 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 RST 4 5 AT89C51RD2/ED2 NIC* 6 VQFP44 1 P0.4/AD4 33 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 NIC* 27 ALE/PROG 26 ...

Page 10

... P5.5 1 P0.3/AD3 2 P0.2/AD2 3 P5.6 4 P0.1/AD1 5 P0.0/AD0 6 P5.7 7 AT89C51ED2 VCC 8 NIC 9 P1.0/T2 10 P4.0 11 P1.1/T2EX/SS 12 P1.2/ECI 13 P1.3/CEX0 14 P4.1 15 P1.4/CEX1 16 AT89C51RD2/ED2 10 P5.5 10 P0.3/AD3 11 P0.2/AD2 12 P5.6 13 P0.1/AD1 14 P0.0/AD0 15 P5.7 16 VCC 17 NIC 18 P1.0/T2 19 P4.0 20 P1.1/T2EX/SS 21 P1.2/ECI 22 P1.3/CEX0 23 P4.1 24 P1.4/CEX1 25 P4 P2.4/A12 47 P2.3/A11 46 P4.7 45 P2.2/A10 44 P2.1/A9 43 P2.0/A8 42 P4.6 41 NIC VQFP64 40 VSS 39 P4 ...

Page 11

... As inputs, Port 1 pins that are externally 19, 20 pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51RD2/ED2 Port 1 include I/O P1.0: Input/Output I/O T2 (P1 ...

Page 12

... P5.0 - P5.7 63 10, 13, 16 RST AT89C51RD2/ED2 12 Type VQFP64 PDIL40 Name and Function 20 8 I/O P1.7: Input/Output: I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. ...

Page 13

... PSEN is not acti- vated during fetches from internal program memory External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If security level 1 is programmed, EA will be internally latched on Reset. AT89C51RD2/ED2 13 ...

Page 14

... Data AT89C51RD2/ED2 14 AT89C51RD2/ED2 I/O ports (P1, P2, P3, P4, P5) implement the quasi-bidirectional out- put that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possi- ble because when the port outputs a logic high weakly driven, allowing an external device to pull the pin low ...

Page 15

... Power-down Mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle Mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51RD2/ED2 CKRL4 CKRL3 CKRL2 POF ...

Page 16

... Functional Block Diagram Figure 4. Functional Oscillator Block Diagram F OSC Xtal1 Osc Xtal2 Prescaler Divider AT89C51RD2/ED2 16 Reload Reset CKRL 1 8-bit :2 0 Prescaler-Divider X2 CKCON0 • A hardware RESET puts the prescaler divider in the following state: • CKRL = FFh CLK CPU • Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: • ...

Page 17

... ALE disabling • Some enhanced features are also located in the UART and the Timer 2 The AT89C51RD2/ED2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...

Page 18

... Figure 6. Mode Switching Waveforms XTAL1 XTAL1:2 X2 Bit CPU Clock STD Mode AT89C51RD2/ED2 18 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 16) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode) ...

Page 19

... X2 and to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting cleared. Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”) Not bit addressable AT89C51RD2/ED2 SIX2 T2X2 T1X2 ...

Page 20

... AT89C51RD2/ED2 20 Table 17. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle ...

Page 21

... There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 18) that allows the program code to switch between them (Refer to Figure 7). 0 DPS DPTR1 DPH(83H) DPL(82H) AT89C51RD2/ED2 External Data Memory DPTR0 21 ...

Page 22

... AT89C51RD2/ED2 22 Table 18. AUXR1 Register AUXR1- Auxiliary Register 1(0A2h ENBOOT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Enable Boot Flash Cleared to disable boot ROM ...

Page 23

... DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C51RD2/ED2 23 ...

Page 24

... AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792 bytes (see Table 19). The AT89C51RD2/ED2 internal data memory is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...

Page 25

... The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings set, the read and write pulses are extended from clock periods. This is useful to access external slow peripherals. AT89C51RD2/ED2 25 ...

Page 26

... Registers AT89C51RD2/ED2 26 Table 19. AUXR Register AUXR - Auxiliary Register (8Eh DPU - M0 Bit Bit Number Mnemonic Description Disable Weak Pull-up 7 DPU Cleared by software to activate the permanent weak pull-up (default) Set by software to disable the weak pull-up (reduce power consumption) Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. ...

Page 27

... The Reset input can be used to force a reset pulse longer than the internal reset con- trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51RD2/ED2 datasheet. Figure 10. Reset Circuitry and Power-On Reset RST VSS a ...

Page 28

... Reset Output AT89C51RD2/ED2 28 As detailed in Section “Hardware Watchdog Timer”, page 86, the WDT generates a 96- clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit resistor must be added as shown Figure 11. ...

Page 29

... This is achieved by applying an internal reset to them. By gen erating the the Power Monito r insures a correct start up whe n AT89C51RD2/ED2 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...

Page 30

... Figure 13. Power Fail Detect Vcc Reset Vcc AT89C51RD2/ED2 30 The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure 13 below. When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input ...

Page 31

... Timer 2 Auto-reload Mode 4235E–8051–04/04 The Timer 2 in the AT89C51RD2/ED2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 20) and T2MOD (Table 21) registers. Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F external pin T2 (counter operation) as the timer clock input ...

Page 32

... Programmable Clock-output AT89C51RD2/ED2 32 Figure 14. Auto-reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH : 6 In the clock-out mode, Timer 2 operates as a 50% duty-cycle, programmable clock gen- erator (See Figure 15). The input clock increments TL2 at frequency F timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2 ...

Page 33

... Figure 15. Clock-out Mode C/ FCLK PERIPH T2 T2EX AT89C51RD2/ED2 TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 33 ...

Page 34

... Registers AT89C51RD2/ED2 34 Table 20. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1 ...

Page 35

... Timer 2 Output Enable bit 1 T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable AT89C51RD2/ED2 T2OE 1 0 DCEN 35 ...

Page 36

... Programmable Counter Array (PCA) AT89C51RD2/ED2 36 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...

Page 37

... The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR set when the PCA timer overflows. CIDL WDTE CF CR CCF4 CCF3 CCF2 CCF1 CCF0 AT89C51RD2/ED2 To PCA Modules Overflow Bit Up Counter CMOD ...

Page 38

... AT89C51RD2/ED2 38 Table 22. CMOD Register CMOD - PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable ...

Page 39

... PCA Module 0 interrupt flag 0 CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. Reset Value = 00X0 0000b Not bit addressable The watchdog timer function is implemented in Module 4 (See Figure 19). The PCA interrupt system is shown in Figure 17. AT89C51RD2/ED2 CCF4 CCF3 CCF2 1 0 CCF1 ...

Page 40

... Figure 17. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 AT89C51RD2/ED2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 ECF PCA Modules: each one of the five compare/capture modules has six possible func- tions. It can perform: • 16-bit Capture, positive-edge triggered • ...

Page 41

... Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt Cleared to disable compare/capture flag CCFn in the CCON register to generate 0 CCF0 an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. Reset Value = X000 0000b Not bit addressable AT89C51RD2/ED2 CAPNn MATn TOGn 1 0 PWMn ...

Page 42

... AT89C51RD2/ED2 42 Table 25. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 26 & ...

Page 43

... CH Value Reset Value = 0000 0000b Not bit addressable Table 29. CL Register CL - PCA Counter Register Low (0E9h Bit Bit Number Mnemonic Description PCA Counter Value Reset Value = 0000 0000b Not bit addressable AT89C51RD2/ED2 ...

Page 44

... Cex.n ECOMn 16-bit Software Timer/ Compare Mode AT89C51RD2/ED2 44 To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the mod- ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH) ...

Page 45

... PCA counter and the modules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 20). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. AT89C51RD2/ED2 CCON 0xD8 CCF3 ...

Page 46

... Figure 20. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Pulse Width Modulator Mode AT89C51RD2/ED2 CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...

Page 47

... Periodically change the compare value so it will never match the PCA timer. 2. Periodically change the PCA timer value so it will never match the compare values. 3. Disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. AT89C51RD2/ED2 CCAPnH CCAPnL “0” 8-bit Comparator “ ...

Page 48

... AT89C51RD2/ED2 48 The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA mod- ules are being used. Remember, the PCA timer is the time base for all modules; ...

Page 49

... Serial I/O Port Framing Error Detection 4235E–8051–04/04 The serial I/O port in the AT89C51RD2/ED2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...

Page 50

... Automatic Address Recognition Given Address AT89C51RD2/ED2 50 Figure 24. UART Timings in Modes 2 and 3 RXD D0 D1 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 The automatic address recognition feature is enabled when the multiprocessor commu- nication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame ...

Page 51

... On reset, the SADDR and SADEN registers are initialized to 00h the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. AT89C51RD2/ED2 51 ...

Page 52

... Registers Baud Rate Selection for UART for Mode 1 and 3 AT89C51RD2/ED2 52 Table 30. SADEN Register SADEN - Slave Address Mask Register (B9h Reset Value = 0000 0000b Not bit addressable Table 31. SADDR Register SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers ...

Page 53

... SPD • The baud rate for UART is token by formula: SMOD1 2 F PER Baud_Rate = (1-SPD (256 -BRL) SMOD1 2 F PER BRL = 256 - (1-SPD Baud_Rate AT89C51RD2/ED2 TBCK RBCK Clock Source (BDRCON) UART Timer Timer Timer Timer ...

Page 54

... AT89C51RD2/ED2 54 Table 33. SCON Register SCON - Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0=1 ) Clear to reset the error state, not cleared by a valid stop bit. FE Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit. ...

Page 55

... UART, thanks to the bit SRC located in BDRCON register (Table 42.) Table 36. SADEN Register SADEN - Slave Address Mask Register for UART (B9h Reset Value = 0000 0000b Table 37. SADDR Register SADDR - Slave Address Register for UART (A9h Reset Value = 0000 0000b AT89C51RD2/ED2 F = 24MHz OSC Error (%) BRL 1.23 243 1.23 230 1.23 217 1.23 204 0 ...

Page 56

... AT89C51RD2/ED2 56 Table 38. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 39. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b 4235E– ...

Page 57

... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. 0 CP/RL2# Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable AT89C51RD2/ED2 TCLK EXEN2 TR2 Description 1 0 ...

Page 58

... AT89C51RD2/ED2 58 Table 41. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 for UART 6 SMOD0 Cleared to select SM0 bit in SCON register. ...

Page 59

... Baud Rate Source select bit in Mode 0 for UART Cleared to select F 0 SRC mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. Reset Value = XXX0 0000b Not bit addressable AT89C51RD2/ED2 BRR TBCK RBCK /12 as the Baud Rate Generator (F OSC ...

Page 60

... Power Reduction Mode AT89C51RD2/ED2 60 The AT89C51RD2/ED2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes. ...

Page 61

... Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE.0 bit in KBIE register is set. Must be cleared by software. Reset Value = 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. AT89C51RD2/ED2 KBF4 KBF3 KBF2 1 ...

Page 62

... AT89C51RD2/ED2 62 Table 44. KBE Register KBE-Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit 6 KBE6 Cleared to enable standard I/O pin ...

Page 63

... Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value = 0000 0000b AT89C51RD2/ED2 KBLS4 KBLS3 KBLS2 1 ...

Page 64

... Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51RD2/ED2 64 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: • ...

Page 65

... SPR0 AT89C51RD2/ED2 . Clock Rate Baud Rate Divisor (BD CLK PERIPH F /4 CLK PERIPH F /8 CLK PERIPH F /16 CLK PERIPH F /32 CLK PERIPH F /64 CLK PERIPH F /128 CLK PERIPH Don’t Use (2) ...

Page 66

... Functional Description Operating Modes AT89C51RD2/ED2 66 Figure 30 shows a detailed structure of the SPI Module. Figure 30. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode ...

Page 67

... The SPI Module should be configured as a Slave before it is enabled (SPEN set). 3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). AT89C51RD2/ED2 MISO 8-bit Shift register MOSI SCK SS ...

Page 68

... Figure 33. Data Transmission Format (CPHA = 1) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 34. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) AT89C51RD2/ED2 MSB bit6 bit5 bit4 MSB bit6 bit5 bit4 1 2 ...

Page 69

... SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 35 gives a logical view of the above statements. AT89C51RD2/ED2 Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) ...

Page 70

... Registers Serial Peripheral Control Register (SPCON) AT89C51RD2/ED2 70 Figure 35. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs. • ...

Page 71

... Set by hardware to indicate that the SS pin is at inappropriate logic level. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit Reserved 2 - The value read from this bit is indeterminate. Do not set this bit. AT89C51RD2/ED2 SPR1 SPR0 Serial Peripheral Rate CLK PERIPH 0 ...

Page 72

... Serial Peripheral DATa Register (SPDAT) AT89C51RD2/ED2 72 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable The Serial Peripheral Data Register (Table 50 read/write buffer for the receive data register ...

Page 73

... Individual Enable 4235E–8051–04/04 The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI inter- rupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 36 ...

Page 74

... Registers AT89C51RD2/ED2 74 The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors addresses are the same as standard C52 devices. Table 51. Priority Level Bit Values IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’ ...

Page 75

... Table 52. Interrupt Sources and Vector Addresses Number Polling Priority Interrupt Source AT89C51RD2/ED2 Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART RI+TI Timer 2 TF2+EXF2 PCA CF + CCFn ( Keyboard KBDIT - - SPI SPIIT Vector Address ...

Page 76

... AT89C51RD2/ED2 76 Table 53. IENO Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit 6 EC Cleared to disable. Set to enable. Timer 2 overflow interrupt Enable bit ...

Page 77

... PX1L Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit 1 PT0L Refer to PT0H for priority level. External interrupt 0 Priority bit 0 PX0L Refer to PX0H for priority level. Reset Value = X000 0000b Bit addressable AT89C51RD2/ED2 PSL PT1L PX1L PT0L 1 0 PX0L 77 ...

Page 78

... AT89C51RD2/ED2 78 Table 55. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. PPCH PPCL PPCH ...

Page 79

... Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable bit Cleared to disable SPI interrupt. 2 ESPI Set to enable SPI interrupt. 1 Reserved Keyboard interrupt Enable bit 0 KBD Cleared to disable keyboard interrupt. Set to enable keyboard interrupt. Reset Value = XXXX X000b Bit addressable AT89C51RD2/ED2 ESPI KBD 79 ...

Page 80

... AT89C51RD2/ED2 80 Table 57. IPL1 Register IPL1 - Interrupt Priority Register (B2h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved 5 - The value read from this bit is indeterminate. Do not set this bit. ...

Page 81

... The value read from this bit is indeterminate. Do not set this bit. Keyboard interrupt Priority High bit KB DH KBDL KBDH Reset Value = XXXX X000b Not bit addressable AT89C51RD2/ED2 SPIH Priority Level Lowest Highest Priority Level Lowest Highest ...

Page 82

... AT89C51RD2/ED2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed. Note: If IDL bit and PD bit are set simultaneously, the AT89C51RD2/ED2 enters Power-Down mode. Then it does not go in Idle mode when exiting Power-Down mode. There are two ways to exit Idle mode: 1. Generate an enabled interrupt. – ...

Page 83

... Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51RD2/ED2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...

Page 84

... AT89C51RD2/ED2 84 pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Note: Exit from power-down by reset redefines all the RAM content. Table 59. Pin Conditions in Special Operating Modes Mode Port 0 ...

Page 85

... Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. 0 IDL Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. Reset Value= XXXX 0000b AT89C51RD2/ED2 GF1 GF0 PD 1 ...

Page 86

... Hardware Watchdog Timer Using the WDT AT89C51RD2/ED2 86 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H ...

Page 87

... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51RD2/ED2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...

Page 88

... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51RD2/ED2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 63 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...

Page 89

... Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable AT89C51RD2/ED2 switch-on. A warm start reset occurs while POF GF1 GF0 rises from 0 to its nominal voltage ...

Page 90

... Reduced EMI Mode AT89C51RD2/ED2 90 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches ...

Page 91

... EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading or writing. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Figure 38 represents the optimal write sequence to the on-chip EEPROM data memory. AT89C51RD2/ED2 91 ...

Page 92

... AT89C51RD2/ED2 92 Figure 38. Recommended EEPROM Data Write Sequence Exec: MOVX @DPTR, A EEPROM Data Write Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) Data Write DPTR= Address ACC= Data EEPROM Mapping EECON = 00h (EEE=0) Restore IT Last Byte to Load? ...

Page 93

... Set bit EEE of EECON register • Execute a MOVX A, @DPTR • Clear bit EEE of EECON register • Restore interrupts. Figure 39. Recommended EEPROM Data Read Sequence AT89C51RD2/ED2 EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) ...

Page 94

... Registers AT89C51RD2/ED2 94 Table 66. EECON Register EECON (0D2h) EEPROM Control Register Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to ...

Page 95

... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51RD2/ED2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. AT89C51RD2/ED2 ...

Page 96

... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51RD2/ED2 is called Hardware Security Byte (HSB). Table 67. Hardware Security Byte (HSB) 7 ...

Page 97

... These registers are in the "Extra Flash Memory" part of the Flash memory. This block is also called "XAF" or eXtra Array Flash. They are accessed in the following ways: • Commands issued by the parallel memory programmer. • Commands issued by the ISP software. • Calls of API issued by the application software. Several software registers are described in Table 69. AT89C51RD2/ED2 97 ...

Page 98

... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 71. Default value Description FCh 0FFh FFh 58h Atmel D7h C51 X2, Electrically Erasable ECh AT89C51RD2/ED2 64KB AT89C51RD2/ED2 64KB, EFh Revision LB1 1 0 LB0 ...

Page 99

... P: Programmed or "zero" level not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C51RD2/ED2 parts are delivered in standard with the ISP ROM bootloader. After ISP or parallel programming, the possible contents of the Flash memory are sum- marized in Figure 40: Application ...

Page 100

... Specific Protocol Access From User Application Acronyms AT89C51RD2/ED2 100 The bootloader manages communication according to a specifically defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. Bootloader ISP: In-System Programming ...

Page 101

... Results are returned in the registers. The pur- pose on this process is to translate the registers values into internal Flash Memory Management. • Flash Memory Management This process manages low level access to Flash memory (performs read and write access). AT89C51RD2/ED2 User Application User Call Management (API) 101 ...

Page 102

... Bootloader Functionality Figure 43. Hardware conditions typical sequence during power-on. AT89C51RD2/ED2 102 The bootloader can be activated by two means: Hardware conditions or regular boot process. The Hardware conditions ( PSEN = 0) during the Reset# falling edge force the on-chip bootloader execution. This allows an application to be built that will normally execute the end user’ ...

Page 103

... ENBOOT Bit (AUXR1) is Cleared Yes (PSEN = and ALE =1 or Not Connected) FCON = 00h Hardware Condition? FCON = F0h BLJB = 1 BLJB!= 0 ENBOOT = 0 ? BLJB = 0 ENBOOT = 1 F800h Yes = Hardware Boot FCON = 00h ? BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h AT89C51RD2/ED2 Conditions Atmel BOOT LOADER 103 ...

Page 104

... ISP Protocol Description Physical Layer Frame Description AT89C51RD2/ED2 104 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader to compute the baudrate chosen by the host ...

Page 105

... Info Bootloader Info Read-only access allowed Erase Block Allowed Full Chip Erase Allowed Blank Check Allowed AT89C51RD2/ED2 Level 1 Level 2 Read-only access allowed Any access not allowed Read-only access allowed Any access not allowed Read-only access allowed Any access not allowed Write level 2 allowed ...

Page 106

... Full Chip Erase Checksum Error Flow Description Overview Communication Initialization AT89C51RD2/ED2 106 The ISP command "Full Chip Erase" erases all user Flash memory (fills with FFh) and sets some bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • ...

Page 107

... The ISP itia AT89C51RD2/ED2 to establish the baud rate. Table show the autobaud capability ...

Page 108

... Figure 47. Command Flow Host Sends First Character of the Frame Sends Frame (made of 2 ASCII Characters Per Byte) Echo Analysis AT89C51RD2/ED2 108 Bootloader ":" If (not received ":") ":" Else Sends Echo and Start Reception Gets Frame, and Sends Back Echo for Each Received Byte 4235E– ...

Page 109

... CR & 0010 0010 0000 0000 F5 0000 0000 AT89C51RD2/ED2 Bootloader Wait Write Command Checksum Error Send Checksum Error NO_SECURITY Send Security Error ...

Page 110

... Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not Erased COMMAND FINISHED Example AT89C51RD2/ED2 110 Blank Check Command ’X’ & CR & LF ’.’ & CR & LF address & CR & HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF 01 78 ...

Page 111

... D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 BOOTLOADER 0000=-----data------ CR LF (16 data) 0010=-----data------ CR LF (16 data) BOOTLOADER BOOTLOADER 0020=data CR LF AT89C51RD2/ED2 Bootloader Wait Display Command Checksum error Send Checksum Error RD_WR_SECURITY Send Security Error Read Data All Data Read ...

Page 112

... Wait Checksum Error COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED Example AT89C51RD2/ED2 112 This flow is similar for the following frames: • Reading Frame • EOF Frame/ Atmel Frame (only reading Atmel Frame) Read Command ’X’ & CR & LF ’ ...

Page 113

... AT89C51RD2/ED2 Command Effect Program Nb Code Byte. Bootloader will accept up to 128 (80h) data bytes. The data bytes should be 128 byte page flash boundary. Erase block0 (0000h-1FFFh) Erase block1 (2000h-3FFFh) Erase block2 (4000h-7FFFh) Erase block3 (8000h- BFFFh) ...

Page 114

... Example of Flash_api routines are available on the Atmel web site on the software appli- cation note: C Flash Drivers for the AT89C51RD2/ED2 The API calls description and arguments are shown in Table 76. The application selects an API by setting R1, ACC, DPTR0 and DPTR1 registers. ...

Page 115

... XXh 0004h XXh XXXXh XXh DPL = 00h XXh DPL = 01h XXh XXXXh XXh AT89C51RD2/ED2 Returned Value Command Effect Set SSB level 1 Set SSB level 2 ACC = SSB value Set SSB level 0 Set SSB level 1 none Program boot status byte none Program software boot vector ...

Page 116

... V Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports AT89C51RD2/ED2 116 Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...

Page 117

... 0 1 200 RST = V (see Figure 53 must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89C51RD2/ED2 Max Unit (5) 250 k - -650 150 A 0.4 x Frequency (MHz ...

Page 118

... AT89C51RD2/ED2 118 Figure 52. I Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 53. I Test Condition, Idle Mode CC V RST EA XTAL2 (NC) CLOCK XTAL1 SIGNAL V SS Figure 54. I Test Condition, Power-down Mode ...

Page 119

... Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In PLIV T Input Instruction Hold After PSEN PXIX T Input Instruction Float After PSEN PXIZ T Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ AT89C51RD2/ED2 119 ...

Page 120

... AT89C51RD2/ED2 120 Table 78. AC Parameters for a Fix Clock Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Table 79. AC Parameters for a Variable Clock Symbol Type Standard Clock T Min LHLL T Min AVLL T Min LLAX T Max ...

Page 121

... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data Set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51RD2/ED2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 121 ...

Page 122

... AT89C51RD2/ED2 122 Table 81. AC Parameters for a Fix Clock Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T RLAZ T WHLH Table 82. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min RLRH T Min WLWH T Max ...

Page 123

... Serial port clock cycle time XLXL T Output data set-up to clock rising edge QVHX T Output data hold after clock rising edge XHQX T Input data hold after clock rising edge XHDX T Clock rising edge to input data valid XHDV AT89C51RD2/ED2 T WHLH T WLWH T T QVWH DATA OUT T WHLH T RLRH T ...

Page 124

... Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AT89C51RD2/ED2 124 Table 84. AC Parameters for a Fix Clock Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 85. AC Parameters for a Variable Clock Standard Symbol ...

Page 125

... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V occurs mA Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51RD2/ED2 0 0 0.5 for a logic “1” and 0.45V for a logic “0”. ...

Page 126

... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51RD2/ED2 126 STATE5 STATE6 ...

Page 127

... Temperature Supply Voltage Range 2.7V - 5.5V Industrial AT89C51RD2/ED2 Package Packing Product Marking PLCC44 Stick AT89C51RD2-IM VQFP44 Tray AT89C51RD2-IM VQFP64 Tray AT89C51RD2-IM PLCC68 Stick AT89C51RD2-IM PLCC44 Stick AT89C51ED2-IM VQFP44 Tray AT89C51ED2-IM PDIL40 Stick AT89C51ED2-IM PLCC68 Stick AT89C51ED2-IM VQFP64 Tray AT89C51ED2-IM 127 ...

Page 128

... Packaging Information PLCC44 AT89C51RD2/ED2 128 4235E–8051–04/04 ...

Page 129

... VQFP44 4235E–8051–04/04 AT89C51RD2/ED2 129 ...

Page 130

... PLCC68 AT89C51RD2/ED2 130 4235E–8051–04/04 ...

Page 131

... VQFP64 4235E–8051–04/04 AT89C51RD2/ED2 131 ...

Page 132

... PDIL40 AT89C51RD2/ED2 132 4235E–8051–04/04 ...

Page 133

... Added Flash write programming time specification. 1. Changed maximum frequency to 60 MHz in X1 mode and 30 MHz in X2 mode for Vcc = 4.5V to 5.5V and internal code execution. 2. Added PDIL40 Packaging for AT89C51ED2. 1. Improved explanations throughout the document. 1. Improved explanations throughout the document. AT89C51RD2/ED2 + 1 0.9. CC 133 ...

Page 134

... Table of Contents AT89C51RD2/ED2 i Features ................................................................................................. 1 Description ............................................................................................ 1 Block Diagram ....................................................................................... 3 SFR Mapping ......................................................................................... 4 Pin Configurations ................................................................................ 9 Port Types ........................................................................................... 14 Oscillator ............................................................................................. 15 Registers............................................................................................................. 15 Functional Block Diagram ...................................................................................16 Enhanced Features ............................................................................. 17 X2 Feature .......................................................................................................... 17 Dual Data Pointer Register (DPTR) ................................................... 21 Expanded RAM (XRAM) ..................................................................... 24 Registers............................................................................................................. 26 Reset .................................................................................................... 27 Introduction ......................................................................................................... 27 Reset Input ......................................................................................................... 27 Reset Output .......................................................................................................28 Power Monitor ..................................................................................... 29 Description.......................................................................................................... 29 Timer 2 ................................................................................................. 31 Auto-reload Mode ...

Page 135

... WDT during Power-down and Idle...................................................................... 87 ® ONCE Mode (ON- Chip Emulation) .................................................. 88 Power-off Flag ..................................................................................... 89 Reduced EMI Mode ............................................................................. 90 EEPROM Data Memory ....................................................................... 91 Write Data........................................................................................................... 91 Read Data........................................................................................................... 93 Registers............................................................................................................. 94 Flash/EEPROM Memory ..................................................................... 95 Features.............................................................................................................. 95 Flash Programming and Erasure ........................................................................ 95 Flash Registers and Memory Map...................................................................... 96 Flash Memory Status.......................................................................................... 99 Memory Organization ......................................................................................... 99 AT89C51RD2/ED2 ii ...

Page 136

... Packaging Information ..................................................................... 128 PLCC44 ............................................................................................................ 128 VQFP44 ............................................................................................................ 129 PLCC68 ............................................................................................................ 130 VQFP64 ............................................................................................................ 131 PDIL40.............................................................................................................. 132 Datasheet Change Log for AT89C51RD2/ED2 ............................... 133 Changes from 4235A -04/03 to 4135B - 06/03 ................................................. 133 Changes from 4235B -06/03 to 4235C - 08/03................................................. 133 Changes from 4235C - 08/03 to 4235D - 12/03................................................ 133 Changes from 4235D - 12/03 to 4235E - 04/04................................................ 133 Table of Contents .................................................................................. i ...

Page 137

... FAX (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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