X25330 Xicor, X25330 Datasheet

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X25330

Manufacturer Part Number
X25330
Description
Manufacturer
Xicor
Datasheet

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FUNCTIONAL DIAGRAM
7048–1.0 6/18/97 T0/C0/D0 SH
Direct Write
FEATURES
32K
Xicor, Inc. 1994 - 1997 Patents Pending
5MHz Clock Rate
Low Power CMOS
2.5V To 5.5V Power Supply
SPI Modes (0,0 & 1,1)
4K X 8 Bits
Block Lock™ Protection
Programmable Hardware Write Protection
Built-in Inadvertent Write Protection
Self-Timed Write Cycle
High Reliability
Packages
<5mA Active Current
<1 A Standby Current
32 Byte Page Mode
Protect 1/4, 1/2 or all of E
In-Circuit Programmable ROM Mode
Power-Up/Down protection circuitry
Write Enable Latch
Write Protect Pin
5ms Write Cycle Time (Typical)
Endurance: 100,000 cycles
Data Retention: 100 Years
ESD protection: 2000V on all pins
8-Lead SOIC
14-Lead TSSOP
and Block Lock
HOLD
SCK
SO
CS
WP
SI
5MHz SPI Serial E
Protection is a trademark of Xicor, Inc.
COMMAND
REGISTER
CONTROL
CONTROL
DECODE
ST ATUS
TIMING
WRITE
LOGIC
LOGIC
AND
AND
2
PROM Array
PROTECT
WRITE
LOGIC
2
PROM with Block Lock
X25330
1
DESCRIPTION
The X25330 is a CMOS 32K-bit serial E
nally organized as 4K x 8. The X25330 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing
any number of devices to share the same bus.
The X25330 also features two additional inputs that
provide the end user with added flexibility. By
asserting the HOLD input, the X25330 will ignore tran-
sitions on its inputs, thus allowing the host to service
higher priority interrupts. The WP input can be used as
a hardwire input to the X25330 disabling all write
attempts to the status register, thus providing a mech-
anism for limiting end user capability of altering 0, 1/4,
1/2 or all of the memory.
The X25330 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
X DECODE
LOGIC
64
32
32
32
TM
DATA REGISTER
Y DECODE
64 X 256
4K BYTE
32 X 256
32 X 256
Protection
ARRAY
Characteristics subject to change without notice
8
7037 FRM F01
4K x 8 Bit
2
PROM, inter-
TM

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X25330 Summary of contents

Page 1

... PROM with Block Lock DESCRIPTION The X25330 is a CMOS 32K-bit serial E nally organized The X25330 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines ...

Page 2

... The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25330 in a system with WP pin grounded and still be able to write to the status register. The WP pin func- tions will be enabled when the WPEN bit is set “1”. ...

Page 3

... WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25330 is busy with a write operation. When set to a “1”, a write is in progress, when set to a “0”, no write is in progress. During a write, all other bits are set to “1”. ...

Page 4

... This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write bytes of data to the X25330. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will “ ...

Page 5

... CS 0 SCK SI HIGH IMPEDANCE SO Operational Notes The X25330 powers-up in the following state: ) under normal IH • The device is in the low power standby state. • A HIGH to LOW transition required to enter an active state and receive an instruction. • SO pin is high impedance. • The “write enable” latch is reset. ...

Page 6

... X25330 Figure 3. Write Enable Latch Sequence CS SCK SI SO Figure 4. Byte Write Operation Sequence SCK INSTRUCTION SI HIGH IMPEDANCE HIGH IMPEDANCE BIT ADDRESS 7037 FRM F05 ...

Page 7

... X25330 Figure 5. Page Write Operation Sequence SCK INSTRUCTION SCK DATA BYTE Figure 6. Write Status Register Operation Sequence CS SCK SI HIGH IMPEDANCE BIT ADDRESS ...

Page 8

... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Max. Supply Voltage +70 C X25330 +85 C X25330-2.5 7037 FRM T06 Limits Units Min. Max – ...

Page 9

... X25330 EQUIVALENT A.C. LOAD CIRCUIT 5V 1.44K OUTPUT OUTPUT 1.95K 100pF A.C. OPERATING CHARACTERISTICS Data Input Timing Symbol f Clock Frequency SCK t Cycle Time CYC t CS Lead Time LEAD t CS Lag Time LAG t Clock HIGH Time WH t Clock LOW Time WL t Data Setup Time SU t Data Hold Time ...

Page 10

... X25330 Serial Output Timing CS SCK MSB OUT ADDR SI LSB IN Serial Input Timing CS t LEAD SCK MSB IN HIGH IMPEDANCE CYC MSB–1 OUT LAG DIS LSB OUT 7037 FRM F10 LAG t FI LSB IN ...

Page 11

... X25330 Hold Timing CS SCK SO SI HOLD 7037 FRM F12 11 ...

Page 12

... X25330 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7 0.050 (1.27 0.0075 (0.19) 0.250" 0.010 (0.25) FOOTPRINT 12 0.150 (3.80) 0.228 (5.80) 0.158 (4.00) ...

Page 13

... X25330 PACKAGING INFORMATION 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V 0 – 8 See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS) .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) .010 (.25) Gage Plane Seating Plane .019 (.50) ...

Page 14

... CC Blank = 5V 10% 2.5 = 2.5 to 5.5V Temperature Range Blank = Commercial = + Industrial = – +85 C Package S8 = 8-Lead SOIC V14 = 14-Lead TSSOP X25330 X Blank = 8-Lead SOIC V = 14-Lead TSSOP X Blank = 10%, – + 2.5V to 5.5V 2.5V to 5.5V, – + ...

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