21285AB Intel Corporation, 21285AB Datasheet

no-image

21285AB

Manufacturer Part Number
21285AB
Description
Manufacturer
Intel Corporation
Datasheet

Specifications of 21285AB

Case
BGA

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
21285AB
Manufacturer:
INTEL
Quantity:
5 510
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
21285AB
Manufacturer:
ROCKWELL
Quantity:
5 510
Price:
21285 Core Logic for SA-110
Microprocessor
Datasheet
September 1998
Order Number:
278115-001

Related parts for 21285AB

21285AB Summary of contents

Page 1

Core Logic for SA-110 Microprocessor Datasheet September 1998 Order Number: 278115-001 ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. ...

Page 3

Contents 1 Introduction.....................................................................................................................1–1 1.1 Features ............................................................................................................1–1 1.1.1 Power Management .............................................................................1–2 1.2 System Applications ..........................................................................................1–2 2 Signal Description ..........................................................................................................2–1 2.1 PCI Signals........................................................................................................2–1 2.2 SA-110 Signals..................................................................................................2–3 2.3 ROM Signals .....................................................................................................2–5 2.4 SDRAM Signals.................................................................................................2–5 2.5 Serial Port Signals.............................................................................................2–7 2.6 Miscellaneous Signals.......................................................................................2–7 2.7 X-Bus/Arbiter ...

Page 4

Unsupported PCI Cycles As Target ..................................................... 3–7 3.2.2 Memory Write to SDRAM ..................................................................... 3–7 3.2.3 Memory Read, Memory Read Line, Memory Read Multiple to SDRAM ................................................................................................ 3–9 3.2.4 Type 0 Configuration Write ................................................................ 3–10 3.2.5 Type 0 Configuration Read ...

Page 5

Reads ...................................................................................................4–7 4.2.3 Writes ...................................................................................................4–7 4.2.4 Timing...................................................................................................4–7 4.2.5 Blank ROM Programming ....................................................................4–8 5 SA-110 Operation...........................................................................................................5–1 5.1 SA-110 Control..................................................................................................5–1 5.1.1 Address Map Partitioning .....................................................................5–1 5.1.2 Byte Enables ........................................................................................5–2 5.1.3 SA-110 Bus Arbiter...............................................................................5–2 5.2 X-Bus Interface..................................................................................................5–3 5.2.1 Address and Data Bus ...

Page 6

Registers ........................................................................................................................ 7–1 7.1 PCI Configuration Space Registers .................................................................. 7–1 7.1.1 Vendor ID Register—Offset 00h .......................................................... 7–2 7.1.2 Device ID Register—Offset 02h ........................................................... 7–2 7.1.3 Command Register—Offset 04h .......................................................... 7–3 7.1.4 Status Register—Offset 06h ................................................................ 7–5 7.1.5 Revision ID ...

Page 7

CSR Base Address Offset Register—Offset FCh ..............................7–27 7.3.9 SDRAM Base Address Mask Register—Offset 100h .........................7–27 7.3.10 SDRAM Base Address Offset Register—Offset 104h ........................7–28 7.3.11 Expansion ROM Base Address Mask Register—Offset 108h............7–29 7.3.12 SDRAM Timing Register—Offset 10Ch .............................................7–31 7.3.13 SDRAM ...

Page 8

PCI Signal Timing Specifications ......................................................... 9–4 9.4.3 PCI Reset Timing Specifications .......................................................... 9–5 9.4.4 JTAG Timing Specifications ................................................................. 9–6 9.5 Memory and SA-110 Interface Timing .............................................................. 9–6 9.5.1 SA-110, 21285, and SDRAM Clock Signal Timing Specifications ....... 9–7 9.5.2 ...

Page 9

Miscellaneous Signals.......................................................................................2–7 2-10 X-Bus Signals....................................................................................................2–9 2-11 PCI Arbiter Signals ..........................................................................................2–10 2-12 JTAG Signals ..................................................................................................2–10 2-13 Pin State at Reset ...........................................................................................2–11 2-14 21285 PBGA Location Pin List ........................................................................2–13 2-15 21285 Pin Name Pin List.................................................................................2–17 3-1 SDRAM Address Generation ...........................................................................3–8 3-2 ...

Page 10

...

Page 11

Introduction Intel Semiconductor’s 21285 is a single-chip interface between an SA-110 microprocessor, synchronous DRAM memory (SDRAM), read-only memory (ROM), and the PCI bus designed to support the following three modes of operation: • PCI-based SA-110 computer. In this ...

Page 12

Introduction • PCI bus arbiter • Supports both 5-V and 3.3-V signaling environments • Provides an IEEE standard 1149.1 JTAG interface 1.1.1 Power Management The 21285 REV_ID 4 or higher provides support to enable applications to be compliant with the ...

Page 13

Figure 1-2. SA-110 Coprocessor Application Diagram SDRAM/ ROM SA-110 Figure 1-3 shows an application diagram of the intelligent add-in card system. In this system: • SA-110 is an embedded controller on add-in card. • Host CPU configures all PCI devices. ...

Page 14

...

Page 15

Signal Description The 21285 signals are categorized into one of several groups: PCI, SA-110, ROM, SDRAM, serial port, miscellaneous, X-Bus/Arbiter, and JTAG. Table 2-1 defines the PCI and SA-110 signal-type abbreviations used in the signal tables. These abbreviations use the ...

Page 16

Signal Description Table 2-2. PCI Bus Interface Signals Signal Name frame_l irdy_l trdy_l stop_l devsel_l idsel perr_l serr_l req_l gnt_l pci_irq_l pci_rst_l 2-2 Type Description STS Frame. frame_l indicates the beginning and duration of an access. The 21285 receives as ...

Page 17

Table 2-2. PCI Bus Interface Signals Signal Name pci_clk pci_cfn Vio a. The value on this pin may be read via the SA-110 control register. 2.2 SA-110 Signals The timing of the SA-110 signals is referenced to the MCLK. signals ...

Page 18

Signal Description Table 2-3. SA-110 Signals Connected to the 21285 Signal Name Type LOCK IC ABE OCZ DBE OCZ nIRQ OCZ nFIQ OCZ nRESET ICOCZ MCLK OCZ Table 2-4. SA-110 Signals Not Connected to the 21285 Signal Name nWAIT MSE ...

Page 19

ROM Signals Table 2-5 describes signal outputs that are used for accessing the ROM. Refer to additional ROM address bit connections. While the ROM is being accessed, signal rom_ce_l is asserted. Refer to Section 4.2 Table 2-5. ROM Signals ...

Page 20

Signal Description Table 2-6. SDRAM Signals (Sheet Signal Name Type d_wren_l OCZ parity[3:0] ICOCZ sdclk[3:0] OCZ Table 2-7 describes the ma signals that are inputs when nRESET is asserted, and are latched at the deassertion of nRESET. ...

Page 21

Table 2-7. ma Signals (Sheet Signal Name Type ma[5:4] ICOCZ ma[3] ICOCZ ma[2] ICOCZ 2.5 Serial Port Signals Table 2-8 describes the serial port signals . Table 2-8. Serial Port Signals Signal Name Type ...

Page 22

Signal Description Table 2-9. Miscellaneous Signals (Sheet Signal Name fclk_in irq_in_l[3:0] scan_en Figure 2-1. Clock Generation 3.68 MHz Note: fclk to fclk_in connection on PC board. All clock etch lengths for fclk, MCLK, and sdclk should be ...

Page 23

X-Bus Selection X-Bus (ma[7]= general-purpose parallel interface port that allows connection of 8- and 16-bit peripheral chips. The address to the peripherals is supplied by A[31:0] (or possibly a buffered version of this signal depending upon the ...

Page 24

Signal Description 2.7.2 PCI Arbiter Selection The PCI arbiter (ma[7]=0) receives requests from five potential bus masters (four external and the 21285), and asserts a grant to the master with the highest priority. See of the PCI arbiter operation. Table ...

Page 25

Pin State During Reset Table 2-13 defines the state of both the output (O) and bidirectional (TS) pins during reset. SA-110 related pins are controlled by nRESET and PCI related pins are controlled by pci_rst_l. Table 2-13. Pin State ...

Page 26

Signal Description Table 2-13. Pin State at Reset Signal Name Type xior_l TS xiow_l TS xcs_l TS tdo O 2.10 Pin Assignment This section describes the 21285 pin assignment and lists the pins according to location (numeric) and in alphabetic ...

Page 27

Pins Listed in Numeric Order Table 2-14 lists the 21285 pins in order of location (numeric), showing the location code, name, and signal type of each pin. Figure 2-2 provides the map for identifying the pin location codes, listed ...

Page 28

Signal Description Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location C19 MCLK D1 Vss D3 ma[12] D5 D[2] D7 Vss D9 parity[1] D11 Vdd D13 Vss D15 Vdd D17 Vss D19 osc E1 ma[7] E3 ma[9] E17 ...

Page 29

Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location L17 Vdd L19 A[14] M1 d_wren_l M3 cmd[1] M17 A[18] M19 A[16] N1 rom_ce_l N3 tdi N17 Vss N19 Vss P1 tdo P3 tck P17 A[26] P19 A[22] R1 ...

Page 30

Signal Description Table 2-14. 21285 PBGA Location Pin List PBGA Pin Name Location V11 Vdd V13 ad[14] V15 ad[8] V17 ad[3] V19 Vio W1 gnt_l W3 ad[31] W5 ad[24] W7 Vss W9 cbe_l[2] W11 Vss W13 ad[15] W15 ad[10] W17 ...

Page 31

Pins Listed in Alphabetic Order Table 2-15 lists the 21285 pins in alphabetic order, showing the name, location code, and signal type of each pin. Figure 2-2 provides the map for identifying the pin location codes. Table 2-1 defines ...

Page 32

Signal Description Table 2-15. 21285 Pin Name Pin List Pin Name ad[27] ad[28] ad[29] ad[30] ad[31] ba[0] ba[1] cbe_l[0] cbe_l[1] cbe_l[2] cbe_l[3] CLF cmd[0] cmd[1] cmd[2] cs_l[0] cs_l[1] cs_l[2] cs_l[3] D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] ...

Page 33

Table 2-15. 21285 Pin Name Pin List Pin Name ma[5] ma[6] ma[7] ma[8] ma[9] ma[10] ma[11] ma[12] MAS[0] MAS[1] MCLK nFIQ nIRQ nMREQ nRESET nRW osc par parity[0] parity[1] parity[2] parity[3] pci_cfn pci_clk pci_gnt_l[0] pci_irq_l pci_req_l[3] pci_rst_l perr_l req_l rom_ce_l ...

Page 34

Signal Description Table 2-15. 21285 Pin Name Pin List Pin Name Vdd Vdd Vdd Vdd Vio Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 2-20 PBGA Type Pin Name ...

Page 35

Transactions All 21285 transactions occur between the SA-110, PCI, SDRAM, ROM, and X-Bus. Figure 3-1 shows the three FIFOs used in performing the various transactions. • Outbound FIFO (256 bytes) — SA-110 write addresses and data for PCI — SA-110 ...

Page 36

Transactions The CSR address space is listed in Tables 7-2, 7-3, and 7-4. Figure 3-1. 21285 Block Diagram SA-110 Control D[31:0] SA-110 Interface A[31:0] SDRAM Control 3.1.3 SDRAM All-Banks Precharge An SA-110 read from one of the four SDRAM array ...

Page 37

SDRAM Mode Register Set SDRAM mode register set occurs in response to an SA-110 write to one of four SDRAM array mode regions. SDRAMs require the mode register to be written after power-up and prior to accessing the SDRAM. ...

Page 38

Transactions 3.1.9 PCI Memory Write The SA-110 address, write data, and byte masks are collected into the Outbound FIFO and written to PCI memory space at a later time. If there is room in the FIFO, the SA-110 stalls for ...

Page 39

PCI I/O Read The SA-110 is stalled while PCI controller performs PCI I/O read. It becomes unstalled when the read data is returned and driven to the D[31:0]. During the wait time, PCI write data in the Inbound FIFO ...

Page 40

Transactions 3.1.18 X-Bus Read The SA-110 is stalled while the 21285 performs the read from the X-Bus device. It becomes unstalled when the read data is returned and driven to the D[31:0] (the software must be aware of the width ...

Page 41

Note: Some master devices, such as Intel Semiconductor’s 21150, 21152, 21153, and 21154 PCI-to-PCI Bridge chips, discard a transaction after 2 implies that the SA-110 should set the initialize complete bit before that time. The following sections describe the target ...

Page 42

Transactions Figure 3-2. Mapping PCI Address to SDRAM Address 4GB PCI Address Space Window Size 0 Table 3-1 describes how the SDRAM address is derived from the PCI address. Note: If the match is to the SDRAM base address register, ...

Page 43

Memory Read, Memory Read Line, Memory Read Multiple to SDRAM PCI memory read from SDRAM occurs if the PCI address matches the SDRAM base address register (at offset 18h) or the CSR base address register (at offset 10h with ...

Page 44

Transactions If the delayed read latch is full and a new read to a different address is attempted, that read gets a retry and no change is made in the delayed read latch. In other words, the new read does ...

Page 45

Write to CSR PCI write to a CSR occurs if either of the following conditions are satisfied: • The PCI address matches the CSR memory base address register (see PCI command is either a memory write or memory write ...

Page 46

Transactions This read is completed as a delayed read. On the first occurrence of the read, the 21285 signals a retry to the PCI master. If the delayed read latch is not full, the 21285 latches the address and command, ...

Page 47

When the address reaches the head of the FIFO, the 21285 reads the ROM. The ROM is read from one to four times, depending on the ROM width setting in the SA-110 control register, and the data is collected and ...

Page 48

Transactions Note that the SA–110 software must ensure that writes to the address registers and the actual loads and stores to PCI DAC space are performed as atomic operations. The following methods can provide this atomicity: • Have each routine ...

Page 49

The PCI byte enables for each data phase are derived from the SA-110 A/MAS signals. The length of the burst is determined by how much sequential data was collected into the Outbound FIFO (see Section 3.1.9). 3.3.2.2 From DMA PCI ...

Page 50

Transactions 3.3.3.1 From SA-110 PCI memory reads are done when the SA-110 performs reads from the memory space. The actual PCI command used is based on whether or not there is a match to the prefetchable PCI range register. For ...

Page 51

The following general rules apply to the command transactions: • If the 21285 receives a target retry response, it repeats the I/O write command at the first opportunity. • If the 21285 receives a master abort, it discards the write ...

Page 52

Transactions Table 3-5. Configuration Address Generation Bits Description 31:11 Derived from the following decodes (Cont.): (Cont.) 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 SA-110 A[15:11] 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 through ...

Page 53

Configuration Read Configuration read is completed when the SA-110 address is in the PCI configuration space. Table 3-5 shows how the PCI address is derived from the configuration address. The PCI byte enables for each data phase are derived ...

Page 54

Transactions When the 21285 requests the PCI bus, it performs a PCI transaction when gnt_l is received. Once req_l is asserted, the 21285 never deasserts it prior to receiving gnt_l (nor deasserts it after receiving gnt_l without doing a transaction). ...

Page 55

Write Data Parity Error A write data parity error is detected when the par that is received by the 21285 does not match the expected parity for data and byte enables. This causes the following actions to occur: • ...

Page 56

Transactions 3.4.2.2 Write Data Parity Error A write data parity error occurs when the PCI target asserts perr_l in response to write data driven by the 21285. This causes the following actions to occur: • If the command register parity ...

Page 57

SDRAM and ROM Operation This chapter describes the operation of the SDRAM and ROM. 4.1 SDRAM Control The SDRAM controller on the 21285 controls from one to four arrays of synchronous DRAMs (SDRAMs). SDRAM supported parts include: 8Mb, 16Mb, and ...

Page 58

SDRAM and ROM Operation Mode register set is generated in response to an SA-110 write to a specified address space (see Section 5.1.1). The mode register of the SDRAMs must be written before any SDRAM writes or reads can be ...

Page 59

Note: “—” in Table 4-2 indicates that the address is not used by the SDRAM in this configuration. The pin is driven by the 21285 and its value can be either Note: “ap” in Table 4-2 indicates ...

Page 60

SDRAM and ROM Operation Table 4-3. SDRAM Commands SDRAM Command Bank activate Write Read 4.1.3 Parity The SDRAM can be optionally protected by byte parity. Parity is enabled by bit [12] in the SDRAM timing register. When parity is enabled, ...

Page 61

ROM Control Figure 4-2 shows the ROM configuration. The ROM output enable and write enable are connected to address bits [30:31] respectively. The ROM address is connected to address bits [24:2]. Figure 4-2. ROM Configuration SA-110 This section describes ...

Page 62

SDRAM and ROM Operation Table 4-4. ROM Addressing ROM Width Byte Word (2 bytes) Dword (4 bytes) During ROM accesses from the SA-110, the 21285 latches the address and drives it back onto A. Table 4-5 shows how the ROM ...

Page 63

Reads During ROM reads, the 21285 asserts rom_ce_l and A[30], which should be connected to the ROM output enable (oe_l) signal. For reads from a byte-wide ROM, the 21285 performs the following: • Sequences A[29:28] with values 3,2,1,0 • ...

Page 64

SDRAM and ROM Operation All ROM address, data, and control signals are controlled synchronously to fclk_in. The ROM read timing is as follows: • At the start of the cycle, the address is driven and rom_ce_l is asserted. • After ...

Page 65

SA-110 Operation This chapter describes the operation of the following: • SA-110 interface • X-Bus interface • Ordering and deadlock avoidance 5.1 SA-110 Control This section provides descriptions for the following: • Address map partitioning • Byte enables • SA-110 ...

Page 66

SA-110 Operation Table 5-1. SA-110 4GB Address Mapping Function X-Bus XCS1 X-Bus XCS2 X-Bus no CS Reserved ROM CSR space Reserved SA-110 cache flush Reserved Outbound write flush PCI IACK/special space PCI type 1 configuration PCI type 0 configuration PCI ...

Page 67

Post write to PCI — Read X-Bus — Write X-Bus • PCI operations (that come through the Inbound FIFO) — Read SDRAM (nonprefetch) — Read SDRAM (prefetch) — Write SDRAM — Read ROM — Write ROM • DMA operations ...

Page 68

SA-110 Operation Figure 5-1. X-Bus Configuration D[31:0] SA-110 5.2.1 Address and Data Bus Generation The X-Bus address and data buses are generated by buffering the address and data buses (A and D). Low voltage TTL buffers must be used for ...

Page 69

Device Support The X-Bus can support 8-bit, 16-bit, and 32-bit devices. An 8-bit peripheral device data bus is wired to the low-order byte lane of the buffered D bus. A 16-bit peripheral device data bus is wired to the ...

Page 70

SA-110 Operation Figure 5-2. X-Bus Timing xior_l, xiow_l D (write) X-Bus Device Data (Read) On reads, the X-Bus device drives read data to the SA-110, and the 21285 unstalls the SA-110 after the cycle count has expired. On writes, the ...

Page 71

Inbound FIFO — SA-110 read data and prefetch read data from PCI — PCI to SDRAM/ROM write data — PCI to SDRAM DMA • PCI read FIFO — PCI read data from SDRAM/ROM 5.3.2 Ordering Rules The following ordering ...

Page 72

...

Page 73

Functional Units This chapter contains descriptions of the following functional units: • PCI bus arbiter • DMA channels • message unit 2 • Timers • Serial port 6.1 PCI Bus Arbiter The 21285 contains a PCI bus arbiter ...

Page 74

Functional Units Figure 6-1. Secondary Arbiter Example m0 Note: B – 21285 m x – Bus Master Number lpg – Low-Priority Group Arbiter Control Register = 0011b Each bus master, including the 21285, can be configured either ...

Page 75

Figure 6-2 shows DMA descriptors in local memory. Each descriptor occupies four Dwords and must be naturally aligned. The channels read the descriptors from local memory into working registers. Figure 6-2. DMA Descriptor Read Local Memory 4 1 Descriptors 6.2.1 ...

Page 76

Functional Units regardless of the value of the end-of-chain bit, and that this value can the PCI address of the transfer has 0 for its upper 32 bits. — The address of the next descriptor (if any) ...

Page 77

Table 6-1. DMA Channel Write a Initial Destination Address [1: Destination is SDRAM for PCI-to-SDRAM transfers, and PCI for SDRAM-to-PCI transfers. In Table 6-2, on the final write, some of the high-order bytes can be ...

Page 78

Functional Units 6.2.2 SDRAM-to-PCI Transfer For a SDRAM-to-PCI transfer, the channel reads the SDRAM and places the data into the Outbound FIFO when the following conditions are met: • There is enough free space in the FIFO (according to the ...

Page 79

For Dword aligned and unaligned cases, the DMA channels may need to read more data from SDRAM than is transferred to the PCI bus for each burst. case. The PCI address is 100h and the SDRAM address is 208h. To ...

Page 80

Functional Units The FIFOs are used to hold message frame addresses (MFAs). The MFAs are offsets (pointers) to the message frames. The 21285 does not interpret the MFA values other than to recognize the special indicator for an invalid MFA ...

Page 81

I O Inbound FIFO Operation 2 The I O Inbound FIFO operation is as follows: 2 Initialization 1. The I O inbound FIFOs are initialized by the SA-110. During operation, the host sends 2 messages to the local processor ...

Page 82

Functional Units 3. The host processor initializes the outbound free_list FIFO by writing valid MFAs to all entries. SA-110 posts an outbound message 1. When it needs to send a reply message, the SA-110 removes an MFA from the head ...

Page 83

Timers The 21285 contains four timers. Each timer is a 24-bit timer that can be preloaded and either free- run, or decremented to zero and then reloaded. Each timer is clocked in one of four ways: • fclk_in • ...

Page 84

Functional Units System software can use the watchdog as follows. Set timer 4 for periodic interrupts and disable the interrupt on nIRQ/nFIQ. A periodic process (based on one of the other timers) would write to Timer4Load. If that process ever ...

Page 85

Baud Rate Generation The baud rate is derived by dividing down the 21285 clock (fclk_in). The signal fclk_in is divided by four and used as the reference clock. That clock is first divided by a programmable number between 1 ...

Page 86

Functional Units 6.5.7 Serial Port Interrupts Table 6-5 describes how serial port interrupts can be generated. Table 6-5. UART Interrupts Name Source RXINT Rx interrupt TXINT Tx interrupt 6.6 UART Register Definitions This section describes the seven UART registers. 6.6.1 ...

Page 87

RXSTAT—Offset 164h Reading from the RXSTAT provides the error status associated with the data received on UARTDR. Flags in this register indicate error conditions, such as overrun, framing, and parity errors, which occurred during the unpacking of a received ...

Page 88

Functional Units 6.6.3 H_UBRLCR—Offset 168h Writing to this register sets the bit rate and mode for the UART. Dword Bit Name 0 Break 1 Parity enable 2 Odd/even select 3 Stop bit select 4 Enable FIFO 6:5 Data size select ...

Page 89

M_UBRLCR—Offset 16Ch The 12-bit baud rate divisor (BRD) field (top four bits of M_UBRLCR and lower eight bits from L_UBRLCR) is used to select the baud rate of the UART. A total of 4096 different baud rates can be ...

Page 90

Functional Units 6.6.6 UARTCON-Offset 174h This register controls the encoding and protocols. The UE bit is the only control bit that is reset to a known state to ensure that the UART is disabled following a reset. The reset state ...

Page 91

Registers This chapter describes the following categories of registers: • PCI configuration space registers • PCI control and status registers • SA-110 control and status registers — Interrupt controller registers — Timer control registers — DMA control registers — I ...

Page 92

... Expansion ROM Base Address Reserved Cap_Ptr Reserved Interrupt Pin Interrupt Line Reserved PM Capability Identifier PM Control and Status R/W Description R Identifies Intel Corporation as the vendor of this device. Internally hardwired to be 1011h. R/W Description R Identifies this device as the 21285. Internally hardwired to be 1065h. 0 Offset 00h 04h 08h ...

Page 93

Command Register—Offset 04h Dword Bit Name 0 I/O space enable 1 Memory space enable 2 Master enable 3 Special cycle enable 4 Memory write and invalidate enable 5 VGA palette snoop enable 6 Parity error response 21285 Core Logic ...

Page 94

Registers Dword Bit Name 7 Wait cycle control 8 SERR# enable 9 Fast back-to- back enable 15:10 Reserved 7-4 R/W Description R Reads indicate that the 21285 does not perform address or data stepping. R/W Controls the ...

Page 95

Status Register—Offset 06h Dword Bit Name 19:16 Reserved 20 Reserved 21 66-MHz capable 22 UDF supported 23 Fast back-to- back capable 24 Data parity error detected 26:25 DEVSEL#timing 27 Signaled target abort 28 Received target abort 29 Received master ...

Page 96

Registers 7.1.5 Revision ID Register—Offset 08h Dword Bit Name 7:0 Revision ID 7.1.6 Class Code Register—Offset 0Ah Dword Bit Name 31:8 Class code 7.1.7 Cache Line Size Register—Offset 0Ch Dword Bit Name 7:0 Cache line size 7.1.8 Latency Timer Register—Offset ...

Page 97

BIST Register—Offset 0Fh Dword Bit Name 31:24 BIST 7.1.11 CSR Memory Base Address Register—Offset 10h Dword Bit Name 6:0 Memory address space 17:7 CSR base address 27:18 CSR base address 31:28 CSR base address The read/write capability of the ...

Page 98

Registers 7.1.12 CSR I/O Base Address Register—Offset 14h Dword Bit Name 6:0 CSR address space 31:7 CSR base address 7-8 R/W Description R Reads indicate that the CSRs require 128 bytes of I/O address space. R/W Contains ...

Page 99

SDRAM Base Address Register—Offset 18h The read/write capability of the SDRAM base address register is controlled by the SDRAM base address mask register with the following values. For more information about the SDRAM base address mask register, see • ...

Page 100

Registers 7.1.15 Expansion ROM Base Address Register—Offset 30h The read/write capability of the expansion ROM base address register is controlled by the expansion ROM base address mask registers with the following values. • the mask register causes ...

Page 101

Subsystem Vendor ID Register—Offset 2Ch Dword Bit Name 15:0 Subsystem vendor ID 7.1.18 Subsystem ID Register—Offset 2Eh Dword Bit Name 31:16 Subsystem ID 7.1.19 Interrupt Line Register—Offset 3Ch Dword Bit Name 7:0 Interrupt line 7.1.20 Interrupt Pin Register—Offset 3Dh ...

Page 102

Registers 7.1.22 Max_Lat Register—Offset 3Fh Dword Bit Name 31:24 Max_Lat 7.1.23 Capability Identifier Register—Offset 70h Dword Bit Name 7:0 Cap_ID 15:8 Next Item Ptr 7.1.24 Power Management Capabilities (PMC) Register—Offset 72h The PMC register is used to indicate to system ...

Page 103

Dword Bit R/W 8 R/W from SA-110 R from PCI 4 R/W from SA-110 R from PCI 3 R/W from SA-110 R from PCI 2:0 R/W from SA-110 R from PCI 7.1.25 Power Management Control/Status (PMCSR) Register— ...

Page 104

Registers 2. The 21285 asserts Pre_PME due to the SA-110 setting the PME_Status bit (assuming that PME_En is set). 3. System software, in response to PME#, writes Power State from D3 to D0. This causes the 21285 to assert nRESET, ...

Page 105

Table 7-3 lists the PCI control and status registers. Table 7-3. PCI Control and Status Registers 31 7.2.1 Outbound Interrupt Status Register—Offset 30h The outbound interrupt status register indicates the reasons why the 21285 is asserting pci_irq_l. Dword Bit Name ...

Page 106

Registers 7.2.2 Outbound Interrupt Mask Register—Offset 34h The outbound interrupt mask register is used to allow the host processor to disable the 21285 from asserting pci_irq_l. Dword Bit Name 1:0 — 2 Doorbell interrupt mask 3 Outbound post list interrupt ...

Page 107

I O Outbound FIFO Register—Offset 44h 2 The I O Outbound FIFO register is used to access the outbound free_list and outbound post_list 2 from PCI memory space. This register appears as a read-only register if accessed by the ...

Page 108

Registers 7.2.6 Doorbell Register—Offset 60h Each bit in the doorbell register is write-1-to-set from the SA-110, write-1-to-clear from the PCI bus. Dword Bit Name 31:0 Software interrupt 7.2.7 Doorbell Setup—Offset 64h Doorbell setup is an alias of the doorbell register ...

Page 109

SA-110 Control and Status Registers SA-110 control and status registers are accessible only from the SA-110 (offset is from address 4200 0000h). These registers are not byte writable. Table 7-4 lists the control and status registers. Table 7-4. SA-110 ...

Page 110

Registers Table 7-4. SA-110 Control and Status Registers Register PCI address extension Prefetchable memory range X-Bus cycle/Arbiter X-Bus I/O strobe mask Doorbell PCI mask Doorbell SA-110 mask UARTDR RXSTAT H_UBRLCR M_UBRLCR L_UBRLCR UARTCON UARTFLG Reserved IRQStatus IRQRawStatus IRQEnable/IRQEnableSet IRQEnableClear IRQSoft ...

Page 111

Table 7-4. SA-110 Control and Status Registers Register Timer2Clear Reserved Timer3Load Timer3Value Timer3Control Timer3Clear Reserved Timer4Load Timer4Value Timer4Control Timer4Clear Reserved a. This register is accessed by two different addresses. 7.3.1 DMA Channel n Byte Count Register—Offset 80h/A0h The DMA channel ...

Page 112

Registers DMA Channel n PCI Address Register—Offset 84h/A4h 7.3.2 The DMA channel n PCI address register ( contains the low 32 bits of the DMA transfer’s PCI address the address of the source of ...

Page 113

DMA Channel 8Ch/ACh The DMA channel n descriptor pointer register ( contains the SDRAM address of the next DMA descriptor for this channel. If the end-of-chain bit in the DMA channel n byte count register ...

Page 114

Registers 7.3.5 DMA Channel The DMA channel n control register ( contains values that control the DMA channels for the duration of a chain operation. Dword Bit Name 0 Channel enable 1 — 2 Channel transfer ...

Page 115

Dword Bit Name 7 Channel chain done 9:8 Channel interburst delay prescale 14:10 — 15 PCI read length 18:16 SDRAM read length 31:19 — 7.3.6 DMA Channel n DAC Address—Offset 94h/B4h The DMA channel n DAC Address register (n = ...

Page 116

Registers The DMA channel n DAC Address register is cleared by chip reset, and also when the channel-done bit is set at the completion of a DMA chain. Dword Bit Name 31:0 DAC Address Note: This register does not increment ...

Page 117

CSR Base Address Offset Register—Offset FCh Dword Bit Name 17:0 — 27:18 Offset 31:28 — 7.3.9 SDRAM Base Address Mask Register—Offset 100h The SDRAM base address mask register must be written by the SA-110 before the initialize complete bit ...

Page 118

Registers Table 7-7 lists the values that should be programmed into the SDRAM base address mask register to enable the different window sizes from PCI into SDRAM. All other values are illegal. Table 7-7. SDRAM Window Sizes Window Size 256KB ...

Page 119

Figure 7-1. PCI-Generated SDRAM Access 27 18 Mask Register [ n ] Note [27:18] 7.3.11 Expansion ROM Base Address Mask Register—Offset 108h The expansion ROM base address mask register must be written by the SA-110 before ...

Page 120

Registers Table 7-8 lists the values that should be programmed into the expansion ROM base address mask register to enable the different window sizes into ROM. All other values are illegal. Table 7-8. Expansion ROM Window Sizes Window Size 1MB ...

Page 121

SDRAM Timing Register—Offset 10Ch This register controls timing for all SDRAMs. All cycles are referenced to fclk_in. Refer to the SDRAM specification for information about the proper values to use in this register. Dword Bit Name 1:0 Row precharge ...

Page 122

Registers Dword Bit Name 10:8 Row cycle time (T 11 Command drive time 12 Parity enable 13 SA-110 Prime 15:14 — 21:16 Refresh interval (T 31:22 — 7-32 R/W Description ) R/W The minimum number of cycles from an auto-refresh ...

Page 123

SDRAM Address and Size Registers—Offsets 110h to 11Ch The SDRAM address and size registers consist of four registers controlling array 0 through array 3. These four registers define each of the four SDRAM arrays’ start address, size, and address ...

Page 124

Registers 7.3. Inbound Free_List Head Pointer Register—Offset 120h 2 The value written into the inbound free_list head pointer register represents the address in SA-110 SDRAM space of the head (next entry to be read by a PCI read ...

Page 125

I O Outbound Free_List Tail Pointer Register—Offset 12Ch 2 The value written into the outbound free_list tail pointer register represents the address in SA-110 SDRAM space of the tail (next entry to be written by a PCI write to ...

Page 126

Registers 7.3. Inbound Post_List Count Register—Offset 138h 2 The contents of the inbound post_list count register contain the number of entries available on the I O inbound post_list. When a PCI bus master places an entry onto the ...

Page 127

Dword Bit Name 4 SA-110 SDRAM parity error 5 PCI SDRAM parity error W1C 6 DMA SDRAM parity error 7 — 8 Discard timer expired 9 PCI not reset 12: list size 2 21285 Core Logic for SA-110 ...

Page 128

Registers Dword Bit Name 13 Watchdog enable 15:14 ROM width 19:16 ROM access time 23:20 ROM burst time 27:24 ROM tristate time 30:28 XCS direction 31 PCI central function 7-38 R/W Description W1S When 1: Timer 4 resets the SA-110 ...

Page 129

Table 7-9 lists the size of the I Table 7- Inbound and Outbound List Sizes 2 Value 000 001 010 011 100 101 110 111 7.3.22 PCI Address Extension Register—Offset 140h Bit [15] of this register provides bit ...

Page 130

Registers 7.3.23 Prefetchable Memory Range Register—Offset 144h Dword Bit Name 0 Prefetch range enable 1 Prefetch read type 4:2 Prefetch length 7:5 — 18:8 Mask 19 — 30:20 Base address 31 — 7-40 R/W Description R/W When 0: There is ...

Page 131

X-Bus Cycle/Arbiter Register—Offset 148h This register is used either to control the parallel port (X-Bus) or the internal PCI Arbiter. The choice is based on the value latched on ma[7] at reset. When X-Bus is selected (ma[7]=1), the register ...

Page 132

Registers When the internal PCI Arbiter is selected (ma[7]=0), the register contents are as follows. Dword Bit Name 4:0 Arbiter priority 13:5 Undefined 22:14 — 23 PCI Arbiter 27:24 Interrupt input level 30:28 X-Bus chip select 31 PCI interrupt request ...

Page 133

X-Bus I/O Strobe Mask Register—Offset 14Ch Dword Bit Name 7:0 I/O device 0 strobe mask 15:8 I/O device 1 strobe mask 23:16 I/O device 2 strobe mask 31:24 I/O device n strobe mask 21285 Core Logic for SA-110 Datasheet ...

Page 134

Registers 7.3.26 Doorbell PCI Mask Register—Offset 150h The doorbell PCI mask register is used to individually enable each bit of the doorbell register to assert an interrupt to PCI. An internal signal, doorbell PCI interrupt, is asserted if the corresponding ...

Page 135

Figure 7-2. Interrupt Source Configuration Interrupt Source (1 of 27) IRQEnable Register Table 7-10 lists the interrupt controller registers. Table 7-10. Interrupt Controller Registers Address 180h 184h 188h 18Ch 190h 280h 284h 288h 28Ch 290h Table 7-11 lists the 32 ...

Page 136

Registers Table 7-11. Interrupt Source Bits Bits Interrupt Source 4 Timer 1 5 Timer 2 6 Timer 3 7 Timer 4 8 irq_in_l[0] 9 irq_in_l[1] 10 irq_in_l[2] 11 irq_in_l[3] 12 xcs_l[0] 13 xcs_l[1] 14 xcs_l[2] 15 Doorbell from host 16 ...

Page 137

IRQRawStatus/FIQRawStatus Register—Offset 184h/284h The IRQRawStatus and FIQRawStatus read-only registers always contain identical data. Dword Bit Name 31:0 IRQRawStatus/ FIQRawStatus 7.3.31 IRQEnable/FIQEnable Register—Offset 188h/288h This read-only register is used to mask the interrupt input sources and defines which active sources ...

Page 138

Registers 7.3.34 IRQSoft/FIQSoft Register—Offset 190h/290h This write-only register can be used to generate an IRQ/FIQ under software control. Dword Bit Name 0 — 1 RawStatus register bit [1] 31:2 — 7.3.35 SA–110 DAC Address Registers—Offsets 200h to 204h This register ...

Page 139

SA-110 DAC Control Registers—Offset 208h This register provides information used to control prefetching for SA-110 loads from DAC PCI memory space. DACs are performed if the value of all bits in the SA-110 DAC address register is not equal ...

Page 140

Registers 7.3.38 Timer Control Registers The following CSRs control the timers. TimerNValue is read-only and TimerNClear is write-only. Table 7-12. Timer Control Registers Register Timer1Load Timer1Value Timer1Control Timer1Clear Timer2Load Timer2Value Timer2Control Timer2Clear Timer3Load Timer3Value Timer3Control Timer3Clear Timer4Load Timer4Value Timer4Control Timer4Clear ...

Page 141

Timer N Control Register—Offsets 308h, 328h, 348h, and 7.3.41 368h This register controls the timer functions. Timer4 can be used as a watchdog timer. When the watchdog enable bit [13] in the SA-110 control register is set ...

Page 142

...

Page 143

JTAG Test Port The 21285 contains a serial scan test port that conforms to IEEE standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. 8.1 Test Access Port Controller The test access port controller is a finite state machine ...

Page 144

JTAG Test Port 8.2 Boundary-Scan Implementation Exceptions The critical timing of the clocking signals osc, fclk, sdclk[3:0], and MCLK force the exception of the IEEE 1149.1 standards for these device pins. The following modifications have been implemented: Note: BC_1, BC_2, ...

Page 145

Boundary-Scan Register The boundary-scan register is a single-shift register-based path formed by boundary-scan cells placed at the chip’s signal pins. The register is accessed through the JTAG ports tdi and tdo pins. A machine-readable boundary-scan index (BSDL.TXT) for each ...

Page 146

...

Page 147

Electrical Specifications This section specifies the following electrical behavior of the 21285: • PCI electrical conformance • Absolute maximum ratings • dc specifications • ac timing specifications 9.1 PCI Electrical Specification Conformance The 21285 PCI pins conform to the basic ...

Page 148

Electrical Specifications 9.3 DC Specifications Table 9-3 defines the dc parameters met by all 21285 PCI signals under normal operating conditions. Note: In Table 9-3, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from the ...

Page 149

AC Timing Specifications The next sections describe the following specifications: • PCI clock timing • PCI signal timing • PCI reset timing • JTAG timing 9.4.1 PCI Clock Timing Specifications The ac specifications consist of input requirements and output ...

Page 150

Electrical Specifications 9.4.2 PCI Signal Timing Specifications Figure 9-2 and Table 9-5 parameters with the 21285 signal pins. Figure 9-2. PCI Signal Timing Measurement Conditions PCI_CLK Output Input Note: _ 1.5 V for 5-V signals; 0 test . ...

Page 151

Table 9-6 lists the ac parameters that are applied in Table 9-6. PCI Signal Timing AC Parameters Name ad[31:0] cbe_l[3:0] par frame_l irdy_l trdy_l stop devsel_l idsel perr_l serr_l req_l gnt_l pci_irq_l 9.4.3 PCI Reset Timing Specifications Table 9-7 shows ...

Page 152

Electrical Specifications 9.4.4 JTAG Timing Specifications Table 9-8 shows the JTAG timing specifications. Table 9-8. JTAG Timing Specifications Symbol Parameter T tck frequency jf T tck high time jht T tck low time jlt T tck rise time jrt T ...

Page 153

SA-110, 21285, and SDRAM Clock Signal Timing Specifications Figure 9-3 and Table 9-9 Figure 9-3. Clock Signal AC Parameter Measurement Conditions T oscrt osc T ckoor fclk T ckosr sdclk T sdclkrt T mclkft MCLK T ckomf Table 9-9. ...

Page 154

Electrical Specifications Table 9-9. SA-110, 21285, and SDRAM Clock Signal AC Parameters Name Parameter T sdclk rise time sdclkrt T sdclk fall time sdclkft T Skew between rising edges on any two of sdclk[3:0] skew1 T Skew between MCLK falling ...

Page 155

Figure 9-5. Input Timing Measurement Conditions fclk_in Falling Input Rising Input Timing Symbol( Table 9-10. Memory and SA-110 AC Parameters Name Parameter T T dis dis T T dih dih T T pis pis ...

Page 156

Electrical Specifications Table 9-10. Memory and SA-110 AC Parameters Name Parameter T dqm[3:0] output delay during 21285 write dqms T ma, ba output delay maout T cmd[2:0] output delay cmdout T cs_l[3:0] output delay csout T xd_wren_l assertion delay xwhl ...

Page 157

Mechanical Specifications The 21285 is contained in an industry-standard 256 plastic ball grid array (PBGA) package, as shown in Figure 10-1. Figure 10-1. 256 Plastic Ball Grid Array (PBGA) Package Pin 1 Corner Pin 1 I. Chamfer 4 ...

Page 158

Mechanical Specifications Table 10-1 lists the package dimensions in millimeters . Table 10-1. 256 Plastic Ball Grid Array (PBGA) Package Dimensions Symbol Dimension e Ball pitch A Overall package height A Package standoff height 1 A Encapsulation thickness 2 b ...

Page 159

Support, Products, and Documentation If you need technical support, a Product Catalog, or help deciding which documentation best meets your needs, visit the Intel World Wide Web Internet site: http://www.intel.com Copies of documents that have an ordering number and are ...

Related keywords