HDMP-1638 Agilent Technologies, Inc., HDMP-1638 Datasheet

no-image

HDMP-1638

Manufacturer Part Number
HDMP-1638
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HDMP-1638
Manufacturer:
AVAGO
Quantity:
4
Part Number:
HDMP-1638
Manufacturer:
AGILENT
Quantity:
20 000
Part Number:
HDMP-1638G
Manufacturer:
PMC
Quantity:
8 708
Technical Data
Gigabit Ethernet Transceiver Chip
with Dual Serial I/O and
Differential PECL Clock Inputs
Features
• IEEE 802.3z Gigabit Ethernet
• Based on X3T11 “10-Bit
• Low Power Consumption
• Transmitter and Receiver
• 10 mm, 64-Pin Plastic
• 5 Volt Tolerant I/Os
• 10-Bit Wide Parallel TTL
• Single +3.3 V Power Supply
• Differential PECL Clock
• Dual Serial I/O With
• 2kV ESD Protection on
Applications
• 1250 MBd Gigabit Ethernet
• High Speed Proprietary
• Backplane Serialization/Bus
CAUTION: As with all semiconductor IC’s, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).
compatible, Supports
1250 MBd Gigabit Ethernet
Specification”
Functions Incorporated
Onto a Single IC
Package
Compatible I/Os
Inputs
Receive Select
All Pins
Interface
Interface
Extender
Description
The HDMP-1638 transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet
or proprietary link interfaces.
It provides complete Serialize/
Deserialize (“SerDes”) for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing
board space, power and cost.
It is compatible with the IEEE
802.3z specification.
The transmitter section accepts
10-bit wide parallel TTL data
and serializes this data into two
high speed serial data streams.
The parallel data is expected to
be “8B/10B” encoded data, or
equivalent. This parallel data is
latched into the input register
of the transmitter section on
the rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL locks
to this user supplied 125 MHz
byte clock. This clock is then
HDMP-1638 Transceiver
the incoming serial signal and
recovers the high speed serial
clock and data. The serial data
is converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed
outputs. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section allows
for the selection of one of two
serial electrical data streams
at 1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto

Related parts for HDMP-1638

HDMP-1638 Summary of contents

Page 1

... CAUTION: As with all semiconductor IC’ advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). Description The HDMP-1638 transceiver is a single silicon bipolar integrated circuit packaged in a plastic QFP package. It provides a low-cost, ...

Page 2

... Parallel to Serial Converter • Serial Clock and Data Recovery • Comma Character Recognition • Byte Alignment Circuitry • Serial to Parallel Converter PROTOCOL DEVICE BYTSYNC REFCLK ENBYTSYNC Figure 1. Typical Application Using the HDMP-1638. DATA BYTE FRAME TX[0-9] MUX TX INTERNAL TXCAP0 PLL/CLOCK TX CLOCKS ...

Page 3

Input Latch The transmitter accepts 10-bit wide TTL parallel data at inputs TX[0..9]. REFCLK (from this point forward, REFCLK is defined as the difference between the user- provided PECL reference clocks, REFCLK) is used as the transmit byte clock. The ...

Page 4

... These clocks will be fully aligned by the start of the second 2-byte ordered set. The second comma character received shall be aligned with the rising edge of RBC1. As per the 8B/10B encoding HDMP-1638 (Transmitter Section) Timing Characteristics + 3. 3. ...

Page 5

REFCLK TX[0]-TX[9] DATA DATA t SETUP Figure 3: Transmitter Section Timing. ± DOUTA TX[0]-TX[9] REFCLK Figure 4: Transmitter Latency. DATA DATA t HOLD DATA BYTE ...

Page 6

... HDMP-1638 (Receiver Section) Timing Characteristics + 3. 3. Symbol f_lock Frequency Lock at Powerup [1,2] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data Valid After Rising Edge of RBC valid_after t RBC Duty Cycle duty A-B [4] t Rising Edge Time Difference Between RBC0 and RBC1 ...

Page 7

... HDMP-1638 (TRx) Guaranteed Operating Rates + 3. 3. Parallel Clock Rate (MHz) Min. Max. 124.0 126.0 HDMP-1638 (TRx) Transceiver Reference Clock Requirements + 3. 3. Symbol f Nominal Frequency (for Gigabit Ethernet Compliance) F Frequency Tolerance tol ...

Page 8

... Transceiver V Supply Current Notes: 1. Masurement Conditions: Tested sending 1250 MBd PRBS 2^7-1 sequence from a serial BERT with both D 150 resistors. 2. Typical specified with V = 3.3 volts, maximum specified with V CC HDMP-1638 (TRx) PECL DC Electrical Specifications + 3. 3. Symbol Parameter V ...

Page 9

... Note: 1.Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-. A. DIFFERENTIAL HS_OUT OUTPUT (DOUT+ MINUS DOUT–) B. SINGLE-ENDED HS_OUT OUTPUT (DOUT+) Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1638 as Captured on the 83480A Digital Communications Analyzer. Tested with PRBS=2 Figure 7: Transmitter DOUT Eye Diagrams. Parameter 22 ...

Page 10

... HDMP-1638 (Transmitter Section) Output Jitter Characteristics (Measured with equivalent parts which have TTL REFCLK input + 3. 3. Symbol [1] RJ Random Jitter at DOUT, the High Speed Electrical Data Port, Specified as 1 Sigma Deviation of the 50% Crossing Point (RMS) [1] DJ ...

Page 11

... CC resistors and receiver TTL outputs driving 10 pF loads. for these devices is 48 C/W for the HDMP-1638 Pd), where T is the case temperature measured on the top center of the package ...

Page 12

O_TTL V _TTL ESD PROTECTION GND_TTL Figure 9: O-TTL and I-TTL Simplified Circuit Schematic. HS OUT ESD PROTECTION NOTES: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. ...

Page 13

... S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE *NOTE: PINS 12 AND 27 ARE DESIGNATED AS "NO CONNECT" PINS AND ARE NORMALLY UNCONNECTED. Figure 11: HDMP-1638 (TRx) Package Layout and Marking, Top View HDMP-1638 xxxx-x Rz.zz S ...

Page 14

TRx I/O Definition NAME PIN BYTSYNC 47 -DINA 52 +DINA 53 -DINB 55 +DINB 56 RXSEL 13 -DOUTA 59 +DOUTA 60 -DOUTB 62 +DOUTB 63 ENBYTSYNC 24 GND 21 25 GND_RXA 51 GND_RXHS 57 GND_RXTTL GND_TXA 15 ...

Page 15

NAME PIN GND_TXHS 1 GND_TXTTL 14 N/C 27,12 LOOPEN 19 RBC1 30 RBC0 31 +REFCLK 22 -REFCLK 23 RX[0] 45 RX[1] 44 RX[2] 43 RX[3] 41 RX[4] 40 RX[5] 39 RX[6] 38 RX[7] 36 RX[8] 35 RX[9] 34 RXCAP0 48 ...

Page 16

NAME PIN TX[0] 2 TX[1] 3 TX[2] 4 TX[3] 5 TX[4] 6 TX[5] 7 TX[6] 8 TX[7] 9 TX[8] 10 TX[9] 11 TXCAP0 17 TXCAP1 16 SIG_DET 26 V _RX _RXA _RXHS 54 ...

Page 17

... CC 100 ppm. 17 Transceiver Power Supply Bypass and Loop Filter Capacitors If desired, bypass capacitors may be used on the power supply pins of the HDMP-1638. All bypass chip capacitors are 0.1 F. The V _RXA and V _TXA pins are CC CC the analog power supply pins for the PLL sections. The supply into these pins should be clean with minimum noise ...

Page 18

... ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER A1 A2 HDMP-1638 10.00 13.20 TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ Figure 13: Mechanical Dimensions of HDMP-1638. Details Plastic 85% Tin, 15% Lead 300–800 m 0.08 mm max ...

Page 19

... Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5120E (11/99) ...

Related keywords