HPFC-5100C Agilent Technologies, Inc., HPFC-5100C Datasheet

HPFC-5100C

Manufacturer Part Number

HPFC-5100C

Description

Manufacturer

Agilent Technologies, Inc.

Datasheet

1.HPFC-5100C.pdf (4 pages)

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Meier Automation Equipment Co., Limited

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HPFC-5100C/2.3

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Tachyon TL

33 MHz PCI to Fibre Channel

Controller

Technical Data

Features

• Second Generation Controller

• Supports All Fibre Channel

• Supports Both Class 3 and

• 33 MHz, 32/64-Bit PCI

• 1 Gigabit/Second Fibre

• Full Duplex Support with

• 32/64-Bit PCI Interface,

• Complete Hardware Handling

• Full Initiator and Target

Applications

• Motherboard Integration

• Host-Based Adapters

• Storage Sub-systems

• I

Description

The HPFC-5100C, Tachyon TL, is

a second-generation controller that

leverages extensive experience in

Fibre Channel, established with the

original TACHYON controller.

Tachyon TL carries forward the

IC, Based on TACHYON

Family Architecture

Topologies; Arbitrated Loop

(FC-AL) and N_Port Fabric

Attachment

Class 2 (via Software)

Interface

Channel Rate

Parallel Inbound and

Outbound Processing

Compliant to PCI v2.1

of Entire SCSI I/O via FCP

On-Chip Assists

Mode Functionality

O Designs

assurance of interoperability and

true Fibre Channel performance.

Tachyon TL focuses on mass

storage applications for any

topology that require Class 3 and

2 (via software) and SCSI upper

layer protocol handling. Coupled

with a high performance 33 MHz,

32/64-bit PCI bus interface,

Tachyon TL provides a cost-

effective, high-performance mass

storage solution.

TACHYON Architecture

Tachyon TL continues with the

TACHYON architecture, a

complete hardware-based state

machine design. This architec-

ture does not require an addi-

tional on-board microprocessor

and therefore avoids reduced

performance issues relating to

processor cycles per second and

access time to firmware. Rather,

the TACHYON architecture is

designed to be a single chip Fibre

Channel solution.

Tachyon TL provides the highest

levels of concurrency via

numerous independent functional

blocks providing parallel

processing of data, control, and

commands. In addition, these

blocks process at hardware

speeds versus firmware speeds,

and automate the entire SCSI I/O

in hardware. The result is

minimized latency and I/O over-

HPFC-5100C

head, coupled with the highest

levels of parallelism to provide

maximum I/O rates and

bandwidth.

FC-AL Features

In addition to the high-perfor-

mance architecture, Tachyon TL

offers FC-AL-1 Fibre Channel

features, such as Auto Status,

multiple I/Os in the same loop

arbitration cycle, loop map, loop

broadcast, and loop directed

reset. These features allow the

designer to achieve higher

performance in an arbitrated loop

topology.

Physical Layer

The physical layer interface is the

popular 10-bit wide specification

that allows interfacing to a low-

cost serializer/deserializer

(SerDes) IC. This is the same

physical layer interface that is

popular on Fibre Channel disk

drives today due to its quality

gigabit signaling, small form

factor, and low cost.

Related parts for HPFC-5100C

HPFC-5100C Summary of contents

Page 1

... Motherboard Integration • Host-Based Adapters • Storage Sub-systems • Designs 2 Description The HPFC-5100C, Tachyon TL second-generation controller that leverages extensive experience in Fibre Channel, established with the original TACHYON controller. Tachyon TL carries forward the assurance of interoperability and true Fibre Channel performance. ...

Page 2

... INBOUND SCSI EXCHANGE DATA MANAGER, MANAGER INBOUND INBOUND FIFO MANAGER OS PROCESSOR/ CRC CHECKER ELASTIC STORE 10B / 8B DECODER HPFC-5100C Block Diagram. HOST DATA STRUCTURES EXCHANGE REQUEST QUEUE SCSI EXCHANGE STATE TABLE PCI LOCAL BUS DMA ARBITER MULTIPLEXER SINGLE EXCHANGE FRAME REQUEST MANAGER ...

Page 3

Tachyon TL Specifications Fibre Channel Operation Fibre Channel Rate Frame Payload Size Topology Classes of Operation Upper Layer Protocol Loop Initialization Arbitrated Loop Capabilities Buffer-to-Buffer Credit Physical Layer Interface Link Diagnostics Compliance Fibre Channel Protocol (FCP) for SCSI Features SCSI ...

Page 4

... Flash and ROM support for Boot BIOS and Subsystem Vendor ID No Yes Yes, IEEE Standard 1149.1 Boundary Scan Yes Yes Link up/down, low-speed serial interface or custom 272-pin Enhanced Plastic Ball Grid Array (PBGA+) www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5968-5303E (11/99) ...

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