HD64645F HITACHI, HD64645F Datasheet
HD64645F
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HD64645F Summary of contents
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HD64645/HD64646 LCTC (LCD Timing Controller) Description The HD64645/HD64646 LCTC is a control LSI for large size dot matrix liquid crystal displays. The LCTC is software compatible with the HD6845 CRTC, since its programming method of internal registers and memory addresses ...
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... LCTC and LCD driver Recommended LCD driver HD66110ST and HD66120 (segment) HD66113T and HD66115T (common) CPU interface 80 family CMOS process Single +5 V 10% Ordering Information Type No. HD64645F HD64646FS 2 Package 80-pin plastic QFP (FP-80) 80-pin plastic QFP (FP-80B) ...
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Pin Arrangement MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 10 MD10 11 MD11 12 MD12 13 MD13 14 MD14 15 MD15 LD3 18 LD2 19 LD1 20 LD0 21 LU3 22 LU2 ...
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HD64645/64646 Pin Description Symbol Pin Number 17 GND1, GND2 37, 59 LU0–LU3 22–25 LD0–LD3 18–21 CL1 28 CL2 29 FLM MA0–MA15 65–80 RA0–RA4 60–64 MD0–MD7 1–8 MD8–MD15 9–16 DB0–DB7 43–50 ...
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Pin Functions Power Supply ( GND Power Supply Pin (+5 V): Connect V Ground Pin (0 V): Connect GND1 and GND2 with 0V. LCD Interface LCD Up Panel Data (LU0–LU3), LCD Down Panel Data (LD0–LD3): ...
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HD64645/64646 Timing Signal D Clock (DCLK): DCLK inputs the system clock. M Clock (MCLK): MCLK indicates memory cycle; DCLK is divided by four. Display Timing (DISPTMG): DISPTMG high indicates that the LCTC is reading display data. Cursor Display (CUDISP): CUDISP ...
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Table 2 Skew Signals SK0 SK1 Skew Function skew 1 0 1-character time skew 0 1 2-character time skew 1 1 Prohibited combination Function Overview Main Features of HD64645/HD64646 Main features of the LCTC are: High-resolution liquid ...
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HD64645/64646 Table 3 Functions, Application, and Configuration Classification Item Functions Screen format Cursor control Memory rewriting Memory addressing Paging and scrolling Character attributes Application CRTC compatible OR function Configuration LCTC configuration 8 Description Programmable horizontal scanning cycle by the character ...
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Differences between HD64645 and HD64646 Figure 1 and Figure 2 show the relation between display data transfer period, when display data shift clock CL2 changes, and display data latch clock CL1. Figure 1 shows the case without skew function and ...
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HD64645/64646 MCLK 1 DISPTMG CL1 MCLK (HD64645) CL1 (HD64646) CL2 ( CL2 MCLK CL2 ( CL2 MCLK 1 MCLK DISPTMG CL1 (HD64645) MCLK CL1 (HD64646) CL2 ( CL2 MCLK CL2 (f ...
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Internal Block Diagram Figure block diagram of the LCTC. DCLK Dot counter CPMA CLK CL2 Q R CL1 CLK CLK CLK CLK FLM Counter 1/2 CLK M CLK MA0–MA15 RA0–RA4 LU0–LU3 8-bit/4-bit counter LD0–LD3 MCLK DISPTMG Skew ...
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HD64645/64646 System Block Configuration Examples Figure block diagram of a character/graphic display system. Figure 6 shows two examples using LCD drivers. MPU bus Memory control Figure 4 Character/Graphic Display System Example 12 Dec. Multiplexer 2 R/W, AD ...
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Interface to MPU A –A 0 IOE RD HD64180 MPU WR D0–D7 RES Note family MPUs, I/O space is separate from memory space in software. Thus the LCTC, a part of I/O, needs the ORed signals of the ...
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HD64645/64646 Dual screen LU0– 4 LU3 FLM CL1 CL2 M LCTC LD0– 4 LD3 Single screen LU0– 4 LU3 FLM CL1 CL2 M LCTC 14 HD66110ST E (1) 160 HD66113T 120 (1) HD66113T 120 (4) 160 HD66110ST E (5) HD66110ST ...
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Registers Table 4 shows the register mapping. Table 5 describes their function. Table 6 shows the differences between CRTC and LCTC registers. Table 4 Registers Mapping Address Register Reg No. Register Name 1 ...
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HD64645/64646 Table 5 Internal Register Description Reg. No. Register Name AR Address register R0 Horizontal total characters R1 Horizontal displayed characters R9 Maximum raster address R10 Cursor start raster R11 Cursor end raster R12 Start address (H) R13 Start address ...
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Table 6 Internal Register Comparison between LCTC and CRTC Reg. No. LCTC HD64645/HD64646 AR Address register R0 Horizontal total characters R1 Horizontal displayed characters R2 — Maximum raster address R10 Cursor start raster ...
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HD64645/64646 Functional Description Programmable Screen Format Figure 7 illustrates the relation between LCD display screen and registers. Figure 8 shows a timing chart of signals output from the LCTC in mode example. (R21) Start Horizontal displayed characters ...
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MCLK DISPTMG CUDISP (Latch timing) MA0–MA15 RA0–RA4 FLM M CL1 CL2 LU0 LU1 ...
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HD64645/64646 Cursor Control The following cursor functions (Figure 9) can be controlled by programming specific registers. Cursor display position Cursor height Cursor blink mode A cursor can be displayed only in character mode. Also, CUDISP pin must be connected to ...
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Character Mode and Graphic Mode The LCTC supports two types of display modes; character mode and graphic mode. Graphic mode 2 is provided to utilize software for a system using the CRTC (HD6845). The display mode is controlled by an ...
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HD64645/64646 Horizontal Virtual Screen Width Horizontal virtual screen width can be specified by the character in addition to the number of horizontal displayed characters (Figure 12). The display screen can be scrolled in any direction by the character, by setting ...
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R18 R1 Start address Performing horizontal scroll by updating the start address ...
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HD64645/64646 Smooth Scroll Vertical smooth scrolling (Figure 14) is performed by updating the display start raster, as specified by the start raster register (R21). This function is offered only in character mode. Wide Display The character to be displayed can ...
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Attribute Functions A variety of character attribute functions such as reverse video, blinking, nondisplay (white) or nondisplay (black) can be implemented by storing the attribute data in A-RAM (attribute RAM). Figure 16 shows a display example using each attribute function. ...
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HD64645/64646 MD Input 15 Function Non- display (black) Note: *** Invalid OR Function — Superimposing Characters and Graphics The OR function (Figure 18) generates the OR of the data entered into MD0–MD7 (e.g. character data) and the data into MD8–MD15 ...
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DRAM Refresh Address Output Function The LCTC outputs the address for DRAM refresh while CL1 is high, as shown in Figure 19. The 16 refresh addresses per scanned line are output 16 times, from $00–$FF. Skew Function The LCTC can ...
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HD64645/64646 Easy Mode This mode utilizes software for systems using the CRTC (HD6845). By setting MODE pin to high, the display mode and screen format are fixed as shown in Table 8. With this mode, software for a CRT screen ...
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System configuration and Mode Setting LCD System Configuration The screen configuration, single or dual, must be specified when using the LCD system (Figure 21). Using the single screen configuration, you can construct an LCD system with lower cost than a ...
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HD64645/64646 Data Column driver Single Screen Figure 21 Hardware Configuration According to Screen Format Table 9 Mode Selection Hardware Configuration Screen LCD Data Configu- Screen Transfer ration Size 4-bit Single Normal Dual Normal Large 8-bit Single Normal ...
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Mode List Table 10 Mode List No. Mode Name D/S 1 Dual-screen character Dual-screen wide 1 character 1 3 Dual-screen graphic Dual-screen graphic Single-screen character Single-screen wide 0 ...
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HD64645/64646 Internal Registers The HD64645/HD64646 has one address register and fourteen data registers. In order to select one out of fourteen data registers, the address of the data register to be selected must be written into the address register. The ...
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Maximum Raster Address Register (R9) R9 register (Figure 25) specifies the number of rasters per row in characters mode, consisting of 5 bits. The programmable range raster/row (32 rasters/row). Figure 23 Horizontal Total Characters Register ...
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HD64645/64646 Cursor End Raster Register (R11) R11 register (Figure 27) specifies the cursor end raster address. Start Address Register (H/L) (R12/R13) R12/R13 register (Figure 28) specifies a buffer memory read start address. Updating this register facilitates paging and scrolling. R14/R15 ...
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Multiplexing Duty Ratio Register (H/L) (R19/R20) R19/R20 register (Figure 31) specifies the number of vertical dots of the display screen. The programmed value differs according to the LCD screen configuration. In single screen configuration: (Programmed value) = (Number of vertical ...
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HD64645/64646 Mode Register (R22) The Or of the data bits of R22 (Figure 33) register and the external terminals of the same name determines a particular mode (Figure 34). Figure 30 Horizontal Virtual Screen Width Register 36 Data Bit Program ...
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AT (data bit 0) BLE (data bit 1) WIDE (data bit 2) G/C (data bit 3) ON/OFF (data bit 4) Mode register (R22) Notes (valid only when G/C is low (character mode High: Attribute functions enabled, ...
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HD64645/64646 Restrictions on Programming Internal Registers Note when programming that the values you can write into the internal registers are restricted as shown in Table 12. Table 12 Restrictions on Writing Values into the Internal Registers Function Restrictions 1 < ...
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Reset RES pin determines the internal state of LSI counters and the like. This pin does not affect register contents nor does it basically control output terminals. Reset is defined as follows (Figure 35): At reset: the time when RES ...
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HD64645/64646 RES 0.8V At reset min During reset Figure 35 Reset Definition V – 0.5V CC After reset ...
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Absolute Maximum Ratings Item Supply voltage Terminal voltage Operating temperature Storage temperature Notes: 1. Permanent LSI damage may occur if maximum ratings are exceeded. Normal operation should be under recommended operating conditions (V +75 C). If these conditions are exceeded, ...
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HD64645/64646 Electrical Characteristics DC Characteristics (V = 5.0V 10%, GND = 0V Item RES, MODE, Input high voltage SK0, SK1 DCLK, ON/OFF All others Input low All others voltage Output high TTL interface* voltage CMOS interface* Output low ...
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AC Characteristics CPU Interface (V = 5.0V 10%, GND = 0V Item RD high level width RD low level width WR high level width WR low level width CS, RS setup time CS, RS hold time DB0–DB7 setup ...
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HD64645/64646 Memory Interface (V = 5.0V 10%, GND = 0V Item DCLK cycle time DCLK high level width DCLK low level width DCLK rise time DCLK fall time MCLK delay time MCLK rise time MCLK fall time MA0–MA15 ...
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CYCD 2.2V Dr DCLK 0.8V t WDL t DMD 2.4V MCLK t Mf 0.4V MA0–MA15 t RAD RA0–RA4 t DTD DISPTMG t CDD CUDISP t CL1D CL1 MD0–MD15 (input) t WDH t DMD ...
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HD64645/64646 LCD Interface 1 (HD64645) (V Item Display data setup time Display data hold time CL2 high level width CL2 low level width FLM setup time FLM hold time CL1 rise time CL1 fall time CL2 rise time CL2 fall ...
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LCD Interface 2 (HD64646 at f Item FLM setup time FLM hold time M delay time CL1 high level width Clock setup time Clock hold time Phase difference 1 Phase difference 2 CL2 high level width CL2 low level width ...
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HD64645/64646 FLM CL1 M CL1 CL2 t LDS t LDD LU0–LU4 LD0–LD4 – 0. PD1 CL1H V – 0.8V CC 0.8V t SCL t PD2 t LDH Figure 39 LCD Interface V ...
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Load Circuit TTL Load Terminal DB0–DB7 MA0–MA15, RA0–RA4, DISPTMG, CUDISP MCLK Capacitive Load Terminal CL2 CL1 LU0–LU3, LD0–LD3, M FLM Refer to user’s manual (No. 68-1-160) and application note (No. ADE-502-003) for detail of this product 2.4 k ...
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... HD64645/64646 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document ...