AMD-X5-133SFZ Advanced Micro Devices, AMD-X5-133SFZ Datasheet
AMD-X5-133SFZ
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AMD-X5-133SFZ Summary of contents
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... X This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Complete 32-Bit Architecture — Address and data buses — ...
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... AMD BLOCK DIAGRAM 2 PRELIMINARY Am5 86 Microprocessor X ...
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... AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. – 133 A D AMD-X5 Valid Combinations OPN Package Type AMD-X5-133ADW PGA AMD-X5-133ADZ PGA AMD-X5-133SFZ SQFP AMD-X5-133SDZ SQFP PRELIMINARY W Case Temperature W= 55° 85° C Operating Voltage 3.3 V Package Type ...
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... AMD Table of Contents 1 Connection Diagrams and Pin Designations ......................................................................................... 8 1.1 168-Pin PGA (Pin Grid Array) Package .......................................................................................... 8 1.2 168-Pin PGA Designations (Functional Grouping) ......................................................................... 9 1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................ 10 1.4 208-Pin SQFP Designations (Functional Grouping) ..................................................................... 11 2 Logic Symbol ...................................................................................................................................... 12 3 Pin Description .................................................................................................................................... 13 4 Functional Description ........................................................................................................................ 18 4.1 Overview ....................................................................................................................................... 18 4 ...
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... SMRAM Interface ................................................................................................................ 48 7.8.2 Cache Flushes .................................................................................................................... 49 7.8.3 A20M Pin ............................................................................................................................. 49 7.8.4 CPU Reset during SMM ...................................................................................................... 52 7.8.5 SMM and Second Level Write Buffers ................................................................................ 52 7.8.6 Nested SMI and I/O Restart ................................................................................................ 52 7.9 SMM Software Considerations ..................................................................................................... 52 7.9.1 SMM Code Considerations ................................................................................................. 52 7.9.2 Exception Handling ............................................................................................................. 52 7.9.3 Halt during SMM .................................................................................................................. 53 7.9.4 Relocating SMRAM to an Address above 1 Mbyte ............................................................. 53 PRELIMINARY Am5 86 Microprocessor X AMD 5 ...
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... AMD 8 Test Registers 4 and 5 Modifications .................................................................................................. 53 8.1 TR4 Definition ................................................................................................................................ 53 8.2 TR5 Definition ................................................................................................................................ 54 8.3 Using TR4 and TR5 for Cache Testing.......................................................................................... 55 8.3.1 Example 1: Reading the Cache (Write-back mode only) ..................................................... 55 8.3.2 Example 2: Writing the Cache .............................................................................................. 55 8.3.3 Example 3: Flushing the Cache ........................................................................................... 55 9 Am5 86 CPU Functional Differences ................................................................................................. 55 X 9.1 Status after Reset ......................................................................................................................... 55 9.2 Cache Status ................................................................................................................................ 55 9 ...
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... Test Register TR5 Bit Descriptions ......................................................................................... 53 Table 19 CPU ID Codes ......................................................................................................................... 56 Table 20 CPUID Instruction Description ................................................................................................. 56 Table 21 Thermal Resistance (°C/W) Table 22 Maximum T at Various Airflows in °C .................................................................................... 65 A Table 23 Maximum T for SQFP Package by Clock Frequency ............................................................. 65 A PRELIMINARY and for the Am5 86 CPU in 168-Pin PGA Package ....... Am5 86 Microprocessor X AMD 7 ...
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... AMD 1 CONNECTION DIAGRAMS AND PIN DESIGNATIONS 1.1 168-pin PGA (Pin Grid Array) Package D20 D19 D11 D22 D21 D18 D13 TCK V CLK D17 D10 SS 3 D23 DP3 V V D13 VCC D24 D25 D27 D13 ...
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... CLKMUL R-17 D/C M-15 DP0 N-3 DP1 F-1 DP2 H-3 DP3 A-5 EADS B-17 FERR C-14 FLUSH C-15 HITM A-12 HLDA P-15 HOLD E-15 IGNNE A-15 INTR A-16 INV A-10 KEN F-15 LOCK N-15 M/IO N-16 NMI B-15 PCD J-17 PCHK Q-17 PLOCK Q-16 PWT L-15 RDY F-16 RESET C-16 SMI B-10 SMIACT C-12 SRESET C-10 STPCLK G-15 UP C-11 VOLDET S-4 WB/WT B-13 W/R N-17 . Am5 86 Microprocessor X AMD V V Test INC cc ss Pin Pin Pin Pin No. No. No. No. A-3 A-13 B-7 A-7 A-14 C-13 B-9 A-9 B-16 J-1 B-11 A-11 B-14 C-4 B-3 C-5 B-4 E-2 B-5 E-16 E-1 G-2 E-17 G-16 G-1 H-16 G-17 K-2 H-1 K-16 H-17 L-16 K-1 M-2 K-17 M-16 L-1 P-16 L-17 R-3 M-1 R-6 M-17 R-8 P-17 R-9 Q-2 R-10 R-4 R-11 S-6 R-14 S-8 S-9 S-10 ...
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... AMD 1.3 208-pin SQFP (Shrink Quad Flat Pack) Package 10 PRELIMINARY TOP VIEW Am5 86 Microprocessor X ...
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... LOCK 207 M/IO 37 NMI 51 PCD 41 PCHK 4 PLOCK 206 PWT 40 RDY 12 RESET 48 SMI 65 SRESET 58 STPCLK 73 SMIACT 59 UP 194 WB/WT 64 W/R 27 Am5 86 Microprocessor X AMD Test INC Pin Pin Pin Pin No. No. No. No 168 167 127 ...
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... AMD 2 LOGIC SYMBOL CLK Clock STPCLK Stop Clock CLKMUL Clock Multiplier A20M Address Mask Upgrade UP Present VOLDET Voltage Detect A31–A4 28 A3–A2 2 Address Bus BE3–BE0 4 BS8 BS16 Bus Cycle ADS Control RDY M/IO D/C Bus Cycle W/R Definition LOCK PLOCK INTR NMI ...
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... Internal Cycle Pending (Active High; Output) BREQ indicates that the microprocessor has generated a bus request internally, whether or not the micropro- cessor is driving the bus. BREQ is active High and is floated only during Tri-state Test mode (see FLUSH). Am5 86 Microprocessor X AMD and t for 18 19 and ...
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... AMD BS8/BS16 Bus Size 8 (Active Low; Input)/ Bus Size 16 (Active Low; Input) The BS8 and BS16 signals allow the processor to op- erate with 8-bit and 16-bit I/O devices by running multiple bus cycles to respond to data requests: four for 8-bit devices, and two for 16-bit devices. The bus sizing pins are sampled every clock ...
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... RDY during the last read in the cache line fill causes the line to be placed in the on-chip cache. KEN is active Low and is provided with a small internal pull-up resistor. KEN must satisfy setup and hold times t proper operation. Am5 86 Microprocessor X AMD and t for proper operation microprocessor X 86 microprocessor will freeze on ...
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... AMD LOCK Bus Lock (Active Low; Output) A Low output on this pin indicates that the current bus cycle is locked. The microprocessor ignores HOLD when LOCK is asserted (although it does acknowledge AHOLD and BOFF). LOCK goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle ...
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... A High output indicates a write cycle. A Low output in- dicates a read cycle. Note: The Am5 86 microprocessor does not use the X V pin used by some 3-V, clock-tripled, 486-based CC5 processors. The corresponding pin on the Am5 croprocessor is an Internal No Connect (INC). Am5 86 Microprocessor X AMD . ...
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... AMD 4 FUNCTIONAL DESCRIPTION 4.1 Overview Am5 86 microprocessors use a 32-bit architecture with X on-chip memory management and cache memory units. The instruction set includes the complete 486 micropro- cessor instruction set along with extensions to serve the new extended applications. All software written for the ...
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... Table 5 shows the MESI cache line states and the correspond- ing availability of data. Am5 86 Microprocessor X AMD S0 Line State 0 Invalid 1 Exclusive 0 ...
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... AMD Table 5. MESI Cache Line Status Situation Modified Exclusive Shared Line valid? Yes Yes Yes External out-of- memory valid valid date is... goes to A write to does not does not go the bus this cache go to the to the bus and line... bus updates 4.6 Cache Replacement Description ...
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... In this case, the snoop requires the use of the cycle control signals and the data bus. The following sections describe the scenarios for the HOLD, AHOLD, and BOFF implementations. Am5 86 Microprocessor X AMD Invalid (EADS = 0 * INV = 1) + FLUSH = 0 Shared EADS = 0 * INV = 0 * FLUSH = 1 ...
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... AMD 4.8.2.2 HOLD Bus Arbitration Implementation The HOLD/HLDA bus arbitration scheme is used prima- rily in systems where all memory transfers are seen by the microprocessor. The HOLD/HLDA bus arbitration scheme permits simple write-back cache design while maintaining a relatively high performing system. Figure 3 shows a typical system block diagram for HOLD/HLDA bus arbitration ...
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... BOFF Note: The circled numbers in this figure represent the steps in section 4.8.2.2.2. CLK ADR M/IO W/R 1 ADS BLAST BRDY Data WB/WT BOFF Note: The circled numbers in this figure represent the steps in section 4.8.2.2.3. PRELIMINARY n n n+4 Figure 4. External Read n n Figure 5. External Write Am5 86 Microprocessor X AMD n+8 n+12 3 n+12 n ...
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... AMD CLK ADR INV EADS HITM HOLD HLDA Note: The circled numbers in this figure represent the steps in section 4.8.3.1. Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line CLK ADR INV EADS HITM HOLD HLDA Note: The circled numbers in this figure represent the steps in section 4.8.3.2. ...
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... If INV is 1, snooping is caused by a write access. EADS is not sampled again until after the modified line is written back to memory detected again as early as in Step 11. n n+4 n+8 n n+4 n+8 n+12 Am5 86 Microprocessor X AMD floating/tri-stated 11 6 valid ...
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... AMD Step 3 Two clock cycles after EADS is asserted, HITM becomes valid, and is 0 because the line is mod- ified. Step 4 In the next clock, the core system logic deas- serts the HOLD signal in response to the HITM = 0 signal. The core system logic backs off the current bus master at the same time so that the microprocessor can access the bus ...
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... The status of the addressed line is now either shared (INV = changed to invalid (INV = 1). 4.8.5.1 HOLD/HLDA Write-Back Design Considerations When designing a write-back cache system that uses HOLD/HLDA as the bus arbitration method, the follow- ing considerations must be observed to ensure proper operation (see Figure 10). Valid Hold Assertion Am5 86 Microprocessor X AMD 27 ...
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... AMD Step 1 During a snoop to the on-chip cache that hits a modified cache line, the HOLD signal cannot be deasserted to the microprocessor until the next clock cycle after HITM transitions active. Step 2 After the write-back has commenced, the HOLD signal should be asserted no earlier than the next clock cycle after ADS goes active, and no later than in the final BRDY of the last write ...
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... Step 6 With HITM going Low, the core system logic asserts BOFF in the next clock cycle to the snooping processor to reorder the access. BOFF overrides BRDY. Therefore, the partial read is not used reread later. Am5 86 Microprocessor X from CPU n+4 W n+8 W n+C AMD 29 ...
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... AMD CLK ADR R1 from CPU W1 to CPU M/IO CACHE W/R ADS BLAST BRDY BOFF AHOLD INV EADS HITM Data Note: The circled numbers in this figure represent the steps in section 4.8.6. Figure 13. Cycle Reordering with BOFF (Write-Back) Step 7 One clock cycle later BOFF is deasserted. The ...
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... Set the PWT bit in the page table entries. 2. Drive the WB/WT signal Low when accessing these memory locations. Option operating-system-level solution not di- rectly implemented by user-level code. Option 2, the hardware solution, is implemented at the system level. Am5 86 Microprocessor B+4 B+8 B+12 A AMD 31 ...
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... AMD 4.8.7.2 BOFF Write-Back Arbitration Implementation The use of BOFF to perform snooping of the on-chip cache is used in systems where more than one cache- able bus master resides on the microprocessor bus. The BOFF signal forces the microprocessor to relinquish the bus in the following clock cycle, regardless of the type of bus cycle it was performing at the time ...
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... Writ- ing back modified data adds to this minimum time. The flush operation can only be stopped by a RESET. Table 8 shows the special flush bus cycle configuration. Am5 86 Microprocessor X AMD Address B M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle ...
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... AMD Table 8. FLUSH Special Bus Cycles A32–A2 M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle 0000 0001h 0000 0001h 4.9.3 Snooping During Cache Flushing As with snooping during normal operation, snooping is permitted during a cache flush, whether initiated by the FLUSH pin or WBINVD instruction. After completion of the snoop, and write-back, if needed, the microproces- sor completes the copy-back of modified cache lines ...
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... No read or write after the last locked access is issued internally or on the bus until the final RDY or BRDY for all locked accesses possible to get a locked read, write-back, locked write cycle. Am5 86 Microprocessor X AMD XX4 XX8 XXC XX8 XXC XX4 35 ...
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... AMD 4.10.3 PLOCK Operation in Write-Through Mode As described in Section 3, PLOCK is only used in Write- through mode; the signal is driven inactive in Write-back mode. In Write-through mode, the processor drives PLOCK Low to indicate that the current bus transaction requires more than one bus cycle. The CPU continues to drive the signal Low until the transaction is completed, whether or not RDY or BRDY is returned ...
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... CPU entered the Stop Previous State Grant State. For minimum CPU power consumption, all Previous State other input pins should be driven to their inactive level Previous State while the CPU is in the Stop Grant state. Am5 86 Microprocessor X AMD Stop Grant Bus cycle 37 ...
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... AMD (valid for Write-back mode only) CLK STPCLK Sampled STPCLK NMI SMI Note Earliest time at which NMI or SMI is recognized. Figure 21. Recognition of Inputs when Exiting Stop Grant State A RESET or SRESET brings the CPU from the Stop Grant state to the Normal state. The CPU recognizes the inputs required for cache invalidations (HOLD, AHOLD, BOFF, and EADS) as explained later ...
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... SMM is intended for use only by system firmware, not by applications soft- ware or general purpose systems software. The SMM architectural extension consists of the follow- ing elements: System Management Interrupt (SMI) hardware in- terface Am5 86 Microprocessor X AMD 39 ...
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... AMD Dedicated and secure memory space (SMRAM) for SMI handler code and CPU state (context) data with a status signal for the system to decode access to that memory space, SMIACT Resume (RSM) instruction, for exiting SMM Special features, such as I/O Restart and I/O instruc- tion information, for transparent power management of I/O peripherals, and Auto HALT Restart 7 ...
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... SMI handler routine for the CPU (from the completion of the interrupted instruction) is given by: Latency to start of SMl handler = 161 clocks and the minimum time required to return to the interrupt- ed application (following the final SMM instruction be- fore RSM) is given by: Latency to continue application = 258 clocks Am5 86 Microprocessor X AMD 41 ...
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... AMD T1 T2 CLK CLK2 SMI ADS RDY SMIACT A: Last RDY from non-SMM transfer to SMIACT assertion B: SMIACT assertion to first ADS for SMM state save C: SMM state save (dependent on memory performance) D: SMI handler E: SMM state restore (dependent on memory performance) F: Last RDY from SMM transfer to deassertion of SMIACT G: SMIACT deassertion of first non-SMM ADS 7 ...
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... In this case, the suspend SMI handler should read these registers directly to save them and restore them during the power up resume. Anytime the SMI handler changes these registers in the CPU, it must also save and restore them. Am5 86 Microprocessor X AMD 43 ...
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... AMD 7.4 Entering System Management Mode SMM is one of the major operating modes, along with Protected mode, Real mode, and Virtual mode. Figure 27 shows how the processor can enter SMM from any of the three modes and then return. Real mode Reset or Reset RSM ...
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... In SMM, the CPU can access or jump anywhere within the 4-Gbyte logical address space. The CPU can also indirectly access or perform a near jump anywhere with- in the 4-Gbyte logical address space. Am5 86 Microprocessor X AMD 1 Base Attributes Limit 16-bit, 30000h 4 Gbytes ...
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... AMD 7.7.1 Exceptions and Interrupts with System Management Mode When the CPU enters SMM, it disables INTR interrupts, debug, and single step traps by clearing the EFLAGS, DR6, and DR7 registers. This prevents a debug appli- cation from accidentally breaking into an SMI handler. This is necessary because the SMI handler operates ...
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... For REP instructions, the external chip set should return a valid SMI within the first access. Bit 0 indicates whether the opcode that was accessing the I/O location was performing either a read ( write (0) operation as indicated by the R/W bit. Am5 86 Microprocessor X AMD 0 Register offset 7F00h I/O instruction restart slot 15–2 1 Reserved Valid I/O Instruction ...
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... AMD If an SMI occurs and it does not trap an I/O instruction, the contents of the I/O address and R/W bit are unpre- dictable and should not be used. 7.7.6 SMM Base Relocation The Am5 86 CPU family provides a new control regis- X ter, SMBASE. The SMRAM address space can be mod- ified by changing the SMBASE register before exiting an SMI handler routine ...
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... A20M must be driven inactive before the first cycle of the SMM state save, and must be returned to its original level after the last cycle of the SMM state restore. This can be done by blocking the assertion of A20M when SMIACT is active. Am5 86 Microprocessor X AMD 86 CPUs provides this function ...
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... AMD State Save SMI SMIACT Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode with Caching Enabled During SMM State Save SMI SMIACT WB/WT Note: For proper operation of systems configured in Write-back mode when caching during SMM is allowed, force WB/WT Low to force all caching to be write-through during SMM. ...
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... Cache must be empty Figure 38. SMM Timing in Systems Using Overlaid Memory Spaces and Configured in Write-Back Mode PRELIMINARY SMI Handler SMI Handler State SMI Handler Save RSM Am5 86 Microprocessor X AMD Instruction x+1 Normal State Cycle Resume RSM Cache contents invalidated Instruction x+1 Normal State Cycle Resume ...
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... AMD 7.8.4 CPU Reset During SMM The system designer should take into account the fol- lowing restrictions while implementing the CPU Reset logic: 1. When running software written for the 80286 CPU, a CPU RESET switches the CPU from Protected mode to Real mode. RESET and SRESET have a higher priority than SMI ...
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... Table 17. Test Register TR4 Bit Descriptions 25–24 23–22 21–20 19–16 Tag ST2 ST1 ST0 Reserved 18–17 16 15–12 Set State Reserved Not used Not used Am5 86 Microprocessor X AMD 86 microproces- X 15– 9–7 6–3 2–0 Valid Not 0 Valid LRU (rd) used Valid Not Not used Valid ...
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... AMD STn (bits 30–29): Read Only, available only in Write- back mode when Ext=1 in TR5. STn returns the sta- tus of the set (ST3, ST2, ST1, or ST0) specified by the TR5 Set State field (bits 18–17) during cache look-ups. Returned values are: — invalid — ...
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... For the standard Am486 processor, the Enhanced Am486 processor, and the Am5 CLKMUL pin is driven High at RESET, the processor uses a Clock-tripled mode. To ensure correct operation of the 133-MHz Am5 processor, always connect the CLKMUL input to V Am5 86 Microprocessor X AMD processor, if the ...
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... PRELIMINARY When the parameter passed in EAX is zero, the register values returned upon instruction execution are: The values in EBX, ECX, and EDX indicate an AMD microprocessor. When taken in the proper order: EBX (least significant bit to most significant bit) EDX (least significant bit to most significant bit) ...
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... For reliable operation, always connect unused inputs appropriate signal level. Active Low inputs should be connected to V the range plane. CC puts should be connected to GND. 86 CPU to X Am5 86 Microprocessor X AMD through a pull-up resistor. Pull-ups in CC are recommended. Active High in- 57 ...
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... AMD ABSOLUTE MAXIMUM RATINGS Case Temperature under Bias . . . – 65°C to +110°C Storage Temperature . . . . . . . . . . – 65°C to +150°C Voltage on any pin with respect to ground . . . . . . – 0 Supply voltage with respect – Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure ...
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... Am5 86 Microprocessor X AMD Figure Notes Note 2 39 Adjacent Clocks Notes 3 and 4 39 Note 3 39 Note 3 39 Note 3 39 Note 3 Note 5 40 Note Note Note ...
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... AMD Am5 86 Microprocessor AC Characteristics for X Boundary Scan Test Signals at 25 MHz V = 3.3 V ±0 0°C to +85° CASE Symbol Parameter t TCK Frequency 24 t TCK Period 25 t TCK High Time TCK Low Time at 0 TCK Rise Time (0.8 V–2 V) ...
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... Don’t care; any change permitted Does not apply Figure 39. CLK Waveforms Figure 40. Output Valid Delay Timing Am5 86 Microprocessor X Outputs Will be steady Will change from Will change from Changing; state unknown Center line is High-impedance “Off” state AMD 61 ...
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... AMD 62 PRELIMINARY Figure 41. Maximum Float Delay Timing Figure 42. PCHK Valid Delay Timing Am5 86 Microprocessor X ...
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... PRELIMINARY Figure 43. Input Setup and Hold Timing Figure 44. RDY and BRDY Input Setup and Hold Timing Am5 86 Microprocessor X AMD 63 ...
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... AMD 64 PRELIMINARY Figure 45. TCK Waveforms Figure 46. Test Signal Timing Diagram Am5 86 Microprocessor X ...
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... MHz 54.3 C 69.6 C 133 MHz 75.8 C 77.0 C for SQFP Package by Clock Frequency A Clock 133 MHz Am5 86 Microprocessor X AMD = Junction, Ambient, and Case Temperature = Junction-to-Case and Junction-to-Ambient Thermal Resistance, respectively = Maximum Power Consumption and are given in Table 21 for the 14.0 and = 1. ...
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... AMD 13 PHYSICAL DIMENSIONS Index Corner 1.595 1.605 1.735 1.765 Bottom View (Pins Facing Up) Notes: 1. All measurements are in inches. 2. Not to scale. For reference only. 3. BSC is an ANSI standard for Basic Space Centering. 66 PRELIMINARY 168-Pin PGA 1.735 1.765 1.595 1.605 Am5 86 Microprocessor X Base Plane Seating Plane 0 ...
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... All measurements are in millimeters unless otherwise noted. 2. Not to scale. For reference only. Trademarks AMD, Am386, and Am486 are registered trademarks and Am5 FusionPC is a service mark of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corp. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...