CL-PD6729-QC-E Cirrus Logic, Inc., CL-PD6729-QC-E Datasheet
CL-PD6729-QC-E
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CL-PD6729-QC-E Summary of contents
Page 1
... The chip also provides a Suspend mode, which stops the internal clock, and an automatic Low-power Dynamic mode, which stops transactions on the PCMCIA bus, stops internal clock distribution, and turns off much of the internal circuitry. PCMCIA SOCKET 1 CL-PD6729 208-Pin PQFP ...
Page 2
... PC applications typically access PCMCIA cards through the socket/card-services software interface. To assure full compatibility with existing socket/card- services software and PC-card applications, the reg- ister set in the CL-PD6729 is a superset of the Intel 82365SL register set. Notebook Computer Design Priorities Small Form Factor ...
Page 3
... Power-On Setup................................................. 24 4. REGISTER DESCRIPTION CONVENTIONS................................... 25 5. PCI-CONFIGURATION REGISTERS . 26 5.1 Vendor ID and Device ID.................................... 26 5.2 Command and Status ........................................ 27 5.3 Revision ID and Class Code .............................. 29 5.4 Cache Line Size, Latency Timer, Header Type, and BIST ................................................................... 30 5.5 Base Address 0.................................................. 31 5.6 Interrupt Line/Pin, Min_Gnt, and Max_Lat......... 32 6. OPERATION REGISTERS .................. 33 6.1 Index................................................................... 33 6 ...
Page 4
... Operation registers for device identification. 10.1 Misc Control 1 register is updated with the Mul- timedia Enable bit description. 10.3 Timer Clock Divide bit is removed from the Misc Control 2 register since the PCMCIA interface is set to operate at half the PCI_CLK or EXT_CLK frequency. 10.5 Speaker_Is_LED_Input description is changed. ...
Page 5
... In this document, the names of the CL-PD6729 inter- nal registers are bold-faced. For example, Chip Revi- sion and Power Control are register names. The names of bit fi ...
Page 6
... IRQ3/INTA# 204 IRQ4/INTB# 205 IRQ5/INTC# 206 IRQ7/INTD# 207 RST# 208 NC 6 PIN INFORMATION +5V CL-PD6729 208-Pin PQFP PCI_VCC Figure 2-1. CL-PD6729 Pin Diagram PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter 104 A_A7 A_A24 103 A_SOCKET_VCC A_SOCKET_VCC 102 A_A12 101 A_A23 100 A_A15 99 ...
Page 7
... AD[0] is pin 57 The quantity (Qty.) column indicates the number of pins used (per socket where applicable). The I/O-type code (I/O) column indicates the input and output configurations of the pins on the CL-PD6729. The possible types are defined below. The power-type code (Pwr.) column indicates the output drive power source for an output pin or the pull-up power source for an input pin on the CL-PD6729. The possible types are defi ...
Page 8
... Device Select: The CL-PD6729 drives this output active (low) when it has decoded the PCI address as one that it is programmed to support, thereby acting as the target for the current PCI cycle. PERR# Parity Error: The CL-PD6729 drives this output active (low detects a data parity error during a write phase ...
Page 9
... C/BE[3:0]#. PCI_CLK PCI Clock: This input provides timing for all trans- actions on the PCI bus to and from the CL-PD6729. All PCI bus interface signals described in this table (Table 2-1), except RST#, INTA#, INTB#, INTC#, and INTD#, are sampled on the rising edge of PCI_CLK ...
Page 10
... Although there is no specific mapping requirement for connecting interrupt lines from the CL-PD6729 to the system, a common use is to connect this pin to the system IRQ4 signal or to the PCI bus INTB# signal ...
Page 11
... I/O reads from the socket to the CL-PD6729. -IOWR I/O Write: This output goes active (low) for I/O writes from the CL-PD6729 to the socket differentiate the sockets, all socket-specific pins have either prepended to the pin names indicated. For exam- ple, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. ...
Page 12
... PC Card socket’s - INPACK pin. RDY/-IREQ † Ready / Interrupt Request: In Memory Card Interface mode, this input indicates to the CL-PD6729 that the card is either ready or busy. In I/O Card Interface mode, this input indicates a card interrupt request. -WAIT † ...
Page 13
... The socket interface outputs (listed in this table, Table 2-2) will operate at the voltage applied to these pins, independent of the voltage applied to other CL-PD6729 pin groups. Connect these pins to the V supply of the socket (pins 17 and 51 of the respective PCMCIA socket differentiate the sockets, all socket-specifi ...
Page 14
... This active-high output controls the socket V supply to the socket’ and V 2 pins. The active-high level of PP this output is mutually exclusive with that of VPP_PGM. VPP_PGM This active-high output controls the pro- gramming voltage supply to the socket’ and V 2 pins. The active-high ...
Page 15
... CORE_VDD This pin provides power to the core circuitry of the CL-PD6729. It can be connected to either a 3.3- or 5-volt power supply, independent of the operating voltage of other interfaces. For power conservation on a system with a 3.3-volt supply available, this pin should be connected to the 3 ...
Page 16
... The CL-PD6729 is backward-compatible with PCMCIA standards 1.0, 2.0, and 2.01. The CL-PD6729 is also compatible with JEIDA 4.1 and its earlier standards cor- responding with the PCMCIA standards above. 16 INTRODUCTION TO THE CL-PD6729 ...
Page 17
... The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets: Timing Timer Set 0 or Timer Set 1. CAUTION: The windows of the CL-PD6729 should never be allowed to overlap with each other or the other devices in the system. This would cause signal collisions, resulting in erratic behavior. January 1997 PRELIMINARY DATA SHEET v ...
Page 18
... Start Address Registers System Memory Map Upper Address Register (selects 16-Mbyte page) Page 1 Page 0 Figure 3-1. Memory Window Organization PCI I/O Address Space System I/O Map End Address Registers System I/O Map Start Address Registers 18 INTRODUCTION TO THE CL-PD6729 4 Gbytes Memory . . . . Memory Window 16-Mbyte Page . . Card Memory Map ...
Page 19
... DAC. It allows the PC Card to directly write video data to an input port of a graphics controller and audio data to a digital-to-analog converter. The CL-PD6729 supports the ZV Port in the “bypass” mode during which the signals are directly routed from the PC Card bus to the video port of the VGA controller ...
Page 20
... Battery dead indicator (BVD1) or I/O-type card status change (STSCHG) Ready (RDY) status change on a PCMCIA mem- ory-type card Either class of interrupts can be routed to any of the ten interrupt pins on the CL-PD6729. 3.1.4.2 Connection of Interrupt Pins Programmed as PCI-Bus INT# Signals Pins programmed as INT#-type interrupts can be connected to the correspondingly named signals on the PCI bus ...
Page 21
... IRQ14/EXT_CLK can alternately be configured as an external clock input (EXT_CLK). When configured in External Clock mode by programming Misc Control 2 register bit ‘1’, IRQ14/EXT_CLK acts as a clock input, bringing in an external clock that drives the CL-PD6729 circuitry whenever the PCI bus is inactive. Similarly, IRQ15/RI_OUT* can alternately be confi ...
Page 22
... If Extension Control PP 1 register bit ‘1’, Power Control register bit 4 is prevented from being automatically cleared when a card is removed. The CL-PD6729 can also be config- ured to have management interrupts notify software of card removal. Card Insertion At reset, and whenever there is no card in a socket, power to the socket is off ...
Page 23
... CL-PD6729 PCI-to-PCMCIA Host Adapter 3.1.8 Bus Sizing The CL-PD6729 operates in 32-bit mode. All PCI transactions are 32-bit, even when supporting 8-bit- only or 16-bit PCMCIA cards. 3.1.9 Programmable PCMCIA Timing The Setup, Command, and Recovery time for the PCMCIA bus is programmable (see CL-PD6729 can be programmed to match the timing requirements of any PCMCIA card ...
Page 24
... Power-On Setup Following RST#-activated reset, the CL-PD6729 must be configured by host initialization or BIOS soft- ware. The application of the RST# signal on power-up causes initialization of all the CL-PD6729 register bits and fields to their reset values. PRELIMINARY DATA SHEET v.2.0 CL-PD6729 Register indexes ...
Page 25
... Similarly, the phrase “the system resets a bit” or “the system clears a bit” is the same as stating “the system writes the appropriate register with a ‘0’ (zero) in the bit”. ...
Page 26
... Group. This field always reads back 1013h. Bits 31-16: Device ID This read-only field is the device identification assigned to this device by Cirrus Logic. This field always reads back 1100h for the CL-PD6729. (Revision number identification for the CL-PD6729 part itself is indicated by the Mask Revision byte at extended index 34h. 26 ...
Page 27
... R:1 RW:0 Bit 0: PCI I/O Space Enable The I/O space for the CL-PD6729 is disabled. Any reads or writes to the I/O space will be ignored. This 0 applies to both the I/O registers of the CL-PD6729 itself, as well as any I/O windows that might have been enabled to the PCMCIA sockets. The I/O space for the CL-PD6729 is enabled and will respond to reads and writes to the I/O address 1 range defi ...
Page 28
... Bit 8 of this register must be set before system errors can be reported, and bit 6 must be set to allow address parity errors to be detected. The CL-PD6729 only asserts SERR# if address parity errors occur. No other chip or system actions will cause SERR driven active ...
Page 29
... Byte 0 Revision ID a This read-only value depends on the revision level of the CL-PD6729. For CL-PD6729 Revision E or later, these bits corre- spond to the value of the Mask Revision Byte register at extended index 34h. Bits 7-0: Revision ID This read-only field identifies the revision level of the CL-PD6729 chip. ...
Page 30
... BIST test features. Bits 23:16 Header Type Register These bits will always read back 00h and specifies that the CL-PD6729 uses the standard type 00 configuration space header register layout for configuration bytes 10h through 3Fh. Bits 31:24 Latency Timer Register Since the CL-PD6729 does not use bus mastering, this bit fi ...
Page 31
... CL-PD6729 PCI-to-PCMCIA Host Adapter 5.5 Base Address 0 Configuration Register Name: Base Address 0 Offset: 10h Bit 31 Bit 30 Byte 3 Bit 23 Bit 22 Byte 2 Bit 15 Bit 14 Byte 1 Bit 7 Bit 6 Byte 0 This is the PCI I/O address space base address for the Operation registers. Bit 0: I/O Space Indicator This bit always reads back a ‘1’, indicating that this base address register defines a PCI I/O space. ...
Page 32
... Bits 31-24: Max_Lat This field indicates the maximum time that can occur between PCI bus accesses to the CL-PD6729 while still efficiently performing transfers to or from PCMCIA cards. The value pro- grammed is in 250-ns increments, based on full-speed PCI_CLK operation. This field always reads back 00h, indicating that there are no major latency requirements. ...
Page 33
... PCI-to-PCMCIA Host Adapter 6. OPERATION REGISTERS The CL-PD6729’s internal Device Control, Window Mapping, Extension, and Timing registers are accessed through a pair of Operation registers — an Index register and a Data register. The Index register is accessed at the address programmed in the Base Address 0 register, and the Data register (see page 37) is accessed by adding 1 to the address programmed in Base Address 0 ...
Page 34
... Memory Window 1Bh 5Bh Mapping 1Ch 5Ch 1Dh 5Dh a 1Eh Chapter 10: a Extension 1Fh 20h 60h Chapter 9: 21h 61h Memory Window Mapping 22h 62h PRELIMINARY DATA SHEET v.2.0 CL-PD6729 Page Number ...
Page 35
... CL-PD6729 PCI-to-PCMCIA Host Adapter Table 6-1. Index Registers (cont.) Register Name System Memory Map 2 End Address High Card Memory Map 2 Offset Address Low Card Memory Map 2 Offset Address High ATA Control Scratchpad System Memory Map 3 Start Address Low System Memory Map 3 Start Address High ...
Page 36
... This register is only applicable for the extended index 2F register. 36 OPERATION REGISTERS (cont.) Index Value Socket A Socket B 3Ah 7Ah 3Bh 7Bh 3Ch 7Ch 3Dh 7Dh 3Eh 7Eh 3Fh 7Fh 80h–FFh PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Page Chapter Number Chapter 11: Timing – – January 1997 . ...
Page 37
... CL-PD6729 PCI-to-PCMCIA Host Adapter 6.2 Data Register Name: Data Index: n/a Bit 7 Bit 6 The Data register is accessed at Base Address This register indicates the contents of the register at the Socket/Register Index selected by the Index register. January 1997 PRELIMINARY DATA SHEET v.2.0 Bit Bit Bit ...
Page 38
... These bits will always read back as ‘0’. Bits 7-6: Interface ID 00 I/O only. 01 Memory only. 10 Memory and I/O. 11 Reserved. These bits identify what type of interface this controller supports. The CL-PD6729 supports both memory and I/O interface PCMCIA cards. 38 DEVICE CONTROL REGISTERS Bit Bit Bit ...
Page 39
... Ready/Busy R:1 R:0 a Bit 7 always reads a ‘1’ on the CL-PD6729. b Bit 5 indicates the value of the RDY/-IREQ pin (see page 12). c Bit 4 indicates the value of the WP/-IOIS16 pin (see page 12). d Bits 3-2 indicate the inversion of the values of the -CD1 and -CD2 pins (see page 12). ...
Page 40
... Bit 6: Card Power On 0 Power to the card is not on. 1 Power to the card is on. This status bit indicates whether power to the card is on. Refer to the 40 DEVICE CONTROL REGISTERS CL-PD6729 PCI-to-PCMCIA Host Adapter Table 7–1 for more details. January 1997 PRELIMINARY DATA SHEET v.2.0 . ...
Page 41
... Inactive (low) Activated per Activated per Power Control Misc Control 1 register, register, bit 1 bits 1 and 0 Inactive (high) Inactive (low) Activated per Activated per Power Control Misc Control 1 register, register, bit 1 bits 1 and 0 CL-PD6729 Output Signals to Socket DEVICE CONTROL REGISTERS Bit 0 and 41 ...
Page 42
... V and V CC both active (low). When this bit is set to a ‘1’, the CL-PD6729 allows power to the card to be turned on and off automatically with the insertion and removal of a PCMCIA card. Bit 7: Card Enable 0 Outputs to card socket are not enabled and are floating. ...
Page 43
... Reserved. No hardware function in the CL-PD6729. This bit was created to determine how management interrupts occur on ISA-based systems included for software compatibility. Because there is no -INTR pin on the PCI bus, setting this bit to a ‘1’ would cause management interrupts not to occur. ...
Page 44
... In I/O Card Interface mode, this bit determines whether the -STSCHG input pin is used to activate the IRQ15 pin in conjunction with the IRQ15 Is RI Out bit (Misc Control 2 bit 7, see page 62). This bit is not valid in Memory Card Interface mode. 44 DEVICE CONTROL REGISTERS CL-PD6729 PCI-to-PCMCIA Host Adapter January 1997 PRELIMINARY DATA SHEET v.2.0 . ...
Page 45
... R:0 R:0 This register indicates the source of a management interrupt generated by the CL-PD6729. NOTE: The corresponding bit in the Management Interrupt Configuration register must be set to a ‘1’ to enable each specific status change detection. Bit 0: Battery Dead Or Status Change 0 A transition (from high to low in Memory Card Interface mode or either high to low or low to high in I/O Card Interface mode) on the BVD1/-STSCHG/-RI pin has not occurred since this register was last read ...
Page 46
... DEVICE CONTROL REGISTERS Bit Bit Bit Card Detect Enable RW:0 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Register Per: socket Register Compatibility Type: 365 Bit Bit Bit 2 1 Battery Dead Battery Or Status Ready Enable ...
Page 47
... IRQ12 1101 Reserved 1110 IRQ14 (This output can alternately be used as external clock input.) 1111 IRQ15 (This output can alternately be used as ring indicate output.) These bits determine which interrupt pin will be used for card status change management inter- rupts. January 1997 PRELIMINARY DATA SHEET v ...
Page 48
... DEVICE CONTROL REGISTERS Bit Bit Bit Memory Map Memory Map Bit 4 Enable 3 Enable R:0 RW:0 RW:0 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Register Per: socket Register Compatibility Type: 365 Bit Bit Bit 2 1 Memory Map Memory Map Memory Map 2 Enable 1 Enable 0 Enable RW:0 ...
Page 49
... CL-PD6729 PCI-to-PCMCIA Host Adapter Bit 6: I/O Map 0 Enable 0 I/O Window Mapping registers for I/O Window 0 disabled. 1 I/O Window Mapping registers for I/O Window 0 enabled. When this bit is a ‘1’, the I/O Window Mapping registers for I/O Window 0 are enabled and the con- troller will respond to I/O accesses in the I/O space defined by those registers. ...
Page 50
... I/O WINDOW MAPPING REGISTERS Bit Bit Bit Timing I/O Window 1 Register Size Select 0 RW:0 RW:0 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Register Per: socket Register Compatibility Type: 365 Bit Bit 2 1 Compatibility Auto-Size I/O I/O Window 0 Bit Window 0 RW:0 RW:0 Chapter 11) for I/O Window 0. January 1997 ...
Page 51
... CL-PD6729 PCI-to-PCMCIA Host Adapter Bit 7: Timing Register Select 1 0 Accesses made with timing specified in Timer Set 0. 1 Accesses made with timing specified in Timer Set 1. This bit determines the access timing specification (see 8.2 System I/O Map 0-1 Start Address Low ...
Page 52
... Bit End Address 7-0 RW:00000000 Bit Bit Bit End Address 15-8 RW:00000000 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Register Per: socket Register Compatibility Type: 365 Bit Bit Bit Register Per: socket Register Compatibility Type: 365 Bit Bit Bit ...
Page 53
... CL-PD6729 PCI-to-PCMCIA Host Adapter 8.6 Card I/O Map 0-1 Offset Address Low Register Name: Card I/O Map 0-1 Offset Address Low Index: 36h, 38h Bit Bit This bit must be programmed to ‘0’. There are two separate Card I/O Map Offset Address Low registers, each with identical fields. These reg- ...
Page 54
... The most-significant four bits are located in the System Memory Map 0-4 Start Address High register. 54 MEMORY WINDOW MAPPING REGISTERS Bit Bit Bit Start Address 19-12 RW:00000000 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter page 67) is equal to the upper PCI address. Register Per: socket Register Compatibility Type: 365 Bit Bit 2 1 January 1997 . Bit ...
Page 55
... CL-PD6729 PCI-to-PCMCIA Host Adapter 9.2 System Memory Map 0-4 Start Address High Register Name: System Memory Map 0-4 Start Address High Index: 11h, 19h, 21h, 29h, 31h Bit Bit 7 6 Window Data Compatibility Size Bit RW:0 RW:0 There are five separate System Memory Map Start Address High registers, each with identical fields. ...
Page 56
... Selects Timer Set 0. 01 Selects Timer Set 1. 10 Selects Timer Set 1. 11 Selects Timer Set 1. This field selects the timer set. Timer Set 0 and 1 reset to values compatible with standard PCI and three-wait-state cycles (see page 74). 56 MEMORY WINDOW MAPPING REGISTERS Bit Bit Bit 5 4 ...
Page 57
... CL-PD6729 PCI-to-PCMCIA Host Adapter 9.5 Card Memory Map 0-4 Offset Address Low Register Name: Card Memory Map 0-4 Offset Address Low Index: 14h, 1Ch, 24h, 2Ch, 34h Bit Bit 7 6 There are five separate Card Memory Map Offset Address Low registers, each with identical fields. These ...
Page 58
... Writes to the card through this window are allowed. 1 Writes to the card through this window are inhibited. This bit determines whether writes to the card through this window are allowed. 58 MEMORY WINDOW MAPPING REGISTERS CL-PD6729 PCI-to-PCMCIA Host Adapter January 1997 PRELIMINARY DATA SHEET v.2.0 . ...
Page 59
... When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in Figure 10-1 and allows for interrupt sharing. This bit selects Level or Pulse mode operation of the IRQ[XX] pin (see page 9). Note that a clock must be present on PCI_CLK or IRQ14/EXT_CLK for pulsed interrupts to work. Refer to Section 13 ...
Page 60
... Bit 7: Inpack Enable 0 No effect effect. The -INPACK function is not applicable in PCI bus environments. This bit is provided for compati- bility with other Cirrus Logic products. Its setting has no effect on operations of the CL-PD6729. 60 EXTENSION REGISTERS CL-PD6729 PCI-to-PCMCIA Host Adapter January 1997 PRELIMINARY DATA SHEET v ...
Page 61
... CL-PD6729 PCI-to-PCMCIA Host Adapter 10.2 FIFO Control Register Name: FIFO Control Index: 17h Bit Bit 7 6 FIFO Status / Flush FIFO RW:1 Bit 7: FIFO Status / Flush FIFO Value I/O Read 0 FIFO not empty 1 FIFO empty This bit controls FIFO operation and reports FIFO status. When this bit is set to a ‘1’ during write operations, all data in the FIFO is lost. During read operations, when this bit is a ‘ ...
Page 62
... IRQ14/EXT_CLK will be internally divided by two and used as the internal clock for the socket interfaces. This feature facilitates PCMCIA transfer cycles when the PCI bus clock is stopped to conserve power. When set to a ‘0’, the PCI_CLK input is divided by two and used as the internal clock, which drives the socket interfaces and specifies their timing. ...
Page 63
... Identification R:11 a This read-only value depends on the revision level of the CL-PD6729 chip. A value of 21h/E1h indicates the chip uses extended registers 34h-3Bh to indicate chip revision and features. Bits 5-0: CL-PD6729 Revision Level This field identifies the revision of the controller. Contact Cirrus Logic for more information on re- vision levels for the CL-PD6729 ...
Page 64
... This bit has no hardware control function when not in ATA mode. 64 EXTENSION REGISTERS Bit Bit Bit A22 A21 RW:0 RW:0 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter Register Per: socket Register Compatibility Type: ext. Bit Bit Bit 2 1 Speaker Is Scratchpad Bit ATA Mode LED Input RW:0 ...
Page 65
... CL-PD6729 PCI-to-PCMCIA Host Adapter Bit 7: A25/CSEL In ATA mode, the value in this bit is applied to the ATA A25 pin and is vendor-specific. Certain ATA drive vendor-specific performance enhancements beyond the PCMCIA 2.1 standard can be con- trolled through use of this bit. This bit has no hardware control function when not in ATA mode. ...
Page 66
... LED activity disabled. 1 LED activity enabled. This bit allows the LED_OUT* pin to reflect any activity in the card. Whenever PCMCIA cycles are in process to or from a card in either socket, LED_OUT* will be active low. Bit 3: Invert Card IRQ Output 0 The card IRQ is active-high. ...
Page 67
... CL-PD6729 PCI-to-PCMCIA Host Adapter Bit 4: Invert Management IRQ Output 0 The management IRQ is active-high. 1 The management IRQ is active-low and open-drain. This bit changes the active-high, ISA-type management IRQ level to an active-low, open-collector output that complies with PCI bus requirements. Bit 5: Pull-Up Control 0 Pull-ups on VS2, VS1, CD2, and CD1 are in use ...
Page 68
... Contact Cirrus Logic representatives for the value corresponding to a particular revision of the CL-PD6729. Bits 7:0 — Mask Revision These bits indicate the mask revision of the device. Contact Cirrus Logic representatives for infor- mation on correlating revision numbers with the value of this field. ...
Page 69
... Bit 21: GPSTB Capable A value of ‘1’ in this field is intended to indicate that a Cirrus Logic device supports general-pur- pose strobe. Note that even though the CL-PD6729 may report this bit as ‘1’, it DOES NOT support the general-purpose strobe. Bit 20: RFU (Reserved for Future Use) Reserved for future use ...
Page 70
... Bits 30:27: RFU (Reserved for Future Use) Reserved for future use. Bit 26: CLKRUN Support A ‘0’ indicates that the CL-PD6729 does not output a CLKRUN signal for the PCI Mobile Specifi- cation signaling for control of system clock turn on/turn off. Bit 25: LOCK# Support A ‘ ...
Page 71
... A ‘1’ indicates that in the system implementation, a pin on the device designated as a hardware control of suspend for deep power saving has been connected to system circuitry designed for power management. Since the CL-PD6729 has no hardware suspend pin, this bit should remain cleared to ‘0’. ...
Page 72
... A value of ‘0’ indicates that 5.0 V voltage source is not available for the powering of PC- cards in this system, and that the PC card sockets only operate at other available voltages indi- cated by bits 43:41. Systems that only supported 5 V cards set bit 41 to ‘1’ and clear bits 43, 42, and 40 to ‘0’. ...
Page 73
... Reserved for future use. Bit 62 — Clk Opt. Wired A value of ‘1’ indicates that in the particular system implementation, an external clock has been wired to the CL-PD6729 EXT_CLK pin. A value of ‘0’ indicates that an external clock is being con- nected. Bits 61:58 — RFU (Reserved for future use) Reserved for future use. Bit 57 — ...
Page 74
... The Setup Timing register for each timer set controls how long a PCMCIA cycle’s command (that is, -OE, -WE, -IORD, -IOWR; see page 11) setup time will be, in terms of the number of internal clock cycles. The overall command setup timing length S is programmed by selecting a 2-bit prescaling value (bits 7-6 ...
Page 75
... The Command Timing register for each timer set controls how long a PCMCIA cycle’s command (that is, -OE, -WE, -IORD, -IOWR; see page 11) active time will be, in terms of the number of internal clock cycles. The overall command timing length C is programmed by selecting a 2-bit prescaling value (bits 7-6 of this ...
Page 76
... Recovery Timing 1 The Recovery Timing register for each timer set controls how long a PCMCIA cycle’s command (that is, -OE, -WE, -IORD, -IOWR; see page 11) recovery time will be, in terms of the number of internal clock cycles. The overall command recovery timing length R is programmed by selecting a 2-bit prescaling value (bits ...
Page 77
... ATA disk interface. Table 12-1 lists each interface pin and its function when a CL-PD6729 card socket is operating in ATA mode. All register functions of the CL-PD6729 are available in ATA mode, including socket power control, inter- face signal disabling, and card window control. No memory operations are allowed in ATA mode. ...
Page 78
... Socket Pin Interface Number Function -IOIS16 34 Ground a Not supported by the CL-PD6729. 78 ATA MODE OPERATION (cont.) PCMCIA ATA Interface Socket Pin Function Number n/c 56 n/c 57 n/c 58 n ...
Page 79
... CL-PD6729 PCI-to-PCMCIA Host Adapter 13. ELECTRICAL SPECIFICATIONS 13.1 Absolute Maximum Ratings Description Ambient temperature under bias Storage temperature Voltage on any pin (with respect to ground) Operating power dissipation Power dissipation during Suspend mode a Power supply voltage a Injection current (latch up) a Stresses above those listed may cause permanent damage to system components. These are stress ratings only ...
Page 80
... V respective SOCKET_VCC = 3.0V At rated I SOCKET_VCC V – 0.5 respective SOCKET_VCC = 3.0V 0 rated I Respective SOCKET_VCC = 3.0V Respective SOCKET_VCC = 3.0V Respective SOCKET_VCC = 3.0V PRELIMINARY DATA SHEET v.2.0 CL-PD6729 core voltage = 3.0V, DD core voltage = 4.5V, DD core voltage = 3.6V, DD core voltage = 5.5V, DD core voltage = 4.5V, DD core voltage = 5.5V OHC SOCKET_VCC – 0.5V OHC = 0.4V OL January 1997 ...
Page 81
... Output current low OL a When CORE_VDD is 3.3V, input thresholds are TTL-compatible; when CORE_VDD is 5V, input thresholds are CMOS-com- patible. b The value of the input threshold level is dependent on the voltage applied to the CORE_VDD pin of the CL-PD6729. January 1997 PRELIMINARY DATA SHEET v.2.0 MIN MAX Unit Conditions 4 ...
Page 82
... V +5V pin voltage = 5.5V 2.4 V +5V pin voltage = 4.5V, I +5V volt- V +5V pin voltage = 4.5V, I age – 0.5 0.4 V Respective +5V pin voltage = 4.5V Respective +5V pin voltage = 4.5V OHC Respective +5V pin voltage = 4.5V PRELIMINARY DATA SHEET v.2.0 CL-PD6729 = 2.4V = +5V pin voltage – 0.5V = 0.4V January 1997 . ...
Page 83
... Symbol Parameter Power supply current, Icc tot(1) operating Power supply current, Icc Suspend mode tot(2) (Misc Control 2, bit 2 = ‘1’) Power supply current, Icc RST# active, tot(3) no clocks January 1997 PRELIMINARY DATA SHEET v.2.0 MIN TYP MAX <6 8 >20 6 <250 MIN TYP MAX <8 12 > ...
Page 84
... AC Timing Specifications This section includes system timing requirements for the CL-PD6729. Unless otherwise specified, timings are provided in nanoseconds (ns), at TTL input levels, with the ambient temperature varying from and V varying from 3.0V to 3.6V or 4.5V to 5.5V DC. The PCI bus speed is 33 MHz unless oth- CC erwise specifi ...
Page 85
... FRAME# setup to PCI_CLK 1 t AD[31:0] (address) setup to PCI_CLK 2 t AD[31:0] (address) hold from PCI_CLK 3 t AD[31:0] (data) setup to PCI_CLK 4 t AD[31:0] (data) active to HI-Z from PCI_CLK 5 t C/BE[3:0]# (bus command) setup to PCI_CLK 6 t C/BE[3:0]# (bus command) hold from PCI_CLK 7 t C/BE[3:0]# (byte enable) setup to PCI_CLK 8 t DEVSEL# delay from PCI_CLK ...
Page 86
... PCI_CLK FRAME# AD[31:0] Address Write Cycle AD[31:0] Address Read Cycle Bus C/BE[3:0]# Command HI-Z DEVSEL# HI-Z TRDY# HI-Z STOP# HI-Z = high impedance Figure 13-1. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL# (PCI 86 ELECTRICAL SPECIFICATIONS Data Byte Enable t 9 PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter ...
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... TRDY# active delay from PCI_CLK 1 t TRDY# inactive delay from PCI_CLK 2 t TRDY# high before HI STOP# active delay from PCI_CLK 4 t STOP# inactive delay from PCI_CLK 5 t STOP# high before HI-Z 6 PCI_CLK FRAME# HI-Z TRDY# HI-Z STOP# HI-Z = high impedance Figure 13-2. TRDY# and STOP# Delay (PCI January 1997 PRELIMINARY DATA SHEET v ...
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... Table 13-10. IDSEL Timing in a Configuration Cycle Symbol t IDSEL setup to PCI_CLK 1 t IDSEL hold from PCI_CLK 2 PCI_CLK IDSEL FRAME# HI-Z AD[7:0] HI-Z C/BE[3:0]# HI-Z = high impedance Figure 13-3. IDSEL Timing in a Configuration Cycle (PCI 88 ELECTRICAL SPECIFICATIONS Parameter Select Config. Address Config. Byte Enable Read PRELIMINARY DATA SHEET v.2.0 ...
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... CL-PD6729 PCI-to-PCMCIA Host Adapter Table 13-11. PAR Timing Symbol t PAR setup to PCI_CLK (input to CL-PD6729 PAR hold from PCI_CLK (input to CL-PD6729 PAR valid delay from PCI_CLK (output from CL-PD6729 PAR hold from PCI_CLK (output from CL-PD6729) 4 PCI_CLK FRAME# HI-Z AD[31:0] HI-Z C/BE[3:0]# HI-Z PAR HI-Z = high impedance PAR goes high or low depending on AD[31:0] and C/BE[3:0]# values ...
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... PCI-to-PCMCIA Host Adapter 13.3.2 System Interrupt Timing Table 13-12. Pulse Mode Interrupt Timing Symbol t IRQ[XX] low or high 1 HI-Z IRQ[XX] HI-Z = high impedance NOTE: Each time indicated is 4 PCI clocks or 4 external clocks. Figure 13-5. Pulse Mode Interrupt Timing January 1997 PRELIMINARY DATA SHEET v.2.0 Parameter ...
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... Tcp is two times the period of the PCI bus clock connected to the CL-PD6729 PCI_CLK pin. If PCI_CLK operates at 33 MHz, then: The timing diagrams that follow were derived for a CL-PD6729 using the PCI clock at 33 MHz. The exam- ples are for the default values of the Timing registers for Timer Set 0, as follows: ...
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... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 00h, the hold (Recovery) time would -REG, -CE[2:1], A[25:0] -OE, -WE -WAIT D[15:0] Write Cycle D[15:0] Read Cycle January 1997 PRELIMINARY DATA SHEET v.2.0 Parameter 2 3 pres t 1 ...
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... Timer Set 0 default value of 00h, the hold (Recovery) time would For typical active timing programmed at 340 ns, maximum -WAIT timing is 200 ns after Command active. 5 -IOIS16 must go low within 3Tcp + the cycle beginning or -IOIS16 will be ignored and -CE will not be activated. 94 ELECTRICAL SPECIFICATIONS Parameter ...
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... CL-PD6729 PCI-to-PCMCIA Host Adapter -REG, A[25:0] -IOWR, -IORD -WAIT t -IOIS16 -CE1 -CE2 D[15:0] Write Cycle D[15:0] Read Cycle Figure 13-7. Word I/O Read/Write Timing January 1997 PRELIMINARY DATA SHEET v.2 ref ELECTRICAL SPECIFICATIONS 95 ...
Page 95
... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 00h, the hold (Recovery) time would -REG, A[25:0] -IOWR, -IORD, -OE, -WE -CE1 D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Figure 13-8. PCMCIA Read/Write Timing when System is 8 Bit 96 ELECTRICAL SPECIFICATIONS Parameter pres ...
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... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 00h, the hold (Recovery) time would -REG, A[25:0] t -IOWR, -IORD, -OE, -WE -CE1 -CE2 D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle January 1997 PRELIMINARY DATA SHEET v.2.0 Parameter pres Odd/Even Data Odd/Even Data XX . ...
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... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 00h, the hold (Recovery) time would -IOIS16 level from card must be valid within 3 clocks of an address change to the card. 98 ELECTRICAL SPECIFICATIONS ...
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... CL-PD6729 PCI-to-PCMCIA Host Adapter -REG, A[25:0] t -IOIS16 -CE2 -CE1 -IOWR, -IORD D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Figure 13-10. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing January 1997 PRELIMINARY DATA SHEET v.2 Odd Data Odd Data ...
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... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 100 PACKAGE DIMENSIONS 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 0.13 (0.005) 0.28 (0.011) CL-PD6729 208-Pin PQFP Pin 1 Indicator 25.50 (1.004) REF 3.17 (0.125) 0.40 (0.016) 3.67 (0.144) 0.75 (0.030) PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter 27.90 (1.098) 28.10 (1.106) 25.50 (1.004) REF 1.30 (0.051) REF 0 MIN 7 MAX 0.25 (0.010) MIN January 1997 . ...
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... Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. January 1997 PRELIMINARY DATA SHEET v.2.0 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) CL-PD6729 208-Pin VQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) . 27.80 (1.094) 28.20 (1.110) 1 ...
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... ORDERING INFORMATION The order number for the part is: CL – PD6729 – QC – E Cirrus Logic, Inc. Product Line: Portable Products Part Number † Contact Cirrus Logic for up-to-date information on revisions. 102 ORDERING INFORMATION PCI-to-PCMCIA Host Adapter † Revision Temperature Range: ...
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... DEVSEL# DEVSEL# Timing bits E End Address 15-8 bits End Address 19-12 bits End Address 23-20 bits End Address 7-0 bits EXT_CLK Extended Data register Extended Index bits Extended Index register Extension Control 1 register Extension registers 53 External Clock Enable bit ...
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... Operation registers ordering information package 9 PAR Parity Error Check/Report Enable bit PCI bus interface pins PCI I/O Space Enable bit PCI Memory Space Enable bit 9 PCI_CLK PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter 66, 67 ...
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... Recovery Multiplier Value bits 76 Recovery Prescalar Select bits 76 Recovery Timing 0-1 registers 11 -REG 58 REG Setting bit 33 Register Index bits 12 RESET 100 revision 38 Revision bits Revision ID and Class Code register 29 Revision ID bits 13 -RI 9 RI_OUT* 44 Ring Indicate Enable bit 15 RING_GND 9 RST SERR# 74 Setup Multiplier Value bits ...
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... VPP_VCC Power bits PP 13 VS1/GPSTB1 13 VS2/GPSTB2 106 INDEX W 12 -WAIT Wait Cycle Enable bit waveform. See timing 11 -WE Window Data Size bit 26 windowing WP/-IOIS16 write FIFO Write Protect bit Z Zoomed Video Port PRELIMINARY DATA SHEET v.2.0 CL-PD6729 PCI-to-PCMCIA Host Adapter ...
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... CL-PD6729 PCI-to-PCMCIA Host Adapter January 1997 PRELIMINARY DATA SHEET v.2.0 Notes . 107 INDEX ...
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... FAX: 852/2375-1202 TEL: 886/2-718-4533 FAX: 886/2-718-4526 ITALY Milan UNITED KINGDOM TEL: 39/2-3360-5458 London, England FAX: 39/2-3360-5426 TEL: 44/1727-872424 FAX: 44/1727-875919 Copyright 1997 Cirrus Logic Inc. All rights reserved. Publications Ordering: 800/359-6414 (USA) or 510/249-4200 World Wide Web: http://www.cirrus.com CL-PD6729 346729-002 ...