AMD-8111AC Advanced Micro Devices, AMD-8111AC Datasheet
AMD-8111AC
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AMD-8111AC Summary of contents
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... The AMD-8000™ series of chipset components is a highly integrated system logic solution that delivers enhanced performance and features for the AMD Athlon 64 and AMD Opteron processors. The AMD-8111™ HyperTransport™ I/O hub includes the following features: • ...
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... AMD-8111™ HyperTransport™ I/O Hub Data Sheet • Legacy AT-Compatible Logic – Programmable interrupt controller – Programmable interval timer – DMA controller (LPC bus) – Legacy ports • IOAPIC controller • Real-time Clock – Includes 256 bytes of CMOS, battery-powered RAM, and ACPI-compliant extensions ...
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... AMD’s products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body other applications intended to support or sustain life any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or environmental damage may occur. AMD reserves the right to discontinue or make changes to its products at any time without notice. © ...
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Table of Contents Chapter 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Enhanced IDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Network Port Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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System Management I/O Mapped Registers (PMxx .220 4.8 AC ‘97 Controller Registers . . . . . . . ...
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List of Figures Figure 1. System Block Diagram .....................................................................................................2 Figure 2. Interrupt Sources.............................................................................................................41 Figure 3. Vectored Interrupt Routing .............................................................................................42 Figure 4. High Precision Event Timer Block Diagram ..................................................................47 Figure 5. High Precision Event Timer Interrupt Routing...............................................................49 Figure 6. SMBus Controller ...
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List of Tables Table 1. I/O Cell Types .................................................................................................................19 Table 2. Host HyperTransport™ Technology Pin Descriptions ...................................................20 Table 3. Secondary PCI Interface Pin Descriptions......................................................................21 Table 4. LPC Bus and Legacy Support Pin Descriptions .............................................................22 Table 5. Ultra DMA Enhanced IDE ...
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Table 42. PCI Configuration Spaces .............................................................................................136 Table 43. PCI Configuration Spaces .............................................................................................136 Table 44. Fixed Address Spaces ...................................................................................................137 Table 45. Relocatable Address Spaces..........................................................................................138 Table 46. Register Behavior Types (Read, Write, Etc.)................................................................138 Table 47. Registers Affected by DevB:0x41[SHEN] ...................................................................153 Table 48. ...
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Table 86. NAND Tree 3: Output NC24 ........................................................................................372 Table 87. NAND Tree 4: Output DCSTOP_L..............................................................................372 Table 88. NAND Tree 5: Output DIOWP_L ................................................................................373 Table 89. NAND Tree 6: Output GNT_L[3] ................................................................................373 ...
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... Chapter 1 Ordering Information The Ordering Part Number (OPN) is formed by a combination of the elements shown below. Contact your AMD representative for detailed ordering information. AMD-8111 A C Case Temperature C = Commercial Temperature range Package Type A = 492-pin Plastic Ball Grid Array Family/Core AMD-8111™ I/O Hub ...
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Chapter 2 Signal Descriptions 2.1 Terminology See Section 4.1.2 on page 136 for a description of the register naming conventions used in this document. See Section 3.7.1.6 on page 57 for a description of the system power states: MOFF, SOFF, ...
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Host HyperTransport™ Technology Interface Table 2. Host HyperTransport™ Technology Pin Descriptions Pin Name and Description LDTCOMP[3:0]. HyperTransport™ compensation pins. These should be connected as follows: Bit Function External Connection [0] Positive RX compensation 50 ohms 10% to VDD_LDT [1] ...
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Table 2. Host HyperTransport™ Technology Pin Descriptions (Continued) LRXCTL_H/L. HyperTransport receive link control signal. LTXCAD_H/L[7:0]. HyperTransport transmit link command- address-data bus. LTXCLK_H/L. HyperTransport transmit link clock. LTXCTL_H/L. HyperTransport transmit link control signal. Note: 2.3 Secondary PCI Interface Table 3. Secondary ...
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Table 3. Secondary PCI Interface Pin Descriptions (Continued) Pin Name and Description PIRQ[ D]_L. PCI interrupt requests. PREQ_L. Priority PCI master request. PREQ_L/PGNT_L have no functional differences from REQ_L[6:0]/GNT_L[6:0]. REQ_L[6:0]. PCI master request signals. SERR_L. PCI system error ...
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Ultra DMA Enhanced IDE Interface Table 5. Ultra DMA Enhanced IDE Pin Descriptions Pin Name and Description DADDR[P,S][2:0]. IDE controller [primary, secondary] port address. DCS1P_L. IDE controller primary port chip select 1. This is active during accesses to the ...
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Table 6. System Management Pin Descriptions Pin Name and Description ACAV. AC available input. This may be used to detect changes to the state of system AC power. It controls PM20[ACAV_STS]. This pin may be configured as GPIO0 by PMC0. ...
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Table 6. System Management Pin Descriptions (Continued) Pin Name and Description FANCON[1:0]. Fan control outputs. These may be used to control system fans. The frequency and duty cycle are specified by PMF8. FANCON1 may be configured as GPIO9 by PMC9. ...
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Table 6. System Management Pin Descriptions (Continued) Pin Name and Description LID. Lid change-state detect input. This may be used to detect state changes in notebook shell lids. The logic for this pin includes a debounce circuit. When the signal ...
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Table 6. System Management Pin Descriptions (Continued) Pin Name and Description PWROK. Power OK. This is required to be Low while the main power planes are not valid, stay Low for at least 50 milliseconds after they become valid, and ...
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Table 6. System Management Pin Descriptions (Continued) Pin Name and Description SLPBTN_L. Sleep button input. This may be used to control the automatic transition from a sleep state to FON. It controls PM00[SLPBTN_STS]. Also asserted for four ...
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Table 6. System Management Pin Descriptions (Continued) Pin Name and Description SUSPEND_L. This may be used to gate RESET_L during Suspend to RAM (S3 enable power reduction during Power on Suspend (S1 controlled by DevB:3x50[SUSP]. This ...
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Table 7. USB Pin Descriptions (Continued) USBOC0_L. USB over current detect 0. This goes to the USB logic to report the occurrence of an over-current condition on the voltage supplied to the USB ports. USBOC1_L. USB over current detect 1. ...
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MII Interface Table 9. MII Interface Pin Descriptions Pin Name and Description MII_TX_CLK. MII Transmit Clock. MII_TX_CLK is a continuous clock input that provides the timing reference for the transfer of the MII_TX_EN and MII_TXD[3:0] signals. MII_TX_CLK must provide ...
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Table 9. MII Interface Pin Descriptions (Continued) Pin Name and Description MII_RXD[3:0]. MII Receive Data. MII_RXD[3:0] is the nibble-wide MII receive data bus. Data on MII_RXD[3:0] is sampled on every rising edge of MII_RX_CLK while MII_RX_DV is asserted. MII_RXD[3:0] is ...
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Table 9. MII Interface Pin Descriptions (Continued) Pin Name and Description MII_PHY_RST. MII PHY Reset. MII_PHY_RST is an output pin that is used to reset the external PHY. The output polarity is determined by ENC054[PHY_RST_POL]. MII_MDC. MII Management Data Clock. ...
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Miscellaneous Table 11. Miscellaneous Pin Descriptions Pin Name and Description NC[32:0]. Must be left unconnected. STRAPH[3:0]. Must be tied High. STRAPL[3:0]. Must be tied Low. 2.12 Power and Ground See Section 3.7.1.6 on page 57 for a description of ...
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VDD_IOAL and VDD_COREAL. VDD_IOAL is a 3.3-V plane and VDD_COREAL is a 1.8-V plane. Both power planes are part of the internal AL (always) power plane supplied by AUX when that plane is valid or by VDD_RTC when ...
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Chapter 3 Functional Operation 3.1 Overview 3.1.1 Resets The IC generates an internal reset for the AUX power planes called RST_SOFT. RST_SOFT lasts for about 30 milliseconds after the AUX planes become valid. PWROK is the source of reset for ...
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Table 12. Error Handling (Continued) Error Type Status Bit Received target abort on DevA:0x1C[RTA] secondary bus while executing a downstream posted command Received master abort DevA:0x1C[RMA] on secondary bus Received master abort DevA:0x1C[RMA] on secondary bus while executing a downstream ...
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Table 12. Error Handling (Continued) Error Type Status Bit LPC protocol error DevB:0x40[LPCERR], PORT61[IOCHK] Received posted write DevB:0x40[PW2LPC] targeting LPC while LPC bus master is active 2. PERR_L is only asserted enabled by DevA:0x3C[PEREN both ...
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Table 14. HyperTransport™ Protocol Unit IDs Unit Unit ID First BUID Second BUID + 1 Third BUID + 2 Fourth BUID + 3 3.3 Secondary PCI Bridge The secondary PCI bridge interfaces to the internal USB and Ethernet controllers and ...
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NMI, INIT, SMI IRQ Pins, TCO, Interrupt PNPIRQ[2:0], Routing IRQ8, IRQ13, Equation Serial IRQ, SCI PIRQ[A,B,C,D]_L GPIO[31:28] Figure 2. Interrupt Sources The following table specifies how interrupts are routed based on the configuration bit. Table 15. Interrupt Routing Configuration APIC-EN ...
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LANC_INT, SMBC_INT, USB0_INT, USB1_INT, EHC_INT, AC97_INT, GPIO[31:28], NMP_INT, NMS_INT PIRQ[A,B,C,D]_L PNPIRQ[2:0] SCI_IRQ IRQx pins, devices Serial IRQs Figure 3. Vectored Interrupt Routing Several internal interrupts are shared with the PCI interrupts pins. These internal interrupt signals drive the PIRQ[A,B,C,D]_L pins ...
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PNP_IRQx = PNPIRQ2 & (DevB:3x44[11:8] == 4'hx) | PNPIRQ1 & (DevB:3x44[7:4] == 4'hx) | PNPIRQ0 & (DevB:3x44[3:0] == 4'hx); SCI_IRQx = SCI_IRQ & (DevB:3x42[3:0] == 4'hx); ISA_IRQx = ~(IRQx & SERIRQx ) & ~( (DevB:3x56[3:0] | (DevB:3x56[15:12] == 4'hx) | ...
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PNPIRQ[2:0] PNP IRQ pins (with the polarity specified by the associated GPIO control register). SCI_IRQ Active-High SCI interrupt. IRQx External interrupt. PIC_IRQx The interrupt signals that go to the PIC. Notes from the interrupt routing equations: 3.4.2.2 PIC/SMI/NMI/INIT to HyperTransport™ ...
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PIC. The interrupt vector is in the 8 LSBs of the response and the 24 MSBs are zero. The PIC clears the INTR line for a minimum of one PCLK when the interrupt acknowledge is ...
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Watchdog Timer (WDT) The watchdog timer is a down counter starting at a programmed value. It resets or shuts down the system if the count reaches zero. Operating system services periodically restart the timer so that if the operating ...
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MHz 32 Bit Up Counter (roll over Accu Figure 4. High Precision Event Timer Block Diagram 3.4.4.1.1 Periodic Mode Only Timer 0 supports the periodic mode. In the periodic mode the comparator consists of a comparator ...
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Non-Periodic Mode All timers support the non-periodic (one-shot) mode. The timer generates an interrupt if either the comparator value matches the main counter value or the main counter wraps around. During runtime the hardware does not change the value ...
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PIT t0irq lien t0irq t2irq t2introute[4:0] t1introute[4:0] t0introute[4:0] HPET Note: High Precision Event Timers can be routed only to INTINx inputs 10, 11, 12, 14, 15, 16, 17, 18 and 19 ...
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Real-Time Clock (Logic Powered by VDD_COREAL) The real-time clock logic requires an external 32-kHz oscillator. It includes a clock and calendar timer, an alarm which generates an interrupt, and 256 bytes of non-volatile RAM register compatible with ...
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ACPI 2.0 specification. SC04[SCI_EVT] comprises three sources of events with each source having an unique notification header associated with it (see Table 18). If there are more than one with SC04[SCI_EVT] associated event pending, the notification header with the highest ...
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SMBALERT SC08[SMBALERT_EN] 1 SMB01[xxx] DONE ALARM STATUS SCI_EVT SCI_EVT=1 IBF IBF=0 OBF OBF=1 SC04[xxx] Notification Header, sticky Event Generator (set pulse) Status Bit, sticky, R/Clr Status Bit, non-sticky, RO Enable Bit, R/W Figure 6. SMBus Controller Interrupt Model Note ...
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System Management Logic System management includes logic for most of the multiplexed-function pins—such as general- purpose I/O (GPIO) pins, the power management (PM) pins, system management bus 1.0 (SMBus 1.0) pins, the processor interface pins, and the plug and ...
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Table 19. System Management Events (Continued) Events USB bus resume event AC ‘97 events SMBus 2.0 events Power button override TCO events Miscellaneous SMI events PIC INTR signal (unmasked IRQs) Real-time clock IRQ NMI to processor INIT to processor SMI ...
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STS register Device Monitors EN register PM[8C:40] SMI_EN register STS register SMBus EN register Events STS register PM20 Events EN register SMI_EN register STS register GPIO pins EN register PM[DF:C0] SMI_EN register STS register PM00 Events EN register Figure 7. ...
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Address Decode Interrupt OR Select DMA Request Select Figure 8. Device Monitors and Retrigger Timers 3.7.1.2.1 Traps Configuration registers DevB:3x[D8:B4] specify several traps for memory, I/O, and configuration space address ranges. These traps are generated for the specified transactions that ...
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PCISTOP_L Assertion The PCLK input to the IC is required to always operate regardless of the CLKRUN_L protocol. The PCI clock to external devices is stopped when the IC asserts PCISTOP_L. If the PCI bus has been idle for ...
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Table 20. System Power States System Power State Full on (FON; S0 Power on suspend (POS; S1) Suspend to RAM (STR; S3) Soft off (SOFF; S5); suspend to disk (STD; S4) Mechanical off (MOFF; G3) Mechanical off (MOFF ...
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Resume event STR(S3) suspend to RAM CPU initiated (PM04) PWRON_L High RPWRON High Resume event SOFF(S5)/STD(S4) soft off/suspend to disk CPU initiated (PM04) PWRON_L High RPWRON Low VDD_AUX power applied, DevB:3x43[G3TOS5]=1, and DevB:3x43[VDDA_STS MOFF(G3) mechanical off VDD_AUX power ...
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Table 21. Resume Events (Continued) Resume Event EXTSMI_L SMBus 2.0 events SMBALERT1_L AC ‘97 events GPIO[25, 24, 23, 22, 18, 14 THERM_L TCO SCI System inactivity timer Device monitor events Device monitor events GPIO[31:26, 21:19, 17:15, ...
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RESET_L. LDTRST_L DCSTOP_L SUSPEND_L AGPSTOP_L LDTSTOP_L PWRON_L RPWRON PWROK Resume event VDD_IO, VDD_CORE RST_SOFT VDD_IOX, VDD_COREX MOFF to SOFF Figure 10. Transitions from MOFF to SOFF and from SOFF/STD/STR to FON See RTC more ...
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STPCLK Message Stop Grant Message AGPSTOP_L DCSTOP_L SUSPEND_L LDTSTOP_L RESET_L, LDTRST_L PWRON_L RPWRON PWROK VDD_IO, VDD_CORE Figure 11. Transitions from FON to SOFF/STD/STR 3.7.1.6.3 Transitions From any state to G3 (MOFF) Transitions from any state to G3 (MOFF) occur whenever ...
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AGPSTOP_L. CPUSLEEP_L. LDTSTOP_L. 3.7.1.6.5 Transitions From (FON) When the IC detects an enabled resume event, it issues a HyperTransport STPCLK system management message with the STPCLK bit deasserted. 3.7.1.6.6 Transitions From (FON) The following ...
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Stop-grant. CPUSLEEP_L and CPUSTOP_L AGPSTOP_L. DCSTOP_L. SUSPEND_L. PCISTOP_L. LDTSTOP_L. 3.7.1.6.8 Transitions From S1 (POS (FON) The following is the S1 resume sequence, once an enabled resume event occurs: PCISTOP_L, CPUSLEEP_L, CPUSTOP_L. LDTSTOP_L. DCSTOP_L, SUSPEND_L. AGPSTOP_L. ...
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Serial IRQ Protocol The IC supports the serial IRQ protocol. This logic controls the SERIRQ pin and outputs IRQs to the PIC and IOAPIC blocks. This logic runs off of PCLK specified by DevB:3x4A. The serial IRQ ...
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SMBALERT. The host controller includes support for the SMBALERT_L signal. If this signal is asserted, then it is expected that software determines the source by generating a host read cycle to the alert response address, 0001100b. If the SMBus host ...
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LTCH_STS LATCH To interrupt generator or alternative logic FF GPIO output clocks 0 and 1 Figure 12. GPIO Pin Format Debounce. The input signal must be active and stable for before the output signal will be ...
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PCM Audio In, 2-, 4-, 6-channel stereo for PCM Audio Out • 16 bit sample resolution • Multiple sampling rates • two codecs An AC '97 sub-system includes a digital controller and a set ...
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See the AC '97 specification for further information. 3.8.2 AC ‘97 Serial Link Interface The AC ‘97 serial link interface is designed '97 revision 2.2 compliant. For a detailed description of the AC-link interface see the AC ...
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When accessing the codec registers, only one I/O cycle can be pending across the AC-link at any time. The IC internal architecture and AC ‘97 controller implementation provides arbitration logic to ensure that. For compatibility reasons the CAS bit in ...
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Table 23. PCI Interrupt Sources (Continued) Interrupt Register Bit AC30/MC40[SRINT] AC2C/MC3C[SRIEN] AC30/MC40[PRINT] AC2C/MC3C[PRIEN] AC30/MC40[GPIINT] AC2C/MC3C[GPIIEN] The principal function of scatter/gather (i.e., basically a memory paging mechanism assist the host operating system in managing memory fragmentation. One logical buffer ...
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AC '97 Data Buffering Data buffering inside the digital controller is provided with FIFO buffers. The following buffers are provided as separate, independent buffers: • Audio PCM left out • Audio PCM right out • Audio PCM center front ...
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The sample pairs Left-Front/Right-Front, Center-Front/Subwoofer and Left-Rear/Right-Rear can be swapped by programming DevB:5x4C. Each FIFO has the following characteristics: • Contains eight 16 bit samples. Either one 16 bit word (i.e., one sample at a ...
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Output slots which are not in use for a given configuration are always stuffed with zeros by the IC. Slot Number 0 1 Frame n CMD CMD TAG ADDR DATA Frame n+1 CMD CMD TAG ADDR DATA Frame n+2 CMD ...
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A transition from Low to High at ACSDI0 or ACSDI1 causes the AC ‘97 controller to sequence through a wake-up event detection and to finally report this wake-up event in PM20[AC97_STS], AC2C/MC3C[PRINT] or AC2C/MC3C[SRINT], respectively, depending on the AC ‘97 ...
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USB Controller The USB 2.0 host controller is designed to comply with the EHCI (Enhanced Host Controller Interface) specification. It consists of three main components (see Figure 16): The Enhanced Host Controller (EHC): This block handles the USB 2.0 ...
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LAN Ethernet Controller 3.10.1 Interfaces 3.10.1.1 Software Interface The software interface to the network controller is divided into three parts. One part is the PCI configuration registers used to identify the network controller and to setup the configuration of ...
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Before any network frames can be sent or received, the unique 48-bit IEEE MAC address must be written to the Physical Address Register (PADR). Normally this is done by a chipset initialization routine that runs before the network device driver ...
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After the transmitter is suspended, the TX_SUSPENDED bit in STAT0 is set and SPNDINT interrupt bit in INT0 is set. Setting the TX_SPND bit in CMD0 suspends the transmitter in the same way as TX_FAST_SPND, ...
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The manner in which this scheme relates to standards such as IEEE 802 described elsewhere in this document. This section simply describes the implementation of the descriptor rings themselves. Each descriptor describes a single buffer. ...
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BADR0 RCV_RING0_LEN BADR0 + 16 * RCV_RING0_LEN BADX0 XMT_RING0_LEN BADX0 + 16 * XMT_RING0_LEN Figure 17. Receive and Transmit Descriptor Rings 3.10.2.5 Polling Polling is the action that the Descriptor Management Unit (DMU) takes when it reads a descriptor to ...
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DMU finds that the OWN bit of the next descriptor in the internal descriptor cache must access the host system memory again to read in another block of descriptors. 3.10.2.6 Transmit Polling After the host CPU has ...
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Whenever the DMA controller finishes copying a transmit frame from system memory, it sets the TINTx bit of INT0 that corresponds to the descriptor ring number to indicate that the buffers are no longer needed. This causes an interrupt signal ...
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FFFFh which corresponds to 0.671 seconds. A write to STVAL restarts the timer with the new contents of STVAL. 3.10.4 Media Access Control The Media Access Control (MAC) engine incorporates the essential protocol requirements for operation of an Ethernet/IEEE 802.3-compliant ...
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Framing The MAC engine autonomously handles the construction of the transmit frame. Once the transmit FIFO has been filled to the predetermined threshold and access to the channel is currently permitted, the MAC engine commences the 7-byte preamble sequence ...
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The MAC engine can be programmed to try to transmit the same frame again after a FIFO underflow. The transmitter backoff logic can also be programmed to treat late collisions just like normal collisions. The status of each receive message ...
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The MAC engine allows the user to program both the IPG and the first part deferral (IFS1) through the IFS and IFS1 registers. The user can change the IPG value from its default of 96-bit times to compensate for delays ...
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XmtOneCollision counter is incremented. If more than one retry was required, the XmtMultipleCollision counter is incremented. If all 16 attempts experienced collisions, the XmtExcessiveCollision counter is incremented. After an excessive collision error, the transmit message is flushed from the FIFO. ...
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Transmit Start Point (XMTSP) in CTRL1 sets the point when the transmitter actually attempts to transmit a frame onto the media. A minimum of XMTSP bytes must be written to the transmit FIFO for the current frame before transmission of ...
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Preamble SFD Destination 1010....1010 10101011 56 8 Bits Bits Figure 18. ISO 8802-3 (IEEE/ANSI 802.3) Data Frame The 544 bit count is derived from the following: At the point that FCS appended, the transmitted frame should contain: ...
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Late collision errors can only occur when the device is operating in half-duplex mode. Loss of carrier and transmit FIFO underflow errors are possible when the device is operating in half- or full-duplex mode. When a late collision or underflow ...
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Conduit Mode The Conduit Mode of operation allows the LAN Ethernet controller to pass frame data to an external MAC-type device attached to the MII bus. This option eliminates the need for a frame buffer in the external device. ...
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TX_EN TXD[3:0] frame1 CRS COL Figure 19. Conduit Mode Transmission with One Collision TX_EN TXD[3:0] frame1 CRS COL Figure 20. Conduit Mode Excessive Collisions Error 3.10.6 Receive Operation The receive operation and features of the network controller are controlled by ...
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For test purposes, the controller can be programmed to accept runt packets of 12 bytes or larger by setting RPA in CMD2. 3.10.6.2 Address Matching MAC addresses are classified as either unicast, multicast, or broadcast. The least significant bit of ...
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The Logical Address Filter block consists of a 64-bit Logical Address Filter Table and associated control logic. The Logical Address Filter logic uses the CRC generator from the Frame Check Sequence block to perform a calculation on the DA field ...
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Received Message Destination Address Match = 1 Packet Accepted Match = 0 Packet Rejected Figure 21. Address Match Logic 3.10.6.3 Automatic Pad Stripping During reception of an IEEE 802.3 frame, the pad field can be stripped ...
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Bits Bits Preamble SFD 1010....1010 10101011 Start of Frame at Time = 0 Increasing Time Figure 22. IEEE 802.3 Frame and Length Field Transmission Order Since any valid Ethernet Type field value is greater than a valid IEEE ...
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These error conditions are reported in the corresponding receive descriptors. The RcvFCSErrors, RcvAlignmentErrors, or RcvMissPkts counter is also incremented when one of these events occurs. 3.10.7 Statistics Counters In order to provide network management information with minimum host CPU overhead, ...
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In Table 27 on page 99, the Address column gives the value that the host CPU must write to the MIB_ADDR register in order to read the counter. Table 27. Receive Statistics Counters Addres Receive Counter Name s (hex) 00 ...
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Table 27. Receive Statistics Counters (Continued) Addres Receive Counter Name s (hex) 06 RcvFragments 07 RcvJabbers 08 RcvUnicastPkts 09 RcvAlignmentErrors 0a RcvFCSErrors 0b RcvGoodOctets 0c RcvMACCtrl 0d RcvFlowCtrl 0e RcvPkts64Octets MIB Object Supported RMON etherStatsFragments RMON etherHistoryFragments RMON etherStatsJabbers RMON ...
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Table 27. Receive Statistics Counters (Continued) Addres Receive Counter Name s (hex) 0f RcvPkts65to127Octets 10 RcvPkts128to255Octets RMON 11 RcvPkts256to511Octets RMON 12 RcvPkts512to1023Octets RMON 13 RcvPkts1024to1518Octe ts 14 RcvUnsupportedOpcode s 15 RcvSymbolErrors 16 RcvDropPktsRing0 17-19 Reserved 1a RcvJumboPkts 1b-1f Reserved MIB ...
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Transmit Statistics Counters Table 28 on page 102 describes the statistics counters associated with the transmitter and lists the MIB objects that these counters support. The Address column gives the value that the host CPU must write to the ...
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Table 28. Transmit Statistics Counters (Continued) Addres Transmit Counter s (hex) Name 26 XmtUnicastPkts 27 XmtOneCollision 28 XmtMultipleCollision 29 XmtDeferredTransmit 2a XmtLateCollision 2b XmtExcessiveDefer 2c XmtLossCarrier 2d XmtExcessiveCollision E-like dot3StatsExcessiveCollisions The number of packets that are not 2e XmtBackPressure 2f ...
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Table 28. Transmit Statistics Counters (Continued) Addres Transmit Counter s (hex) Name 31 XmtPkts65to127Octets RMON 32 XmtPkts128to255Octet s 33 XmtPkts256to511Octet s 34 XmtPkts512to1023Octe ts 35 XmtPkts1024to1518 Octets 36 XmtOversizePkts 37 XmtJumboPkts 3.10.8 VLAN Support Virtual Bridged Local Area Network (VLAN) ...
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OCTETS PREAMBLE 1 OCTET DESTINATION ADDRESS 6 OCTETS SOURCE ADDRESS 6 OCTETS LENGTH/TYPE = 8100h 2 OCTETS TAG CONTROL INFORMATION 2 OCTETS MAC CLIENT LENGTH/TYPE 2 OCTETS 42-1500 OCTETS MAC CLIENT DATA FRAME CHECK SEQUENCE 4 OCTETS Figure 23. ...
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TCI field of a VLAN tag. This feature allows VLAN software to control the VLAN tag of a frame without modifying data in transmit buffers. The receiver can determine whether a frame is untagged, priority-tagged, or ...
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Alternatively, in external loopback mode, data can be transmitted to and received from the external network. All transmit and receive function programming, such as automatic transmit padding and receive pad stripping, operates the same way in loopback as it ...
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TX_ER is not driven by the network controller and therefore not looped back. Internal loopback should not be used on a live network because transmit data path signals might interfere with network traffic. The PHY should be disconnected from ...
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PHY and is synchronous with the rising edge of TX_CLK. The transmit process starts when the network controller asserts TX_EN, which indicates to the external PHY that the data on TXD(3:0) is valid. IEEE ...
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MII Network Status Interface The MII also provides the CRS (Carrier Sense) and COL (Collision Sense) signals that are required for IEEE 802.3 operation. Carrier Sense is used to detect non-idle activity on the network for the purpose of ...
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OP ST Preamble 10 Rd 1111....1111 Bits Bits Bits Figure 26. Frame Format at the MII Interface Connection The preamble (if present) is followed by a start field (ST) and an operation field (OP). ...
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Host CPU Access to External PHY The host CPU can indirectly read and write external PHY registers through the PHY Access Register. To write to a PHY register the host CPU puts the register data into the PHY_DATA field ...
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The automatic polling of PHY registers is controlled by six 16-bit Auto-Poll registers, AUTOPOLL0 to AUTOPOLL5 shown in Figure 27. By writing to the Auto-Poll registers, the user can independently define the PHY addresses and register numbers for six external ...
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AP_VALUE Register ADR Figure 28. Indirect Access to Auto-Poll Data Registers Auto-Poll Register 0 differs from the other Auto-Poll Registers in several ways. The PHY address (AP_PHY0_ADDR) field of this register defines the default PHY address that is used by ...
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The Auto-Poll’s frequency of generating MII management frames can be adjusted by setting of the APDW bits (CTRL2, bits 2-0). 3.10.12 Network Port Manager The network controller does not require software intervention to control and configure an external PHY attached ...
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To control the auto-negotiation process, the Network Port Manager generates MII Management Frames to execute the procedure described below. The Network Port Manager is held in the IDLE state while H_RESET is asserted and while the EN_PMGR bit is cleared. ...
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Table 32. Sources of Auto-negotiation Advertisement Register (R4) Bits 4.13 Remote Fault 4.12 Reserved 4.11 ASM_DIR 4.10 PAUSE 4.9 100BASE-T4 4.8 100BASE-TX, Full Duplex 4.7 100BASE-TX 4.6 10BASE-T, Full Duplex 4.5 10BASE-T 4.4:0 Selector Field Note: The notation Rx.y stands ...
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Operation Without MII Management Interface The Port Manager normally sets up the speed, duplex mode, and flow control (pause) ability of the MAC based on the results of auto-negotiation. However possible to operate the device with no ...
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MAC Control Pause Frames The format of a MAC Control Pause frame is shown in Table 33. Table 33. MAC Control Pause Frame Format Octet Numbers Field Name 1-6 Destination Address 7-12 Source Address 13-14 Length/Type 15-16 MAC Control ...
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Enabling Traffic Regulation MAC Control Pause frame generation or half-duplex back pressure assertion is controlled by the host CPU when it sets or clears the Flow Control Command (FCCMD) bit. When the FCCMD bit is set, the receiver is ...
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PAUSE_LEN field of the Flow Control register. If FIXP is 0, the contents of the request_operand field are set to 0FFFFh. In full-duplex mode, if FIXP is 0, the act of clearing ...
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PAUSE frames asymmetric configuration only one link partner transmits PAUSE frames and the other one receives them. During the auto-negotiation process each link partner indicates its configuration preference in the form of PAUSE and ASM_DIR bits that are ...
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Received MAC Control PAUSE frames are handled completely by the hardware. They are not passed on to the host computer. However, MAC Control frames with opcodes not equal to 0001h are treated as normal frames, except that their reception causes ...
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Delay Time field are loaded into an internal interrupt event timer, and the interrupt event timer is disabled. Each time a receive or transmit interrupt event that is included in that group occurs, the interrupt event counter is decremented by ...
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The type of wake-up is configured by software using the bits LCMODE_SW, PMAT_MODE, and MPEN_SW in the CMD7 register. These bits are only reset by the power-on reset (POR) so that they maintain their values across PCI bus resets. 3.10.16.2 ...
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The RUN or suspend bits must not be reset while Pattern Match mode is enabled. The controller can be programmed to save the wake-up frame so that the software can respond to the frame that caused the CPU to wake ...
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The first two 40-bit words in the PMR serve as pointers and contain enable bits for the eight possible match patterns. The format of the first two words is shown in Table 36 on page 127. Table 36. Format of ...
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... The contents of the PMR are not affected by any reset. The contents are undefined after a power-up reset (POR). Future AMD Ethernet controllers may contain two Pattern Match RAMs, one for patterns 0-3 and one for patterns 4-7. To anticipate compatibility with these controllers recommended that the software follow these rules ...
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... Data Byte 2 Figure 29. Pattern Match RAM 3.10.16.3.3 Sample PMR Patterns The Microsoft® and AMD Device Class Power Management Reference Specification for the Network Device Class describes five sample wake-up patterns. The first three of these are shown below. ARP to machine address 157.55.199.72: Table 38 ...
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Directed IP packet (note that this excludes any other directed packets to our MAC address): Table 39. Directed IP Packet Example Offset Pattern (decimal) (hex) 0 08003e304770 12 0800 30 9d37c748 NBT Name Query/Registration for computer name <00>, <03>, <20>: ...
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Table 41. PMR Programming Example ...
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H_RESET Hardware Reset (H_RESET) occurs when the RESET_L signal is asserted. When the minimum pulse width timing as specified in the RESET_L signal description has been satisfied, an internal reset operation is performed. H_RESET programs most of the internal ...
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Chapter 4 Registers 4.1 Register Overview The IC includes several sets of registers accessed through a variety of address spaces. I/O address space refers to register addresses that are accessed by x86 I/O instructions such as IN and OUT. PCI ...
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LPC Bridge System Management DevB:0xXX DevB:3xXX Device Header Function 3 Second Device AC ‘97 Audio Function 0 DevB:5xXX IDE Controller Function 5 DevB:1xXX AC ‘97 Modem Function 1 DevB:6xXX SMBus2.0 Controller Function 6 DevB:2xXX IPB Controller Function 2 DevB:7xXX Function ...
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Table 43. PCI Configuration Spaces Primary BUID+1 2 Primary BUID+1 3 Primary BUID+1 5 Primary BUID+1 6 Secondary 0 0 Secondary 0 1 Secondary 0 2 Secondary 1 0 Table 44. Fixed Address Spaces Port(s) Mnemonic 00-0F PORTxx 20-21 PORTxx ...
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Table 45. Relocatable Address Spaces Address Specified By Size Configuration (Bytes) Register DevB:0x74 256 DevB:0xA0 1024 Memory mapped HPETxx High Precision Event Timer control registers DevB:0xA8 32 Memory mapped 1 8 DevB:1x10 1 4 DevB:1x14 1 8 DevB:1x18 1 4 ...
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LPC bus (see DevB:0x40[SUBDEC]). Thus, the LPC bridge is the subtractive decode path for all unclaimed cycles. 4.2 PCI Bridge Configuration Registers (DevA:0xXX) These registers are located in PCI configuration space on the primary ...
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Bits Description (Continued MHz Capable. Read-only. This bit is fixed in the High state. 20 Capabilities Pointer. Read-only. This bit is fixed in the High state. 19:9 Reserved 8 SERREN. SERR_L Enable. Read-write. See DevA:0x3C[SERREN]. 7 Reserved. 6 ...
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PCI Bridge Memory Base-Limit Registers These registers specify the I/O-space (DevA:0x1C), non-prefetchable memory-space (DevA:0x20), and prefetchable memory-space (DevA:0x24) address windows for transactions that are mapped to the secondary PCI bus as follows: PCI I/O window = {16'h0000,DevA:0x1C_IOLIM,12'hFFF} >= address >= ...
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STA. Signaled target abort. Read; set by hardware; write 1 to clear. 1=The IC generated a target abort as a target on the secondary PCI bus. The IC generates a target abort if it receives a target abort (a ...
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HyperTransport™ Technology Capabilities Pointer Register Default: 0000 00C0h. Bits Description 31:8 Reserved. 7:0 CAPABILITIES_PTR. Specifies the offset to standard HyperTransport technology registers. PCI Bridge Interrupt and Bridge Control Register Default: 0000 00FFh. Bits Description 31:28 Reserved. 27 DTSERREN. Discard timer ...
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Bits Description (Continued) 17 SERREN. System error enable. Read-write. If DevA:0x04[SERREN] and DevA:0x3C[SERREN] are both High and if: • An address parity error of a transactions targetted to the PCI bridge is detected, or • SERR_L is detected asserted (DevA:0x1C[RSE] ...
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Unit ID count. Read-only. Specifies the number of unit IDs used by the IC. 20:16 BUID. Base UnitID. Read-write. This specifies the HyperTransport™ protocol base unit ID. The IC's logic uses this value to determine the unit IDs for ...
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Bits Description (Continued) 6 ENDOCH. End of chain. Read-only (not implemented). 5 INITCPLT. Initialization complete. Read-only; set by hardware; cleared by RESET_L. This bit is set by hardware when low-level link initialization has successfully completed. If there is no device ...
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HyperTransport™ Technology Revision ID Register Default: 0001 0022h. Bits Description 31:16 Link Frequency Capability. Read-only. These bits indicate that the IC supports 200 MHz HyperTransport™ clock. 15:12 Link Error. Read-only. These bits are hard wired to the Low state. 11:8 ...
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HyperTransport™ Link PHY Compensation Control Registers The HyperTransport™ PHY circuitry includes automatic compensation that is used to adjust the electrical characteristics for the HyperTransport transmitters and receivers. There is one compensation circuit for the receivers and one for each polarity ...
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Read-Write Register Default: 0000h. Bits Description 15:0 RW. Read-write. These bits are read-write accessible through software; they control no hardware. HyperTransport™ Technology Interrupt Discovery and Configuration Capability Register Default: 8000 0008h Bits Description 31:29 CAPTYPE. Capability type. Read-only. This register ...
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LPC Bridge Status And Command Register Default: 0220 000Fh. Bits Description 31:4 Hardwired to default values. 3 SPCYCEN. Special cycle enable. Read-write. 1=The IC responds to shutdown special cycles by using INIT to reset the processor. 0=The IC ignores shutdown ...
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I/O Control 1 Register Default: 00h. Bits Description 7 NMIONERR. Generate an NMI on error. Read-write. 1=An NMI is generated when one of the error status bits specified by Section 3.1.2 on page 37 is set. Note: see PM48[NMI2SMI_EN] for ...
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DPW2LPC. Discard posted writes targeting LPC. Read-write. 1=Posted writes targeting the LPC while a LPC bus master or DMA cycle is in progress get discarded. 0=Posted writes are passed to the LPC. 3 SPECEN. Special cycle enable onto secondary ...
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Table 47. Registers Affected by DevB:0x41[SHEN] I/O Port R/W Normal Mode DMA: 00h, 02h, 04h, W Base address for DMA channel 06h, C0h, C4h, C8h, R Current address for DMA channel CCh DMA: 01h, 03h, 05h, W Base byte count ...
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Table 47. Registers Affected by DevB:0x41[SHEN] (Continued) PIC: 20h R Interrupt request register for PIC 1 First read: ICW1 for controller 1 PIC: 21h R In service register for PIC 1 PIC: A0h R Interrupt request register for PIC 2 ...
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ROM Decode Control Register Default: 00h. SEGEN. ROM Segment Enables. This register specifies the address space mapped to the BIOS ROM on the LPC or PCI bus (see DevB:3x48[PCIBIOS]). Each bit specifies if the LPC or PCI bus is enabled ...
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Miscellaneous Control Register Default: 00h. Bits Description 7 EHCDIS. Enhanced host controller configuration space disable bit. Read-write. 1= The EHC configuration space (Dev0:2xXX) is disabled. Reads return all 0xF (and an NXA error response) and writes are ignored (and return ...
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Function/Device Enable Register Default: FFFFh. Bits Description 15:8 SECENS[7:0]. Secondary PCI bus device enables. Each of these bits apply to the first 8 internal devices on the secondary PCI bus. Bit[0] applies to device 0, etc. Bits that apply to ...
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Bits Description (Continued) 1 Must be Low. This bit is required to be Low at all times High then undefined behavior results. 0 APICEN. IOAPIC enable. 0=Accesses to the IOAPIC memory mapped register space are ignored; also, ...
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DPDH1, PFEN1_L]. These bits apply to the REQ_L[1]/GNT_L[1] pair. See bits 2:0. 2 DPDM0. Discard prefetch data upon upstream or peer to peer transaction. Read-write.This bit applies to the REQ_L[0]/GNT_L[0] pair When there is a transaction ...
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Prefetching of the first, second, third or fourth cacheline as enabled by CPFEN_MR, CPFEN_MRL, CPFEN_MRM only occurs when all of the following conditions are valid least 1 internal PCI response buffer is available least 1 internal ...
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Debug Control 1 Default: ???? ????h. Bits Description 31 Must be Low. Read-write. These bits are required to be Low at all times. Setting this bit can result in an undefined behaviour. 30:8 Reserved. Read-only. Reading these bits provides undefined ...
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BIOS Access Control Registers Default: 0000 0000h (for each). These registers consists of 24 4-bit registers called OAR (open at reset) locks. Each 4-bit register applies to a sector of the BIOS in the 5 megabyte BIOS range at the ...
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OAR Control Register Default: 00h. Bits Description 7:6 Reserved. 5 SMIACK. System in locked state. Read-only. 1=The last SMI mode special cycle received by the IC indicated that the host is in system management mode. 0=The last SMI mode special ...
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Watchdog Timer Base Address Register Default: 0000 0002h. Bits Description 31:5 WDTBAR. Watchdog Timer Base Address. Read-write. These bits are used in the memory space for decoding the memory mapped Watchdog Timer Registers. There is a maximum of 32 bytes ...
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CLRIOCHK. Clear PORT61[IOCHK]. Read-write. 1=Bit[6] of this register, IOCHK, is asynchronously cleared. 0=PORT61[IOCHK] can be set High. 2 CLRSERR. Clear PORT61[SERR]. Read-write. 1=Bit[7] of this register, SERR, is asynchronously cleared. 0=PORT61[SERR] can be set High. 1 SPKREN. Speaker enable. ...
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FERR_CLR_L FERR_L Figure 31. FERR_L and IGNNE_L Logic Level Sensitive IRQ Select Register Fixed I/O space; offset: 4D0h and 4D1h. Default: 0000h. Bits Description 15:0 LIRQ. Level sensitive IRQs. Each of these 16 bits controls whether a corresponding IRQ line ...
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System Reset Register Notes: 1. This register is enabled by DevB:3x41[PCF9EN]. 2. This register may be accessed only as a byte operation; 16- or 32-bit accesses to port CF8h are ignored by this register. Fixed I/O space; offset: CF9h. Default: ...
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Table 50. DMA Controller Register Summary Name Base Address Registers Base Word Count Registers Current Address Registers Current Word Count Registers Status Registers Command Registers Mode Registers Mask Registers Note: Although channel 4 base and current registers exist for compatibility, ...
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Legacy Programmable Interval Timer (PIT) Registers These timers are halted from counting, if enabled DevB:3x4C[PIT_DIS], when PRDY is asserted. Here are the ports used to access the legacy PIT: Table 53. PIT Register Summary Offset ...
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PIT Control Byte Register Fixed I/O space; offset: 43h. Default: 00h. Bits Description 7:6 SC[1:0]. Select counter. Specifies the counter that the command applies to as follows: 00b Counter 0. 01b Counter 1. 10b Counter 2. 11b Read back command. ...
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Table 54. PIC Register Summary Offset Access type 20h (master), Write-only; D[4]=1b A0h (slave) Write-only; D[4:3]=00b Read-write; D[4:3]=01b 21h (master), Write-only A1h (slave) Write-only Write-only Read-write D[4:3] above refers to bits[4:3] of the associated 8-bit data field. Normally, once ICW1 ...
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Initialization Command Word 3 for Slave Register Fixed I/O space; offset: A1h. Bits Description 7:3 Reserved (must be programmed to all zeros). 2:0 ID[2:0]. These bits must always be programmed to 02h. Initialization Command Word 4 Register Fixed I/O space; ...
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Operation Command Word 3 Register Fixed I/O space; offset: 20h for master and A0h for slave; data bits[4:3] must be 01b. Attribute: Write-only. Bits Description 7 Must be programmed Low. 6:5 ESMM (bit 6) and SMM (bit 5). Special mask ...
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The redirection registers are defined as follows: Bits Description 63:56 Destination. In physical mode, bits[59:56] specify the APIC ID of the target processor. In logical mode bits[63:56] specify a set of processors. 55:17 Reserved. 16 Interrupt mask. 1=Interrupt is masked. ...
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The interrupt definition registers are defined as follows: Bits Description 63 Wait for EOI. Read-write. This bit is set by hardware when an interrupt request is sent and cleared by hardware when the EOI is returned. Software may write a ...
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Watchdog Timer Control/Status Register Default: 0000 0008h. Bits Description 31:8 Read-only. 7 WTRIG. Watchdog Trigger. Read-write. Setting this bit triggers the watchdog timer to start a new count interval, counting down from the value that was last written to the ...
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... HPET148 HPET General Capabilities and ID Register Default: 0429 B17F 1022_82XXh Bits Description 63:32 PERIOD. Main Counter Clock Period in femtoseconds. 31:16 VENDID. Vendor ID. Hardwired to 1022h (AMD). 15 LEGSUP. Hardwired flag that legacy interrupt routing is supported. 14 Reserved. Hardwired to 0b. 13 SIZE. Hardwired flag 32 bit main counter. ...
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HPET General Interrupt Status Register Default: 0000_0000_0000_0000h Bits Description 63:3 Reserved. Read-only. These bits are hardwired C2_STS. Comparator 2 Interrupt Active. Read-write. If set to level-triggered mode, this bit defaults set by hardware ...
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HPE Timer 0 Configuration and Capabilities Register Default: 000F_DEFA_0000_0010h Bits Description 63:32 T0_ROUTE_CAP. These bits indicate to which interrupts in the IOAPIC this timer’s interrupt can be routed. Each bit represents one interrupt. Bit63 represents interrupt 31, bit 32 interrupt0. ...
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Bits Description (Continued) 3 T0PEN. Timer 0 Periodic Mode Enable. Read-write. If T0PCAP is 0. this bit is always 0. Writes have no effect. If T0PCAP is 1, this bits enables the period mode of timer disables ...
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HPE Timer 1 Configuration and Capabilities Register Default: 000F_DEFA_0000_0000h Bits Description 63:32 T1_ROUTE_CAP. These bits indicate to which interrupts in the IOAPIC this timer’s interrupt can be routed. Each bit represents one interrupt. Bit63 represents interrupt 31, bit 32 interrupt0. ...
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HPE Timer 1 Compare Register Default: 0000_0000_FFFF_FFFFh Bits Description 63:32 Reserved. Read-only. These bits are hardwired to 0. 31:0 T1COMP. Timer 1 Comparator Value. Read-write. Reads to this register return the value of the comparator. A write to this register ...
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Bits Description (Continued) 3 T2PEN. Read-only. This bit is always 0. 2 T2IEN. Timer 1Interrupt Enable. Read-write. This bit must be set to enable timer 0 to cause an interrupt when it times out. If this bit is 0, the ...
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Real-Time Clock Legacy Data Port I/O mapped (fixed); offset: 0071h. Bits Description 7:0 RTCDATA. Real-time clock data. This is the data port for accesses to the real-time clock CMOS RAM that is indexed by RTC70. Real-Time Clock 256-Byte Address and ...
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EIDE Controller Vendor And Device ID Register Default: 7469 1022h. Bits Description 31:16 EIDE controller device ID. 15:0 Vendor ID. EIDE Controller Status And Command Register Default: 0200 0000h. Bits Description 31:27 Read-only. These bits is fixed in the Low ...
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Bits Description (Continued) 10 PROGIF[2]. Secondary native mode. Read-write. 0=Compatibility mode for secondary port; DevB:1x18 and DevB:1x1C are ignored and not visible; address decode is based on legacy addresses 170h-177h, 376h; DevB:1x3C[7:0] Read-only zeros; DevB:1x3C[15:8] = 00h; IRQ15 may be ...
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EIDE Controller Primary Control Base Address Default: 0000 03F5h. Bits Description 31:2 BASE[31:2] Port Address. Read-write. These bits specify a 4-byte I/O address space that maps to the ATA-compliant control register set for the primary port (legacy I/O space 3F4h-3F7h). ...
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EIDE Subsystem ID and Subsystem Vendor ID Register Default: 0000 0000h. Bits Description 31:16 SSID. Subsystem ID register. This field is write accessible through DevB:1x70. 15:0 SSVENDORID. Subsystem vendor ID register. This field is write accessible through DevB:1x70. EIDE Controller ...
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Bits Description (Continued) 6:5 PHYSEL. PHY speed select. Read-only. These specify the selected PHY speed selection as follows: 00b=bigger PHY resistor (fast corner); 10b=medium PHY resistor; x1b=smaller PHY resistor (slow corner). The power-up default for these bits is device specific. ...
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EIDE Controller Cycle Time and Address Setup Time Register For bits[7:0] the value in each 2-bit field, plus one, specifies the address setup time in 30 nanosecond PCI clocks; this applies to all PIO and multi-word DMA cycles. For bits[31:16] ...
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EIDE Controller UDMA Extended Timing Control Register The definition of each of the four 8-bit fields in this register are identical; they apply to different drives. Default: 0303 0303h. Bits Description 31:24 P0UDMA. Primary drive 0 UDMA timing control. 23:16 ...
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EIDE Power Management Register This register controls the power state of the two IDE ports. When an IDE port is powered up designed to be fully operational. When it is powered down, outputs DADDR[S,P][2:0], DCS1[S,P]_L, DCS3[S,P]_L, DDACK[S,P]_L, DIO[R,W][S,P]_L ...
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EIDE Device and Subsystem ID Read-Write Register Default: 0000 0000h. Bits Description 31:16 SSID. Subsystem ID register. The value placed in this register is visible in DevB:1x2C[31:16]. 15:0 SSVENDORID. Subsystem vendor ID register. The value placed in this register is ...
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Primary Bus Master IDE PRD Table Address Register Default: 0000 0000h. Bits Description 31:2 PPRDADD[31:2]. Primary physical region descriptor table base address. Read-write. 1:0 PPRDADD[1:0]. Read-only. These bits are fixed in the Low state. Secondary Bus Master IDE Command Register ...
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... System Management Bus Configuration Registers (DevB:2xXX) SMBus Controller Vendor and Device Id Default: 746A_1022h Bits Description 31:16 SMBID. Provides the SMBus controller device identification. 15:0 AMDID. Provides AMD’s PCI vendor identification. SMBus Controller Command and Status Default: 0200_0000h Bits Description 31:16 STAT. Read-only. ...
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SMBus Controller BIST, Header and Latency Default: 0000_0000h Bits Description 31:24 BIST. Read-only. 23:16 HEADER. Read-only. 15:8 LATENCY. Read-write. The latency timer defines the minimum amount of time, in PCI clock cycles, that the bus master can retain ownership of ...
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SMBus Controller Revision Id and Class Code Alias Default: 0C05_0001h Bits Description 31:24 BASECLASS. Read-write. These bits default to 0Ch indicating a serial bus controller. 23:16 SUBCLASS. Read-write. These bits default to 05h indicating a SMBus controller. 15:8 PROGIF. Read-write. ...
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Data Register Default: 0000h Bits Description 7:0 DATA. Data port. This register acts as a port for transferring data between the host and the SMBus controller. Writes to this port by the host are stored in the internal input data ...
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Bits Description 3 CMD. Command byte. 1: Byte in the internal input data register is a command byte. 0: Byte in the internal input data register is a data byte. This bit is set by hardware upon write access to ...
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SMBALERT_EN. SMBALERT enable. 1b enables an internal notification header of 80h to be set and SC04[SCI_EVT set when an SMBALERT event occurs. Note: This bit resides on the VDD_COREX power plane and is cleared to its default ...