AMD-640AC Advanced Micro Devices, AMD-640AC Datasheet
AMD-640AC
Specifications of AMD-640AC
Related parts for AMD-640AC
AMD-640AC Summary of contents
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... Preliminary Information AMD-640 System Controller Data Sheet TM ...
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... Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. AMD-640, AMD-645, K86, AMD-K5, AMD-K6, and the AMD-K6 logo are trademarks of Advanced Micro Devices, Inc. MMX is a trademark of the Intel Corporation. Microsoft and Windows are registered trademarks, and Windows trademark of Microsoft Corporation. ...
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... AMD-640 System Controller Data Sheet 3 21090C/0—June 1997 ...
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... Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 Integrated Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 Integrated Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.4 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 2 Overview 2.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 AMD-640 System Controller Buffers . . . . . . . . . . . . . . . . . . . 2-4 2.3 Definitions, Conventions, and References 2.3.1 2.3.2 3 Ordering Information 4 Signal Descriptions 4.1 Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 PCI Interface Signals ...
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... AMD-640 System Controller Data Sheet 5 Functional Operation 5.1 Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 5.1.2 5.1.3 5.2 Cache Controller 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3 DRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.4.9 6 Initialization iv Preliminary Information Write Posting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Read Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Read-Around-Writes ...
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... DRAM Bank 0 Ending Address (Offset 5Ah 7-19 DRAM Type (Offset 60h 7-20 Shadow RAM Control Register #1 (Offset 61h 7-21 Shadow RAM Control Register #2 (Offset 62h 7-21 Shadow RAM Control Register #3 (Offset 63h 7-22 DRAM Timing (Offset 64h 7-23 DRAM Control Register #1 (Offset 65h 7-24 AMD-640 System Controller Data Sheet 7-1 v ...
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... AMD-640 System Controller Data Sheet 7.5.11 32-Bit DRAM Width Control Register (Offset 67h 7-26 7.5.12 DRAM Refresh Counter (Offset 6Ah 7-27 7.5.13 DRAM Refresh Control Register (Offset 6Bh 7-27 7.5.14 SDRAM Control Register (Offset 6Ch 7-28 7.5.15 DRAM Drive Strength Control Register (Offset 6Dh 7-29 7.5.16 ECC Control Register (Offset 6Eh 7-30 7 ...
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... IBIS Models 10.1 Selectable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 I/O Buffer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.3 I/O Model Application Note . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.4 I/O Buffer AC and DC Characteristics . . . . . . . . . . . . . . . . . 10-3 10.5 References 11 Pin Descriptions 11.1 Electrical Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 Pin Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 12 Package Specifications Table of Contents Preliminary Information AMD-640 System Controller Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10-1 11-1 12-1 vii ...
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... AMD-640 System Controller Data Sheet viii Preliminary Information 21090C/0—June 1997 Table of Contents ...
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... Figure 9-2. Figure 12-1. 328-Pin BGA Package Preliminary Specification 12-2 List of Figures Preliminary Information AMD-640 Chipset System Block Diagram . . . . . . . . . . . . . . . 1-4 AMD-640 System Controller Block Diagram . . . . . . . . . . . . 2-3 Memory-to-PCI Buffer 2-4 PCI-to-Memory Buffer 2-4 Posted Write Buffer Organization ...
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... AMD-640 System Controller Data Sheet x Preliminary Information 21090C/0—June 1997 List of Figures ...
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... Table 9-3. Table 9-4. Table 9-5. Table 9-6. Table 9-7. Table 11-1. Functional Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Table 11-2. AMD-640 System Controller Pin Diagram (Top View 11-4 Table 12-1. 328-Pin BGA Package Preliminary Specification . . . . . . . . . 12-1 List of Tables Preliminary Information Common 8-Bit Tag Configurations . . . . . . . . . . . . . . . . . . . . . . 5-6 Writeback Configurations for 7-Bit Tag with Modify Bit . . . . 5-7 Cache Hit Action Taken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Cache Miss Action Taken ...
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... AMD-640 System Controller Data Sheet xii Preliminary Information 21090C/0—June 1997 List of Tables ...
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... AMD-K5™ processor, AMD-K6™ MMX™ enhanced processor, and other Socket 7-compatible processors. The AMD-640 chipset consists of the AMD-640 system controller in a 328-pin BGA package and the AMD-645TM peripheral bus controller in a 208-pin PQFP package. The AMD-640 system controller features the 64-bit Socket 7 interface, integ rated writeback cache controller, system memory controller, and PCI bus controller ...
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... AMD-640 System Controller Data Sheet 32-byte line size compatible with L1 cache Integrated 10-bit tag comparator 3-1-1-1 read/write timing for PBSRAM access at 66 MHz 3-1-1-1-1-1-1-1 back-to-back read timing for PBSRAM access at 66 MHz Sustained three-cycle access to PBSRAM, DRAM write buffer, and PCI write buffer at 66 MHz ...
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... Features Preliminary Information EDO DRAMs on a 66-MHz bus: 5-2-2-2 on-page, 8-2-2-2 start-page, 11-2-2-2 page-miss, and 5-2-2-2-3-2-2-2 back-to-back access 5-1-1-1 on-page, 8-1-1-1 start-page, 10-1-1-1 page-miss, and 5-1-1-1-3-1-1-1 back-to-back access 6-1-1-1 on-page, 9-1-1-1 start-page, 11-1-1-1 page-miss, and 6-1-1-1-3-1-1-1 back-to-back access Programmable refresh rate CAS-before-RAS Populated banks only AMD-640 System Controller Data Sheet 1-3 ...
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... AMD-640 System Controller Data Sheet SERR# PREQ# PGNT# System Management Figure 1-1. AMD-640 Chipset System Block Diagram 1-4 Preliminary Information AMD-K6 Processor Host Bus 64-bit Memory Bus AMD-640 System Controller 64-bit System Controller PCI Bus 32-bit AMD-645 Peripheral Bus Southbridge LAN Ethernet Controller ...
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... System The local bus is a non-multiplexed bus based on AMD and Intel processors. The AMD-640 system controller is capable ry transactions ...
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... Figure 2-1 illustrates the full complement of features and functions built into the AMD-640 system controller’s system logic. The configuration of the AMD-640 system controller can be programmed via I/O-mapped configuration registers. A PCI- to-CPU read buffer can assemble up to eight bytes of data. A ...
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... PCI-to-DRAM write buffer allows PCI initiators to post writes to memory without adding delay on either the PCI or processor bus. In addition, the AMD-640 system controller contains a PCI arbiter. HA[31:3] HD[63:0] ADS# AHOLD BE[7:0]# BOFF# BRDY# CACHE# D/C# EADS# HITM# HLOCK# Byte KEN#/INV ...
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... AMD-640 System Controller Buffers Figure 2-2 and Figure 2-3 show the basic construction of the buffers in the AMD-640 system controller. Figure 2-2 shows a path from a 64-bit bus to a 32-bit bus (memory-to-PCI). Figure 2-3 shows a path from a 32-bit bus to a 64-bit bus (PCI-to- memory). The control logic assembles 32-bit words into 64-bit words or disassembles 64-bit words into 32-bit words ...
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... Reserved Bits and Signals—Signals or bus bits marked reserved must be driven inactive or left unconnected, as indicated in the signal descriptions. These bits and signals are reserved by AMD for future implementations. When software reads registers with reserved bits, the reserved bits must be masked. When software writes such registers, it must first read the register and change only the non- reserved bits before writing back to the register ...
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... AMD-640 System Controller Data Sheet 2.3.1 Data Quantities—A word is two bytes (16 bits), a dword or doubleword is four bytes (32 bits), and a qword or quadword is eight bytes (64 bits). Addressing—Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries, in which each byte can be separately enabled. Abbreviations—The following notation is used for bits and bytes: • ...
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... AMD-K5 Processor Data Sheet, order# 18522 AMD-K5 Processor Technical Reference Manual, order# 18524 AMD-K6 MMX Enhanced Processor Data Sheet, order# 20695 AMD-645 Peripheral Bus Controller Data Sheet, order# 21095 Bus Architecture PCI Local Bus Specification, Revision 2.1, PCI Special Interest Group, Hillsboro, Oregon, 1993. ...
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... AMD-640 System Controller Data Sheet 2-8 Preliminary Information 21090C/0—June 1997 Overview ...
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... Contact your AMD representative for detailed ordering information. AMD-640 A C OPN AMD-640AC Notes: 1. Valid Combinations lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly-released combinations. ...
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... AMD-640 System Controller Data Sheet 3-2 Preliminary Information 21090C/0—June 1997 Ordering Information ...
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... Processor Interface Signals ADS# Address Strobe ADS# indicates to the AMD-640 system controller that a new bus cycle is starting. When ADS# is asserted, the AMD-640 system controller latches the address bus and all cycle definition signals corresponding to this bus cycle on the rising edge of HCLK. ...
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... EADS# External Address Strobe The AMD-640 system controller asserts EADS# off the rising HCLK edge to snoop each cache line transferred during all PCI-to-DRAM cycles. EADS# strobes the snoop address into the L1 cache cache hits, the processor invalidates unmodified data during writes, and sources (drives) modified data during PCI initiator reads and writes ...
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... When the AMD-640 System Controller samples HLOCK# low, it withholds bus grants to other PCI initiators grant has already been issued to a PCI initiator, the AMD 640 will not assert BOFF# for L1 snoops. These actions effectively suspend a PCI-DRAM transfer until HLOCK# is deasserted. ...
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... AMD-640 System Controller Data Sheet memory or I/O space. When M/IO# is high, the AMD-640 System Controller enables accesses to DRAM and the L2 cache. When the access is not targeted to the cache or the DRAM, the AMD-640 system controller uses M/IO# to generate the PCI commands on C/BE[3:0] during the command phase of CPU-to-PCI cycles ...
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... PCI cycle when it is the initiator, and holds it low until the beginning of the last data transfer in the cycle. If the AMD-640 system controller is the targeted PCI device, it samples and latches the C/BE[3:0]# and AD[31:3] signals and asserts DEVSEL# at the first PCLK edge on which it samples FRAME# asserted ...
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... PCLK after it asserts FRAME# and holds it low until one cycle before the end of all transactions. IRDY input when the AMD-640 system controller is a PCI target. The AMD-640 system controller does not terminate a read or write cycle until it samples both IRDY# and TRDY# low ...
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... SERR# System Error A PCI agent (the AMD-640 system controller or other device) asserts SERR# off the rising clock edge one clock after it detects a system error. SERR input to the AMD-645 peripheral bus controller, which can be programmed to generate an NMI. STOP# PCI Bus Stop ...
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... DRAM when reading. They are driven by the AMD-640 system controller during writes. MPD[7:0] Memory ECC MPD[7:0] carry error correction codes for the eight bytes of data on MD[63:0]. They are inputs to the AMD-640 system controller during DRAM read cycles and outputs during DRAM write cycles. RAS[5:0]#/ Row Address Strobe 5:0/ ...
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... Synchronous DRAM WEB# Memory Write Enable WEC# WEA#, WEB#, and WEC# are write enable pins for all DRAM. They operate in parallel to drive greater loads than a single pin can support. Signal Descriptions Preliminary Information AMD-640 System Controller Data Sheet Outputs Outputs Outputs 4-9 ...
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... It is asserted off the rising clock edge. COE# Cache SRAM Output Enable The AMD-640 system controller asserts COE# off the rising clock edge of a cache read hit or writeback cycle and holds it low for the duration of the cycle to enable cache SRAM output. ...
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... GWE# Global Write Enable GWE# connects to the global write inputs of the cache SRAMs. The AMD-640 system controller asserts GWE# off the rising clock edge during L2 cache line fills to enable the SRAMs to receive each quadword of the line being returned by the DRAM controller. ...
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... PCLK PCI Clock PCLK receives a buffered host clock divided by two used by all of the AMD-640 system controller logic in the PCI clock domain. RESET# Reset Asserting RESET# resets the AMD-640 system controller and sets all register bits to their default values ...
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... L1 cache. The processor responds to a cache hit by asserting the HITM# line. This action notifies the AMD-640 system controller that a modified cache line must be written back to the system before the intended memory access can be performed. A snoop filtering mechanism in the ...
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... When a writeback cache is employed, the AMD-640 system controller sees a block transaction every time the processor clears a cache line. The controller’s posted write buffers can handle four back-to-back block transactions without wait states ...
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... Read Buffer The AMD-640 system controller contains five 8-byte read buffers, each of which can hold an entire 64-bit word of data performance by prefetching data from the main memory and supplying the data to the processor with zero wait states ...
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... AMD-640 System Controller Data Sheet Processor Address Bus Buffer 1 Address Tag Buffer 2 Address Tag Buffer 3 Address Tag Buffer 4 Address Tag Buffer 5 Address Tag Figure 5-2. Read Buffers Memory reads that fill the processor’s caches are by far the most common types of reads. These reads occur as a burst read of four quadwords (32 bytes). When a burst read hits in the controller’ ...
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... Read-around-write is enabled by bit 7 of offset 53h. 5.2 Cache Controller The AMD-640 system controller supports direct-mapped cache systems with data sizes ranging from 128 Kbytes to 2 Mbytes. It can accommodate both synchronous and asynchronous data SRAMs to provide flexibility for system trade-offs between cost and performance ...
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... AMD-640 System Controller Data Sheet Table 5-1. Cache Size 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes Figure 5-3 shows how the AMD-640 system controller connects to a typical 8-bit tag cache. . HA[27:18] A[25:18] Cache Size = 256K Register Offset 51h Bits 1– AMD-640 System Controller Figure 5-3. 8-Bit Tag Cache Connections ...
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... AMD-640 system controller merely sets the modify bit of the altered cache line when a line is modified PCI cycle, the AMD-640 system controller snoops the processor’s L1 cache contains the desired PCI data and it has been modified, the cache line must be written back. ...
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... Processor writeback cycles are handled as normal processor write cycles PCI cycle, the AMD-640 system controller snoops the processor’s L1 cache contains the desired PCI data and it has been modified, the cache line must be written back ...
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... Processor write 1. PCI read PCI write Protocol To simplify system design, the AMD-640 system controller uses only one cache control bit (the modify bit) rather than the two bits employed in the MESI (modified, exclusive, shared, invalid) protocol. In writeback mode there are only three cache states— ...
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... AMD-640 System Controller Data Sheet Figure 5-4. Cache State Transitions Operating Modes The cache controller has three operating modes: enabled, disabled, and initialization. In the enabled mode, the cache controller functions normally. In the disabled mode, all read and write cycles are passed to the DRAM controller with no change to the cache data and tag bits ...
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... The completion of the data G access is not shown. HCLK 1 W/R# ADS# NA# BRDY# HA[31:3] Addr for Data A BE[7:0]# CADV# CADS# CE1# COE# TAGWE# TA[9:0] HD[63:0] CACHE# Figure 5-5. Pipelined Burst Read Cycle Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Addr for Data 5-11 ...
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... AMD-640 System Controller Data Sheet Figure 5-6 shows a burst write to PBSRAM. Note that CADV#, which allows the address to increment, is high for one clock following ADS#. The completion of the data G access is not shown HCLK 1 W/R# ADS# NA# BRDY# HA[31:3] BE[7:0]# CADV# CADS# CE1# GWE# BWE# COE# TAGWE# ...
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... On a cache read hit to a modified line, the buffers allow subsequent cache lines to be read while the altered line is written back to DRAM. On cache write misses, the AMD-640 system controller asserts the BRDY# line, enabling the processor to start the next cycle while the buffered data is written to DRAM ...
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... Snoop filtering increases processor bandwidth by reducing the number of snoop cycles (also called inquire cycles) on the local bus. When a PCI cycle causes a snoop, the AMD-640 system controller retains the number of the cache line subsequent access addresses the same line, no snoop cycle is generated. ...
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... PCI burst, thus avoiding this potential loss of time. 5.3 DRAM Controller The AMD-640 system controller supports up to six 64-bit banks of DRAM with a capacity 768 Mbytes. Each bank can contain 1-, 2-, 4-, or 16-Mbit by 32- or 64-bit DRAMs, in any combination of FPM, EDO, or SDRAM. FPM and EDO DRAMs can be 72-pin SIMMs with either 36 bits if Error Correcting Code (ECC) is required bits (no ECC) ...
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... Pairs must be of the same type (FPM or EDO DRAM 64-bit mode is used, the banks must be paired. They need not be paired in 32-bit mode. 3. They must be populated in order. i.e., 0,1,2,3,4,5. Figure 5-7 shows how EDO DRAM connects to the AMD-640 system controller. Figure 5-8 shows connections to SDRAM. MD[63:32] WEA# ...
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... SDRAM DIMM module 168-Pin, 64- or 72-bit SDRAM DIMM module 168-Pin, 64- or 72-bit SDRAM DIMM module 168-Pin, 64- or 72-bit SDRAM DIMM module 168-Pin, 64- or 72-bit SDRAM DIMM module 168-Pin, 64- or 72-bit SDRAM DIMM module AMD-640 System Controller Data Sheet WEA# WEB# WEC# CS[5:0]# 0 ...
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... Error Correction Code The AMD-640 system controller supports error correction code (ECC) to check the integrity of transactions with system memory. ECC, also referred to as Hamming code, corrects single-bit and double-bit errors as well as some triple-bit errors ...
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... DRAM Refresh The AMD-640 system controller provides DRAM refresh that is transparent to the rest of the system. Normal, burst, or CAS- before-RAS (CBR) refresh can be selected through offset 6Bh (page 7-27). Accesses to the read and posted write buffers are allowed during a refresh period ...
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... AMD-640 System Controller Data Sheet The AMD-640 system controller also contains a refresh counter that provides 4096 refresh cycles on MA[11:0]. This permits the use of DRAMs Mbits in size. The refresh period is derived by dividing HCLK by 16 (four-bit prescale) and a refresh divisor based on the 8-bit value in offset 6Ah. The refresh divisor can be calculated by multiplying the DRAM’ ...
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... CAS# delay can be individually programmed in configuration register 64h. 5.3.4 Shadow RAM The AMD-640 system controller supports shadowing of system, video, and other BIOS functions to accelerate access. The BIOS normally resides in Read Only Memory (ROM) to prevent altering the content of this crucial system code. Because ROM ...
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... EDO DRAM can increase system speed because most EDO accesses take one clock cycle less than standard FPM devices. The AMD-640 system controller generates the appropriate clock cycles for FPM or EDO based on the information in configuration registers 60h and 64h. EDO memory allows shorter page cycle times by keeping the output drivers on when CAS# goes inactive ...
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... HCLK ADS# BE[7:0]# NA# HA[31:3] Addr A BRDY# W/R# MA[13:0] Col Addr A RAS[5:0]# CAS[7:0]# WEx# HD[63:0] MD[63:0] Figure 5-10. Pipelined EDO Read (5-2-2-2, 3-2-2-2) Functional Operation Preliminary Information Addr AMD-640 System Controller Data Sheet 5-23 ...
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... AMD-640 System Controller Data Sheet Figure 5-11 shows a write to address A followed by a pipelined read request from address G. The pipelined read is not shown. The write from the processor to the write buffer is a 3-1-1-1 cycle. The transfer from the buffer to DRAM does not begin until the entire line is written to the write buffer. The write ...
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... Control signals need only be valid during CS#. The BIOS configures the Memory Controller for SDRAM memory operation for each bank of memory by programming offset 60. Functional Operation Preliminary Information sampled asserted. They are turned off when WEx# or CS# goes high. AMD-640 System Controller Data Sheet 5-25 ...
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... AMD-640 System Controller Data Sheet Figure 5-12 shows an SDRAM burst read, followed by a single read to address G, then a read access to address X in the other bank. The bank change is indicated by MA11 changing from low to high. HCLK ADS# BRDY# W/R# KEN# NA# HA[31:3] BE[7:0]# HD[63:0] MD[63:0] SRAS[C:A]# SCAS[C:A]# WEx# DQM[7:0] MA11 ...
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... KEN# NA# HA[31:3] BE[7:0] HD[63:0] MD[63:0] SRAS[C:A]# SCAS[C:A]# WEx# DQM[7:0]# MA11 MA10 MA[9:0] CS0# CS1# Figure 5-13. SDRAM Write Cycle Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Addr for Data A Addr for Data Addr for Data ...
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... AMD-640 System Controller Data Sheet Figure 5-14 shows a CPU read miss. As the processor reads data from DRAM, the cache controller captures the data and stores it in the L2 cache, updating the tag to reflect a new line. Note the first GWE# is wider, allowing Data A and written sequentially ...
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... G H MD[63:0] Figure 5-15. Read Miss With Modified L2 Cache Line Functional Operation Preliminary Information Addr for Data A Cache Write A Cache Write D Row A Col AMD-640 System Controller Data Sheet Addr for Data X Row G Col 5-29 ...
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... AMD-640 system controller’s configuration register addresses, the controller passes the I/O cycle to the PCI bus. The AMD-640 system controller posts the I/O cycle in one of its write buffers. The controller does not respond to I/O cycles driven by PCI initiators on the PCI bus. It allows these cycles to complete on the PCI bus ...
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... byte/word/dword processor reads are passed on to the PCI bus by the AMD-640 system controller as such. The read buffer is always enabled. When the processor reads from the PCI bus, the AMD-640 system controller acts as a PCI initiator ...
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... PHASE Figure 5-16. Basic PCI Read Operation Figure 5-17 depicts a PCI burst read, which requires four data transfers, initiated by the AMD-640 system controller. In this example, the target inserts a wait state before the fourth data transfer by deasserting TRDY# for one PCLK and then reasserting TRDY# when it is ready to supply the data for the fourth transfer ...
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... The AMD-640 system controller also supports byte merging for writes to the video/frame buffer area. Burst Cycles The AMD-640 system controller writes all of its buffer contents in a single PCI transaction when the bus becomes available. In this way, consecutive CPU-to-PCI writes, whether two full quadwords or several smaller transactions combined through byte merging, are performed in a single PCI transaction ...
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... AMD-640 System Controller Data Sheet Writes To PCI When the processor writes to the PCI bus, the AMD-640 system controller acts as a PCI initiator. Figure 5-18 depicts a write to PCI initiated by the AMD-640 system controller. The controller drives FRAME#, AD[31:0], and BE[3:0]# to initiate the write transaction during the first PCLK. FRAME# remains asserted until the data phase for the last transaction begins or the cycle is preempted ...
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... PHASE Figure 5-18. PCI Write Figure 5-19 depicts a burst write with four data transfers on the PCI bus initiated by the AMD-640 system controller. This example also includes a wait state inserted by the target for both the first and the third data transfers. The target inserts the wait state by delaying the assertion of TRDY# for the first transfer ...
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... These two registers are used to access all other internal configuration registers of the AMD-640 system controller. The AMD-640 system controller decodes accesses to these two I/O addresses and handles them internally. A read to a non- existent configuration register returns a value of FFh. Accesses to all other I/O addresses are forwarded to the PCI bus as regular I/O cycles ...
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... Read and write cycles involving the AMD-640 system controller configuration registers are functionally the same as other I/O read and write cycles. Both require five PCI clock cycles to complete. Configuration timing is illustrated in Figure 5-20 and Figure 5-21. HCLK ADS# BE[7:0]# NA# HA[31:3] Addr A BRDY# W/R# HD[63:0] PCLK Figure 5-20 ...
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... AMD-640 System Controller Data Sheet 5.4.5 PCI Transaction Examples CPU Read from PCI Figure 5-22 shows the processor reading from a target on the Target PCI bus. There is a six-clock latency from the PCI bus to the CPU bus. The single wait state on the PCI bus is included as an example and is not required ...
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... CPU Write to PCI Figure 5-23 shows the processor writing to a target on the PCI Target bus. The AMD-640 system controller stores the processor data in the PCI write buffer and controls the transfer from the write buffer to the PCI bus. There is a seven-clock latency from the processor to the PCI bus ...
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... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-24 shows a PCI bus initiator reading from memory. A Read: page miss is indicated by RAS# toggling high, then low, to Cache Miss strobe in the new page address. The page miss accounts for the latency shown. Note that an entire cache line ( read from DRAM even though only four 32-bit words ( are requested (FRAME# is negated at C) ...
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... HD[63:0] MD[63:0] MA[13:0] RAS[5:0]# CAS[7:0]# WEx# PCLK FRAME# DEVSEL# AD[31:0] C/BE[3:0]# IRDY# TRDY# REQ# GNT# Figure 5-24. PCI Bus Initiator Read: Cache Miss Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Snoop Miss Begin Memory Read Row Addr MRD ...
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... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-25 shows a PCI initiator read. L1 and L2 are snooped Read: for the data. L2 misses, but L1 hits a modified line (indicated Modified L1 Hit HITM#). The L1 cache controller writes the data to the Miss DRAM write buffer and the PCI read buffer via the PCI forward mechanism ...
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... CAS[7:0]# WEx# PCLK FRAME# DEVSEL# AD[31:0] C/BE[3:0]# IRDY# TRDY# REQ# GNT# Figure 5-25. PCI Bus Initiator Read: Modified L1 Hit, L2 Miss Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Snoop L1 L1 Hit Modified Data from cache Snoop Data forwarded to PCI Addr A MRD AB ...
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... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-26 shows a PCI initiator read. L1 and L2 are snooped. Read: L1 misses but L2 hits. There is no write to DRAM because the L1 Miss, Unmodified line is not modified. The L2 cache data is forwarded to the PCI L2 Hit bus. Note that the entire cache line is read, and if a successive PCI read addresses this data, it will be supplied directly from the AMD-640 system controller ...
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... CADS# COE# GWE# BWE# CE1# TAGWE# TA[9:0] HD[63:0] PCLK FRAME# DEVSEL AD[31:0] C/BE[3:0]# IRDY# TRDY# REQ# GNT# Figure 5-27. PCI Bus Initiator Read: Modified L1 Hit Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Snoop L1 Hit Modified L2 Miss Write L1 Data Addr MRD BE[3:0 5-45 ...
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... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-28 shows a PCI write to DRAM. L1 and L2 are Write: snooped, and both miss. The AMD-640 system controller stores Cache Miss the PCI data into its write buffer and subsequently writes this data ( DRAM. ...
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... MD[63:0] MA[13:0] RAS[5:0]# CAS[7:0]# WEx# PCLK FRAME# DEVSEL# AD[31:0] Addr C/BE[3:0]# MWR IRDY# TRDY# Figure 5-29. PCI Bus Initiator Write: L1 Hit, L2 Miss Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Snoop L1 Hit Snoop L2 Miss CPU write to DRAM buffer BE[3:0 Merged Data Written to DRAM ...
Page 87
... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-30 shows a PCI write to DRAM. L1 and L2 are Write: snooped miss and hit. The L2 line is not written L1 Miss, Unmodified back because it is not modified. The line is simply marked L2 Hit invalid because new data is written into the DRAM. ...
Page 88
... TAGWE# TA[9:0] HD[63:0] MD[63:0] MA[13:0] RAS[5:0]# CAS[7:0]# WEx# PCLK FRAME# DEVSEL# AD[31:0] Addr C/BE[3:0]# MWR IRDY# TRDY# Figure 5-31. PCI Bus Initiator Write: Modified L1 Hit, L2 Hit Functional Operation Preliminary Information AMD-640 System Controller Data Sheet Snoop L1 Snoop L2 Hit L1 Hit Modified Write L1 data 5-49 ...
Page 89
... AMD-640 System Controller Data Sheet PCI Bus Initiator Figure 5-32 shows a PCI initiator write to DRAM. L1 and L2 are Write: snooped miss but hit and is modified. The L1 Miss, Modified L2 controller reads the modified L2 line into the DRAM write Hit buffer, merges it with the PCI data, and writes the merged data to DRAM ...
Page 90
... AMD-640 system controller ignores the cycle and allows it to complete on PCI.) PCI Reads In a PCI read, the AMD-640 system controller combines the 16- doubleword PCI buffer with the 10-doubleword DRAM read buffer, effectively forming a 26-doubleword PCI read buffer. ...
Page 91
... PCI Fast Back to Back cycles The PCI specification allows fast back-to-back cycles to the same target or to different targets. In the AMD-640 system controller, this feature is controlled by the command register (offset 05h–04h) for reads and the PCI configuration register (offset 71h), bit 7 for writes. Offset 73h, bit 7 must be set for slow decode if fast back-to-back is selected ...
Page 92
... Power Management The AMD-640 system controller supports the Advanced Power Management Specification, version 2.1. The counters required for this feature are contained in the AMD-645 peripheral bus controller companion device. SMIACT controls selection of the SMM memory space. To initialize the SMM memory, the BIOS writes 01 to offset 63h, bits 1-0 ...
Page 93
... AMD-640 System Controller Data Sheet 5-54 Preliminary Information 21090C/0—June 1997 Functional Operation ...
Page 94
... Initialization All programmable features in the AMD-640 system controller are controlled by the PCI configuration registers, which are normally written to only during system initialization. This section summarizes the register functions, default values, access types, and addresses (offset numbers). For more detailed descriptions of the configuration registers, see Section 7 ...
Page 95
... AMD-640 System Controller Data Sheet Table 6-2. Configuration Space Cache Control Registers Offset Cache Control 50h Cache Control 1 51h Cache Control 2 52h Non-Cacheable Control 53h System Performance Control 55h–54h Non-Cacheable Region #1 57–56h Non-Cacheable Region #2 6-2 Preliminary Information Default Recommended Setting 00h ...
Page 96
... DRAM Refresh Control Register 6Ch SDRAM Control Register 6Dh DRAM Drive Strength Control Register 6Eh ECC Control Register 6Fh ECC Status Register Initialization Preliminary Information AMD-640 System Controller Data Sheet Default Recommended Setting 40h 44h 10-bit column 05h 03h banks 0-3 populated 01h ...
Page 97
... AMD-640 System Controller Data Sheet Table 6-4. Configuration Space PCI Control Registers Offset Cache Control 70h PCI Buffer Control 1 71h Processor to PCI Flow Control #1 72h Processor to PCI Flow Control #2 73h PCI Target Control 74h PCI Initiator Control 75h PCI Arbitration Control #1 76h ...
Page 98
... Reserved I/O Address OCFBh To specify the AMD-640 system controller, set bit 31, the enable bit. If bit 31 is cleared, the AMD-640 system controller passes the data through as an I/O transaction. The bus number, device number, and function number of the AMD-640 system controller are all 00h. ...
Page 99
... AMD-640 System Controller Data Sheet The PCI specification calls for 256 configuration registers in each target device to be organized on doubleword boundaries. Each register is numbered as an “offset” from zero. To access a particular register, the most significant six bits of the offset are written to bits 7-2 of the target address to specify the register’ ...
Page 100
... Register Overview Tables 7-2 through 7-5 summarize the AMD-640 system controller configuration register offsets, functions, default values, and access types. Access types are indicated as follows: R/W Read/Write R/O RWC Read, Write 1’s to Clear individual bits Table 7-2. Offset 01h–00h 03h–02h 05h–04h 07h– ...
Page 101
... AMD-640 System Controller Data Sheet Table 7-4. Offset 7-4 Preliminary Information Configuration Space DRAM Control Registers Cache Control 58h DRAM Configuration Register #1 59h DRAM Configuration Register #2 5Ah DRAM Bank 0 Ending 5Bh DRAM Bank 1 Ending 5Ch DRAM Bank 2 Ending 5Dh DRAM Bank 3 Ending 5Eh ...
Page 102
... Device ID (Offset 03h–02h) Bit Reset This read-only value of 1595h represents the AMD-640 system controller. Configuration Registers Preliminary Information Configuration Space PCI Control Registers PCI Bus Control 70h PCI Buffer Control Register 71h Processor-to-PCI Control Register#1 72h ...
Page 103
... Memory Write and Invalidate Command (always reads 1)—This feature increases overall performance by eliminating cache writebacks when a PCI initiator writes to the address of a modified line. The AMD-640 system controller invalidates the cache line rather than writing it back to DRAM Bus initiators may generate Memory Write and Invalidate ...
Page 104
... Signaled Initiator Abort (RO)—This bit is set by a PCI initiator when its transaction is terminated with Initiator Abort PCI transactions proceeding normally 1 = The AMD-640 system controller, acting as PCI initiator, has terminated a transaction before completion Bit 12 Received Target Abort (RWC)—The target issues a target abort when it detects a fatal error or cannot complete a transaction ...
Page 105
... Reserved (always reads 0) 7.3.5 Revision ID (Offset 08h) Bit 7 6 Reset — — Bits 7–0 AMD-640 System Controller Revision Code (RO)—04h = Revision F (as of June 1997). 05h = Revision G. 06h = Revision H. 7.3.6 Programming Interface (Offset 09h) Bit 7 6 Reset 0 0 Bits 7–0 AMD-640 System Controller Programming Interface (always reads 00h)—This register is defined in different ways for each combination of base and subclass codes ...
Page 106
... Reset 0 0 Bits 7–0 Cache Line Size (always reads 0)—The AMD-640 system controller accepts, but does not implement, the PCI Memory Write and Invalidate (MWI) command, for which the cache lines size is a required component. Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet ...
Page 107
... Bits 2–0 Reserved (always reads 0) 7.3.11 Header Type (Offset 0Eh) Bit 7 6 Reset 0 0 Bits 7–0 PCI Header Type (RO)—The AMD-640 system controller PCI Header Type is 00h. 7.3.12 Built-In Self Test (BIST) (Offset 0Fh) Bit 7 6 Reset 0 0 Bits 7–0 Built-in Self Test Functions (RO)—The AMD-640 system controller does not support built-in self-test functions, so this read-only register is 00h ...
Page 108
... Bit 2 Reserved (always reads 0) Bits 1–0 Cache SRAM Type (RW SRAM (default Reserved 10 = Burst SRAM 11 = Pipeline Burst SRAM Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet Reserved TAGCON Bit 0 ...
Page 109
... AMD-640 System Controller Data Sheet 7.4.2 Cache Control Register 2 (Offset 51h) Bit 7 6 Reserved Reset 0 0 Bits 7–6 Reserved (always reads 0) Bit 5 Backoff Processor (RW)—Used when register 52h, bit 2 is set for “L2 fill when CACHE# is inactive.” This bit should normally be cleared to 0 for best performance, although system-level performance differences are usually negligible ...
Page 110
... L2 Fill (RW)—Setting this bit forces the requested data to be filled into the L2 cache (provided that L2 cache is enabled), even if the processor does a read cycle with CACHE# deasserted. Although the AMD-640 system controller ignores the non-cacheable settings in the processor when this bit is set, it still adheres to the non-cacheable settings in its configuration registers ...
Page 111
... AMD-640 System Controller Data Sheet 7.4.4 System Performance Control Register (Offset 53h) Bit 7 6 RAW CRPC Reset 0 0 Bit 7 Read-Around-Write (RW)—This feature gives read priority over write. If data is queued in the write buffer, a read request will be serviced before the write is completed. When read-around-write is disabled, read and write requests are serviced in the order they are received ...
Page 112
... A16 A28 A27 A16 A28 A27 AMD-640 System Controller Data Sheet A26 A25 A24 A23 A22 A26 A25 A24 A23 A22 0 0 ...
Page 113
... AMD-640 System Controller Data Sheet 7.5 DRAM Control Registers 7.5.1 DRAM Configuration Register #1 (Offset 58h) Bit 7 6 Memory Address Map Type for Banks 0–1 Reset 0 1 Bits 7–5 Memory Address Map Type for Banks 0 and 1 (RW) EDO/FP DRAM 000 = 8-bit column address 001 = 9-bit column address ...
Page 114
... Bank 0, Bank 1 and Bank 5 are cacheable. Bank 2, Bank 3 and Bank 4 are non-cacheable if tag = 10 + modified bit. Bank 2, Bank 3 and Bank 4 are cacheable if tag is any other configuration than 10 + modify bit. Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet Reserved ...
Page 115
... AMD-640 System Controller Data Sheet 7-18 Preliminary Information 21090C/0—June 1997 Configuration Registers ...
Page 116
... HA27 HA26 HA25 Example 1 Example 2 Register Memory Values Size 01h 4 Mbytes 02h 8 Mbytes 03h 4 Mbytes 03h 03h 03h AMD-640 System Controller Data Sheet 2 1 Bit 0 HA24 HA23 HA22 Example 3 Register Memory Register Values Size Values 01h 8 Mbytes 02h 03h ...
Page 117
... AMD-640 System Controller Data Sheet 7.5.4 DRAM Type (Offset 60h) Bit 7 6 Reserved Reset 0 0 Bits 7–6 Reserved (always reads 0) Bits 5–4 DRAM Type for Banks 5–4 (RW) Bits 3–2 DRAM Type for Banks 3–2 (RW) Bits 1–0 DRAM Type for Banks 1–0 (RW) ...
Page 118
... Shadow Control Registers (Offsets 61h–63h) A memory read/write is considered shadowed when the accessed memory segment(s) in lower memory are intercepted by the AMD-640 system controller and redirected to data copies in the upper memory area. Each 16 -Kbyte segment in the UMA (64- Kbyte segments in addresses E0000h–FFFFFh) can be enabled for shadowing by setting at least one of its corresponding two bits in offsets 61h– ...
Page 119
... AMD-640 System Controller Data Sheet 7.5.7 Shadow RAM Control Register #3 (Offset 63h) Bit 7 6 E0000–EFFFFh Reset 0 0 Bits 7–6 Shadow RAM Control for Addresses E0000–EFFFFh (RW) Bits 5–4 Shadow RAM Control for Addresses F0000–FFFFFh (RW) Each pair of bits controls the accessibility of its corresponding address ...
Page 120
... Bit 0 Column Address to CAS# Delay (RW (default) Note HCLK period. Configuration Registers Preliminary Information RAS# Pulse Width CAS# Pulse Width EDO cycles AMD-640 System Controller Data Sheet 2 1 Bit 0 Write PW CACAS 7-23 ...
Page 121
... AMD-640 System Controller Data Sheet 7.5.9 DRAM Control Register #1 (Offset 65h) Bit 7 6 Page Mode Control Reset 0 0 Bits 7–6 Page Mode Control (RW Page closes after access (default Reserved 10 = Page stays open after access until page time out or page miss 11 = Page closes if processor is idle, i.e., there has been no DRAM access ...
Page 122
... SDRAM RAS#-to-CAS# Delay Reduction (RW)—This bit is only set for SDRAM. It has no effect if SDRAM is not selected in offset 60h Normal RAS#-to-CAS# delay (2T) (default Reduce RAS# (Active) to CAS# (Command) delay for SDRAM Note HCLK period. Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet Reserved 0 0 ...
Page 123
... AMD-640 System Controller Data Sheet 7.5.11 32-Bit DRAM Width Control Register (Offset 67h) Bit 7 6 RCAD NA Delay Reset 0 0 Bit 7 RAS#-to-Column Address Delay (RW (default Bit 6 NA# Delay (RW NA# delay (default). 1= Delay NA# 1T. The timing for a read hit depends on both the NA# delay and the number of PBSRAM banks, indicated by offset 51h, bit 3 (page 7-12) as shown in Table 7-9 ...
Page 124
... Disabled (default) (RAS#-only refresh Enabled Bit 6 Burst Refresh (RW Disable burst refresh (1 row refreshed every 15 µsec) (default Enable burst refresh (4 rows refreshed every 60 µsec) Bits 5–0 Reserved (always reads 0) Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet Refresh Counter ...
Page 125
... AMD-640 System Controller Data Sheet 7.5.14 SDRAM Control Register (Offset 6Ch) Bit 7 6 64MBSI SBW Reset 0 0 Bit 7 64 Mbit SDRAM Interleave (RW)—This bit is relevant only for 64-Mbit SDRAM with bit 5 set 2-bank interleave (default 4-bank interleave Bit 6 SDRAM Burst Write (RW) ...
Page 126
... Pin N17 Function 0 RAS5# 1 MA1 Bit 4 Force SMM Mode (RW)—When this bit is set the AMD-640 system controller responds as if the SMIACT# pin was asserted SMM mode not forced (default SMM mode forced. Bit 3 SDRAM command Drive (SRAS#, SCAS#, WEx#) (RW (default) ...
Page 127
... AMD-640 System Controller Data Sheet 7.5.16 ECC Control Register (Offset 6Eh) Bit 7 6 ENMS Reserved Reset 0 0 Bit 7 ECC/Normal Mode Select (RW Parity (default ECC Bit 6 Reserved (always reads 0) Bit 5 Enable SERR# on ECC (Multi-bit) Error (RW Don’t assert SERR# for ECC errors (default) ...
Page 128
... Single-Bit Error DRAM Bank (RWC)—These bits contain the encoded value of the DRAM bank containing the single-bit error. Write 1’s to these bits to clear them. 000 = Bank 1 (default) 001 = Bank 2 010 = Bank 3 011 = Bank 4 100 = Bank 5 101 = Bank 6 Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet SBE Bit 0 ...
Page 129
... PCI write buffer (i.e., flushes the buffer) before granting the bus to another PCI initiator. This feature allows the AMD-640 system controller to grant the PCI bus to another initiator before the write buffer is emptied. Enabling this feature reduces grant latency. ...
Page 130
... Processor-to-PCI Flow Control Register #1 (Offset 71h) Bit 7 6 BURST2 Byte Merge Reset 0 0 Bits 7 & 3 PCI Burst Control Bits (RW)—These two bits determine how the AMD-640 system controller processes CPU-to-PCI write transactions, as shown in Table 7-11. Table 7-11. PCI Burst Control Bits Bit 7 Bit Every write transaction goes to the write buffer ...
Page 131
... PCI clock earlier than in standard PCI operation. This is the recommended setting Disabled (default Enabled (recommended) Bit 0 Enable 1-Wait-State PCI Cycles (RW)—The AMD-640 system controller delays assertion of IRDY# one clock cycle when this bit is set Disabled (default Enabled 7-34 Preliminary Information 21090C/0— ...
Page 132
... Reduce 1T for FRAME# Generation (RW)—When this bit is set, FRAME# is generated one PCI clock earlier than the setting in register 71h, bit 1. Doing so may cause timing problems and is not recommended Disabled (default) (recommended Enabled Configuration Registers Preliminary Information AMD-640 System Controller Data Sheet Retry Count and Backoff CFDCR 0 ...
Page 133
... AMD-640 System Controller Data Sheet Bit 0 Reduce 1T for Processor Read of PCI Target (RW)—Setting this bit reduces the delay from TRDY# to BRDY# by one HCLK to speed up system performance Disabled (default Enabled 7-36 Preliminary Information 21090C/0—June 1997 Configuration Registers ...
Page 134
... One wait state TRDY# response Bit 4 Reserved (always reads 0) Bit 3 Assert STOP# After Write Timeout (RW)—Enabling this feature allows the AMD-640 system controller to signal a retry to the initiator by asserting STOP#. This is the recommended setting Disabled (default Enabled (recommended) Bit 2 Assert STOP# After Read Timeout (RW))—Enabling this feature allows the AMD-640 system controller to signal a retry to the initiator by asserting STOP# ...
Page 135
... AMD-640 System Controller Data Sheet Bit 0 PCI Initiator Broken Timer Enable (RW)—Setting this bit forces the AMD-640 system controller to initiate PCI arbitration in the event that FRAME# has not been asserted 16 PCI clocks after the last GNT# was issued Disabled (default Enabled 7 ...
Page 136
... Bits 3–0 PCI Initiator Bus Timeout (RW)—Bits 3–0 represent the binary number of idle time periods the AMD-640 system controller allows on the PCI bus before forcing arbitration. Each time period is equal to 32 PCI clock cycles. The default value of 0000h disables this feature. ...
Page 137
... AMD-640 System Controller Data Sheet 7.6.7 PCI Arbitration Control Register #2 (Offset 76h) Bit 7 6 IPRE Reserved Reset 0 0 Bit 7 Initiator Priority Rotation Enable (RW Disabled (arbitration per register 75h, bit 7) (default Enabled (arbitration per bits 5–4 below) Bit 6 Reserved (always reads 0) Bits 5–4 ...
Page 138
... Electrical Data 8.1 Absolute Ratings Long-term reliability and functional integrity of the AMD-640 system controller are guaranteed as long not subjected to conditions exceeding the absolute ratings listed in Table 8-1. Table 8- DD3 V PIN V PIN T CASE T STORAGE Notes: 1. The voltage on any I/O pin on the CPU interface must not be greater than 0.5 V above the 2 ...
Page 139
... AMD-640 System Controller Data Sheet 8.2 Operating Ranges The functional operation of the AMD-640 system controller is guaranteed if the voltage and temperature parameters are within the limits defined in Table 8-2. Table 8-2. Parameter DD3 T CASE Notes 8-2 Preliminary Information Operating Ranges Minimum Typical 4.75 V 5.0 V 3.135 V 3 ...
Page 140
... V — The maximum power supply current must be taken into account when designing a power supply. DD3 4. Refers to inputs and I/O without an internal pullup resistor and 0 5. Refers to inputs with an internal pullup and V 6. Refers to inputs with an internal pulldown and V Electrical Data Preliminary Information AMD-640 System Controller Data Sheet Preliminary Data Min -0.50 V 2.0 V 2.0 V 2.4 V during functional operation ...
Page 141
... Preliminary Information = 3.3 V. DD3 Typical and Maximum Power Dissipation Clock Control State Typical (Note 1) 1.8 W system operation. listed clock control states. when designing a solution for thermal dissipation for the AMD-640 system controller proces- sor. 21090C/0—June 1997 DD Maximum Comments (Note 2) 2.5 W Note 3 0.21 W Note 4 0 ...
Page 142
... All signal slew rates are 1 V/ns, from (rising (falling). Parameters are within those listed in “Operating Ranges” on page 8-2. The load capacitance (C exception of maximum timings for clock, processor, DRAM and cache, where the C Switching Characteristics Preliminary Information AMD-640 System Controller Data Sheet ) on each signal with the pf. L 9-1 ...
Page 143
... CLK Switching Characteristics Table 9-1 and Table 9-2 contain the switching characteristics of the HCLK input to the AMD-640 system controller for 66-MHz and 60-MHz CPU bus operation, respectively. Table 9-3 contains the switching characteristics of the PCLK input for 33-MHz PCI bus operation. These timings are all measured with respect to the voltage levels indicated by Figure 9-1 on page 9-3 ...
Page 144
... Jitter frequency power spectrum peaking must occur at frequencies greater than (HCLK frequency)/3 or less than 500 KHz. Figure 9-1. CLK Waveform Switching Characteristics Preliminary Information Preliminary Data Min Max 0.15 ns 1.5 ns 250 ps Preliminary Data Min Max 30 ns 11 V/ns 4V/ns 1 V/ns 4V/ns 250 2.0 V 1 AMD-640 System Controller Data Sheet Figure Comments 9-1 Note 1 Figure Comments 9-1 9-1 9-1 9-1 Note 9-3 ...
Page 145
... Likewise, the minimum valid delay timings are used to analyze hold times. The setup and hold time requirements for the AMD-640 system controller input signals presented here must be met by any device that interfaces with it to assure the proper operation of the AMD-640 system controller ...
Page 146
... AHOLD BOFF# vd KEN#/INV EADS# BRDY#, NA# valid delay HA[31:3] valid delay HD[63:0] Valid delay t HA[31:3] float delay fd Notes: 1. Measurements are taken with no load. Switching Characteristics Preliminary Information AMD-640 System Controller Data Sheet Preliminary Data Min Max 1 1.5 ns ...
Page 147
... AMD-640 System Controller Data Sheet 9.4 PCI Interface Timing All of the following timings are relative to PCLK. Table 9-5. PCI Interface Timing Symbol Parameter Description AD[31:0] setup time PREQ#, REQ[3:0]# setup time Setup time for t su FRAME# STOP# TRDY# DEVSEL# IRDY# C/BE[3:0]# RESET# AD[31:0] hold time Hold time for ...
Page 148
... MA[1:0] valid delay MD[63:0] valid delay (SDRAM) MD[63:0] valid delay (EDO/FPM) t MA[11:0] Flow-through delay from ft HA for first read cycle Notes: 1. Measurements are taken with no load. Switching Characteristics Preliminary Information AMD-640 System Controller Data Sheet Preliminary Data Min Max 2 1 ...
Page 149
... AMD-640 System Controller Data Sheet 9.6 L2 Cache Timing All of the following timings are relative to HCLK. Table 9-7. L2 Cache Timing Symbol Parameter Description t TA9–TA0 setup time su t TA9–TA0 hold time h TA9–TA0 valid delay Valid delay for CE1 CADS t vd CADV COE, TAGWE valid delay ...
Page 150
... AMD has developed several I/O buffer models that represent the characteristics of each of the possible drive strength configurations supported by the AMD-640 system controller. AMD developed the models to allow system designers to perform analog simulations of AMD-640 system controller signals that interface with the rest of the system. Analog simulations are used to determine a signal’ ...
Page 151
... V/I tables contain sufficient data points for accurate representation of the nonlinear nature of the V/I curves. In addition, the voltage ranges provided in these tables extend beyond the normal operating range of the AMD-640 system controller to accommodate simulators that can yield more accurate results based on this wider range. ...
Page 152
... Controller I/O Model (IBIS) Application Note, order# (tbd). The Model is available at http://www.amd.com 10.4 I/O Buffer AC and DC Characteristics Refer to Section 9 for the AMD-640 system controller AC timing specifications. Refer to Section 8 for the AMD-640 system controller DC specifications. 10.5 References Ease System Simulation With IBIS Device Models by Syed Huq, Electronics Design, December 2, 1996 IBIS 2 ...
Page 153
... AMD-640 System Controller Data Sheet 10-4 Preliminary Information 21090C/0—June 1997 IBIS Models ...
Page 154
... Pin Numbering The following tables list the AMD-640 system controller pin names and their corresponding pin numbers. Table 11-1 groups the pins by function. Table 11-2 presents the pins as they appear on the 328-pin ball grid array. Pin Descriptions Preliminary Information ...
Page 155
... AMD-640 System Controller Data Sheet Table 11-1. Functional Grouping Host Address Host Data Pin Pin Pin Pin Name No. Name No. HA3 V-11 HD0 Y-1 Y-3 HA4 Y-11 HD1 HA5 U-8 HD2 Y-2 Y-4 HA6 Y-12 HD3 HA7 Y-8 HD4 W-1 HA8 V-8 HD5 W-2 HA9 V-7 HD6 V-1 R-1 HA10 Y-7 HD7 HA11 W-7 HD8 U-1 W-3 HA12 U-7 HD9 HA13 Y-6 HD10 V-3 HA14 ...
Page 156
... MD53 M-18 MD54 K-20 MD55 J-19 MD56 E-20 MD57 D-19 MD58 B-20 MD59 B-19 MD60 A-18 MD61 B-17 MD62 A-16 MD63 C-15 Pin Descriptions Preliminary Information AMD-640 System Controller Data Sheet DRAM Control Power Pin Pin Pin Pin Name No. Name No. V CAS7# L16 E14 DD CAS6# G16 G6 CAS5# J16 CAS4# H16 CAS3# L17 ...
Page 157
... AMD-640 System Controller Data Sheet 11-4 Preliminary Information 21090C/0—June 1997 Pin Descriptions ...
Page 158
... Package Specifications The AMD-640 system controller comes in a 328-pin plastic ball grid array (PBGA). The dimensions and thermal specification are shown below Table 12-1. Symbol Package Specifications Preliminary Information o <= 25 C/W = Not available. Replaced by 328-Pin BGA Package Preliminary Specification ...
Page 159
... AMD-640 System Controller Data Sheet Figure 12-1. 328-Pin BGA Package Preliminary Specification 12-2 Preliminary Information F 0.150 21090C/0—June 1997 ...