S2067TB AMCC (Applied Micro Circuits Corp), S2067TB Datasheet

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S2067TB

Manufacturer Part Number
S2067TB
Description
Communications, Dual Serial Backplane Device With Dual I/O
Manufacturer
AMCC (Applied Micro Circuits Corp)
Datasheet

Specifications of S2067TB

Case
BGA
Dc
01+

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FEATURES
APPLICATIONS
Figure 1. Typical Dual Gigabit Ethernet Application
DEVICE
SPECIFICATION
October 13, 2000 / Revision E
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O
High-speed data communications
• Broad operating rate range
• Dual Transmitter incorporating phase-locked
• Dual Receiver PLL provides independent clock
• Internally series terminated TTL outputs
• On-chip 8B/10B Line encoding and decoding for
• (2x8) bit parallel TTL interface
• Low-jitter serial PECL interface
• Local Loopback
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 1.6 W Power dissipation
• Compact 21mm x 21mm 156 TBGA package
• Redundant high speed transmit and receive
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
INTERFACE
ETHERNET
(0.77 GHz - 1.3 GHz)
- 1062 MHz (Fibre Channel)
- 1250 MHz (Gigabit Ethernet) line rates
- 1/2 Rate Operation
loop (PLL) clock synthesis from low speed
reference
and data recovery for each channel
2 separate parallel 8 bit channels
serial interfaces
GIGABIT
DUAL
GE INTERFACE
S2068
(ASIC)
(ASIC)
MAC
MAC
GENERAL DESCRIPTION
The S2067 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, Fibre Channel, serial backplanes, and pro-
prietary point to point links. The chip provides two
separate transceivers which can be operated indi-
vidually for a data capacity of >2 Gbit/sec in each
direction. The S2067 provides dual transmit and re-
ceive serial I/O. The dual transmit and receive serial
I/O are useful for backbone applications in which re-
dundant optical or electrical links are required.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel to serial and serial to parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip dual
receive PLL is used for clock recovery and data re-
timing on the two independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Re-
dundant transmit and receive serial I/O are provided
to support applications with redundant switch fabrics
or line interfaces. Local loopback mode allows for
system diagnostics. The chip requires a 3.3V power
supply and dissipates 1.6 watts.
Figure 1 shows the use of the S2067 and S2068 in a
Gigabit Ethernet application. Figure 2 shows the use of
a S2067 in a serial backplane application. Figure 3
summarizes the input and output signals on the S2067.
Figures 4 and 5 show the transmit and receive block
diagrams, respectively.
SERIAL BP DRIVER
S2067
TO SERIAL BACKPLANE
TO SERIAL BACKPLANE
S2067
S2067
®
1

Related parts for S2067TB

S2067TB Summary of contents

Page 1

DEVICE SPECIFICATION DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O FEATURES • Broad operating rate range (0.77 GHz - 1.3 GHz) - 1062 MHz (Fibre Channel) - 1250 MHz (Gigabit Ethernet) line rates - ...

Page 2

S2067 Figure 2. Typical Backplane Application MAC (ASIC) MAC ATM (ASIC) Fibre S2065 Channel Ethernet MAC etc. (ASIC) MAC (ASIC) MAC (ASIC) MAC ATM (ASIC) Fibre S2065 Channel Ethernet MAC etc. (ASIC) MAC (ASIC) 2 DUAL SERIAL BACKPLANE DEVICE WITH ...

Page 3

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 3. S2067 Input/Output Diagram RESET RATE REFCLK CLKSEL TMODE TCLKO DINA[0:7] 10 SOFA, KGENA TCLKA DINB[0:7] 10 SOFB, KGENB TCLKB ERRA DOUTA[0:7] 10 EOFA, KFLAGA RCA P/N ERRB DOUTB[0:7] 10 EOFB, KFLAGB ...

Page 4

S2067 Figure 4. Transmitter Block Diagram RATE REFCLK CLKSEL TMODE 8 DINA[0:7] FIFO SOFA (input) KGENA 0 1 TCLKA 8 DINB[0:7] FIFO (input) SOFB KGENB 0 1 TCLKB 4 DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O DIN PLL 10x/20x 10 ...

Page 5

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 5. Receiver Block Diagram RATE CMODE REFCLK EOFA KFLAGA FIFO (output) ERRA 8 DOUTA[0:7] 2 RCAP/N EOFB KFLAGB FIFO (output) ERRB 8 DOUTB[0:7] 2 RCBP/N LPEN October 13, 2000 / Revision E ...

Page 6

S2067 TRANSMITTER DESCRIPTION The transmitter section of the S2067 contains a single PLL which is used to generate the serial rate transmit clock for all transmitters. Two channels are provided with a variety of options regarding input clocking and loopback. ...

Page 7

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O The S2067 supports full and 1/2 rate operation for all modes of operation. When RATE is LOW, the S2067 serial data rate equals the VCO frequency. When RATE is HIGH, the VCO is ...

Page 8

S2067 Table 2. K Character Generation (SOFx = ...

Page 9

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Frequency Synthesizer (PLL) The S2067 synthesizes a serial transmit clock from the reference signal provided. The S2067 will obtain phase and frequency lock within 2500 bit times after the start of receiving reference ...

Page 10

S2067 Clock Recovery Function Clock recovery is performed on the input data stream for each channel of the S2067. The receiver PLL has been optimized for the anticipated needs of Serial Backplane systems. A simple state machine in the clock ...

Page 11

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O 8B/10B Decoding After performing serial-to-parallel conversion, the S2067 provides 8B/10B decoding of the data. The received 10-bit codeword is decoded to recover the original 8-bit data. The decoder also checks for er- rors ...

Page 12

S2067 OTHER OPERATING MODES Operating Frequency Range The S2067 is designed to operate at serial baud rates of 0.77 GHz to 1.3 GHz (616 Mbit/sec to 1040 Mbit/sec user data rate). The part is specified at the Fibre Channel rate ...

Page 13

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 9. Transmitter Input Signals Assignment and Description ...

Page 14

S2067 Table 10. Transmitter Output Signals Assignment and Description ...

Page 15

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 12. Receiver Output Signal Pin Assignment and Description ...

Page 16

S2067 Table 13. Receiver Input Signal Pin Assignment and Description ...

Page 17

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 15. Power and Ground Signals Pin Assignment and Description ...

Page 18

S2067 Figure 9. S2067 Pinout (Bottom View ...

Page 19

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 10. S2067 Pinout (Top View ...

Page 20

S2067 Figure 11. 156 TBGA Package Thermal Management Device S2067 20 DUAL SERIAL BACKPLANE DEVICE WITH DUAL I 19.8˚C/W 3.5˚C/W October 13, 2000 / Revision E ...

Page 21

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 12. Transmitter Timing (REFCLK Mode, TMODE =0) REFCLK DINx[0:7], SOFx, KGENx SERIAL DATA OUT Table 16. S2067 Transmitter Timing (REFCLK Mode, TMODE = ...

Page 22

S2067 Figure 14. Receiver Timing (Full Clock Mode, CMODE = 1) SERIAL DATA IN RCxN RCxP DOUTx[0:7], EOFx, KFLAGx, ERRx Table 18. S2067 Receiver Timing (Full Clock Mode, CMODE = ...

Page 23

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 16. TCLKO Timing REFCLK TCLKO Table 20. S2064 Transmitter (TCLKO Timing ...

Page 24

S2067 Table 21. Absolute Maximum Ratings ...

Page 25

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Table 24. Serial Data Timing, Transmit Outputs ...

Page 26

S2067 OUTPUT LOAD The S2067 serial outputs require a resistive load to set the output current. The recommended resistor value is 4 ground. This value can be varied to adjust drive current, signal voltage swing, and power usage ...

Page 27

DUAL SERIAL BACKPLANE DEVICE WITH DUAL I/O Figure 23. Loop Filter Capacitor Connections October 13, 2000 / Revision E 270 CAP1 22 nf CAP2 270 S2067 S2067 27 ...

Page 28

S2067 Ordering Information – Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 ...

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