DT28F320S5-70 Intel Corporation, DT28F320S5-70 Datasheet
DT28F320S5-70
Related parts for DT28F320S5-70
DT28F320S5-70 Summary of contents
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VOLT FlashFile™ MEMORY 28F160S5 and 28F320S5 (x8/x16) n Two 32-Byte Write Buffers 2 s per Byte Effective Programming Time n Operating Voltage Read Access Time (16 Mbit) 90 ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-4725 or call 1-800-548-4725 or visit Intel’s website at http:\\www.intel.com COPYRIGHT © INTEL CORPORATION 1997, 1998 *Third-party brands and names are the property of their respective owners. CG-041493 ...
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INTRODUCTION ........................................... 5 1.1 New Features............................................. 5 1.2 Product Overview....................................... 5 1.3 Pinout and Pin Description ......................... 6 2.0 PRINCIPLES OF OPERATION ..................... 9 2.1 Data Protection ........................................ 10 3.0 BUS OPERATION ....................................... 10 3.1 Read ........................................................ 10 3.2 ...
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REVISION HISTORY Number -001 Original version -002 Added commercial temperature information throughout the document. Updated address in Figure 5. Added descriptive information for CFI query to Section 4.2.5, System Interface Information Updated addresses and added descriptive information in Table ...
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INTRODUCTION This datasheet contains 5 Volt FlashFile™ memory (28F160S5, 28F320S5) specifications. Section 1.0 provides a flash memory overview. Sections 2.0 through 5.0 describe the memory organization and functionality. Section 6.0 covers specifications for extended temperature product offerings. Finally, Section ...
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Individual block locking uses a combination of block lock-bits to lock and unlock blocks. Block lock-bits gate block erase, full chip erase, program and write to buffer operations. Lock-bit configuration operations (Set Block Lock-Bit and Clear Block Lock-Bits commands) ...
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Table 1. Pin Descriptions Sym Type A –A INPUT ADDRESS INPUTS: Address inputs for read and write operations are internally 0 21 latched during a write cycle x16 mode not used; input buffer is off. 0 ...
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This code is copied to and executed from system RAM during flash memory updates. successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software ...
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Output Disable With OE logic-high level (V ), the device IH outputs are disabled. Output pins DQ –DQ 0 placed in a high-impedance state. 3.3 Standby logic-high level (V ) ...
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A[ ]: 16-Mbit 20 32-Mbit 21-1 Word (Subsequent Blocks) Address 0FFFF Block 1 Reserved for Future Implementation 08004 08003 Block 1 Lock Configuration 08002 Reserved for Future Implementation 08000 07FFF Block 0 Reserved for Future Implementation 00004 ...
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Table 2. Bus Operations Mode Notes RP Read 1 Output Disable Standby Reset/Power Down Mode Read Identifier ...
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Table 3. 5 Volt FlashFile™ Memory (28F160S5, 28F320S5) Command Set Definitions Command Scaleable Bus or Basic Cycles Command Req'd Set (14) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS Read Query SCS Read Status Register SCS/BCS 2 Clear Status ...
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NOTES: 1. Bus operations are defined in Table Any valid address within the device Address within the block being erased or locked Identifier Code Address: see Table 12 Query database ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads ...
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Table 4. Summary of Query Structure Output as a Function of Device and Mode Device Type/Mode Word Addressing Location x16 device/ 10h x16 mode 11h 12h x16 device/ N/A (1) x8 mode NOTE: 1. The system must drive the lowest ...
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QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized in Table 8. The following sections describe the Query ...
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BLOCK STATUS REGISTER The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. Table 7. Block Status Register Offset Length (bytes) (1) (BA+2)h ...
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CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor- specified command set(s) is (are) supported. Table 8. CFI ...
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SYSTEM INTERFACE INFORMATION The following device information can be useful in optimizing system interface software. Table 9. System Interface Information Offset Length (bytes) 1Bh 01h V Logic Supply Minimum Program/Erase Voltage CC bits 7–4 BCD volts bits 3–0 BCD ...
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DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 10. Device Geometry Definition Offset Length Description (bytes) 27h 01h Device Size = Number of Bytes 28h 02h Flash Device Interface ...
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INTEL-SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Intel-Specific Extended Query table specifies this and other similar types of information. Table 11. Primary-Vendor Specific Extended Query Offset (1) Length (bytes) (P)h 03h Primary Extended Query ...
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Table 11. Primary-Vendor Specific Extended Query (Continued) Offset Length (bytes) (P+C)h 01h V Logic Supply Optimum Program/Erase voltage CC (highest performance) bits 7–4 bits 3–0 (P+D)h 01h V [Programming] Supply Optimum Program/Erase PP voltage bits 7–4 bits 3–0 (P+E)h ...
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Following a program, block erase, set block lock-bit, or clear block lock-bits command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ and DQ are invalid. When the 0-6 8-15 ...
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This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Full Chip Erase command sequence will result in both status register bits SR.4 and SR.5 being set to 1. Also, ...
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status register bits PP PPLK SR.4 and SR.3 will be set to “1.” Successful byte/word programming requires corresponding block lock-bit be cleared byte/word program is attempted when corresponding block lock-bit is set and ...
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The only other valid commands while programming is suspended are Read Status Register and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. Status register bits SR.2 and SR.7 will automatically ...
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Table 13. Write Protection Alternatives Block Operation Lock- WP# Bit Program and Block Erase Full Chip Erase 0 Set or Clear ...
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Table 15. Status Register Definition WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block erase suspended 0 = Block erase in progress/completed ...
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Start Set Time-Out Issue Write Command No E8H, Block Address Read Extended Status Register 0 Write XSR.7 = Buffer Time-Out? 1 Write Word or Byte Count, Block Address Write Buffer Data, Start Address Yes Check X = ...
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Start Write 40H, Address Write Data and Address Read Status Register No Suspend 0 SR.7 = Byte/Word Program 1 Full Status Check if Desired Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 ...
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Start Write B0H Read Status Register 0 SR SR.2 = Programming Completed 1 Write FFH Read Data Array No Done Reading Yes Write D0H Write FFH Programming Resumed Read Array Data Figure 8. Program Suspend/Resume Flowchart PRELIMINARY ...
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Start Device Supports Queuing Yes Set Time-Out Issue Block Queue Erase Command 28H, Block Address No Read Extended Status Register Is Queue Erase Block 0=No Available? Time-Out? XSR.7= 1=Yes Another Block Erase? Yes Yes Issue Erase Command 28H Block ...
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Start Write B0H Read Status Register 0 SR SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Program No Data Loop Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data ...
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Start Write 60H, Block/Device Address Write 01H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = Voltage Range Error 0 1 SR. ...
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DESIGN CONSIDERATIONS 5.1 Three-Line Output Control Intel provides three control inputs to accommodate multiple memory connections ( OE#, and RP#. Three-line control provides for: a. Lowest possible memory power dissipation; b. Data bus contention ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Temperature under Bias Commercial ............................... 0 °C to +70 °C Extended .............................. –40 °C to +85 °C Storage Temperature................. –65 °C to +125 °C Voltage On Any Pin (except V and V ) ...
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Capacitance T = +25 ° MHz A Symbol Parameter C Input Capacitance IN C Output Capacitance OUT NOTE: 1. Sampled, not 100% tested. 6.4 DC Characteristics – +85 ...
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DC Characteristics (Continued – +85 C (Extended) and T A Sym Parameter I V Programming and Set CCW CC Lock-Bit Current I V Block Erase or Clear Block CCE CC Lock-Bits Current I ...
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DC Characteristics (Continued – +85 C (Extended) and T A Sym Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage (TTL) ...
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Input 1.5 0.0 AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to ...
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AC Characteristics—Read-Only Operations – +85 C (Extended) and T A Versions (4) (All units in ns unless otherwise noted) # Sym Parameter R1 t Read/Write Cycle Time AVAV R2 t Address to ...
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Device Standby Address Selection V IH ADDRESSES ( ( OE# ( WE# ( DATA (D/Q) High Z (DQ0-DQ15 ...
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AC Characteristics—Write Operations – +85 C (Extended) and T A Versions (6) # Sym RP# High Recovery to WE# (CE ) PHWL PHEL Setup ...
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ADDRESSES [ (WE#) [E(W OE# [ WE# (CE #) [W(E ...
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V IH STS ( RP# ( CC1 Figure 18. AC Waveform for Reset Operation Table 18. Reset AC Specifications # Sym Parameter P1 t RP# ...
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Erase, Write, and Lock-Bit Configuration Performance 5 V ± 5 ± 10 Version # Sym W16 Byte/word program time (using write buffer) W16 t Per byte program time (without write buffer) WHQV1 t EHQV1 W16 ...
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... Product Line Designator for all Intel Flash products Device Density 160 = 16 Mbit 320 = 32 Mbit Order Code by Density TE28F160S5-70 TE28F160S5-100 DT28F160S5-70 DT28F320S5-90 DT28F160S5-100 DT28F320S5-110 50 Access Speed (ns) Device Type Product Family S = FlashFile™ Memory Valid Operational Combinations 10 ...
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ADDITIONAL INFORMATION (1,2) Order Number 290608 3 Volt FlashFile™ Memory; 28F160S3 and 28F320S3 datasheet AP-646 Common Flash Interface and Command Sets 292204 292203 AP-645 3 Volt and 5 Volt FlashFile™ Memory Migration Guide 292163 AP-610 Flash Memory In-System Code ...